1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * Copyright (c) 2015 The University of Bologna 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Steve Reinhardt 43 * Andreas Hansson 44 * Erfan Azarkhish 45 */ 46 47/** 48 * @file 49 * Declaration of the SerialLink Class, modeling Hybrid-Memory-Cube's serial 50 * interface. 51 */ 52 53#ifndef __MEM_SERIAL_LINK_HH__ 54#define __MEM_SERIAL_LINK_HH__ 55 56#include <deque> 57 58#include "base/types.hh" 59#include "mem/port.hh" 60#include "params/SerialLink.hh" 61#include "sim/clocked_object.hh" 62 63/** 64 * SerialLink is a simple variation of the Bridge class, with the ability to 65 * account for the latency of packet serialization. We assume that the 66 * serializer component at the transmitter side does not need to receive the 67 * whole packet to start the serialization. But the deserializer waits for the 68 * complete packet to check its integrity first. 69 */ 70class SerialLink : public ClockedObject 71{ 72 protected: 73 74 /** 75 * A deferred packet stores a packet along with its scheduled 76 * transmission time 77 */ 78 class DeferredPacket 79 { 80 81 public: 82 83 const Tick tick; 84 const PacketPtr pkt; 85 86 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) 87 { } 88 }; 89 90 // Forward declaration to allow the slave port to have a pointer 91 class SerialLinkMasterPort; 92 93 /** 94 * The port on the side that receives requests and sends 95 * responses. The slave port has a set of address ranges that it 96 * is responsible for. The slave port also has a buffer for the 97 * responses not yet sent. 98 */ 99 class SerialLinkSlavePort : public SlavePort 100 { 101 102 private: 103 104 /** The serial_link to which this port belongs. */ 105 SerialLink& serial_link; 106 107 /** 108 * Master port on the other side of the serial_link. 109 */ 110 SerialLinkMasterPort& masterPort; 111 112 /** Minimum request delay though this serial_link. */ 113 const Cycles delay; 114 115 /** Address ranges to pass through the serial_link */ 116 const AddrRangeList ranges; 117 118 /** 119 * Response packet queue. Response packets are held in this 120 * queue for a specified delay to model the processing delay 121 * of the serial_link. We use a deque as we need to iterate over 122 * the items for functional accesses. 123 */ 124 std::deque<DeferredPacket> transmitList; 125 126 /** Counter to track the outstanding responses. */ 127 unsigned int outstandingResponses; 128 129 /** If we should send a retry when space becomes available. */ 130 bool retryReq; 131 132 /** Max queue size for reserved responses. */ 133 unsigned int respQueueLimit; 134 135 /** 136 * Is this side blocked from accepting new response packets. 137 * 138 * @return true if the reserved space has reached the set limit 139 */ 140 bool respQueueFull() const; 141 142 /** 143 * Handle send event, scheduled when the packet at the head of 144 * the response queue is ready to transmit (for timing 145 * accesses only). 146 */ 147 void trySendTiming(); 148 149 /** Send event for the response queue. */ 150 EventFunctionWrapper sendEvent; 151 152 public: 153 154 /** 155 * Constructor for the SerialLinkSlavePort. 156 * 157 * @param _name the port name including the owner 158 * @param _serial_link the structural owner 159 * @param _masterPort the master port on the other side of the 160 * serial_link 161 * @param _delay the delay in cycles from receiving to sending 162 * @param _resp_limit the size of the response queue 163 * @param _ranges a number of address ranges to forward 164 */ 165 SerialLinkSlavePort(const std::string& _name, SerialLink& 166 _serial_link, SerialLinkMasterPort& _masterPort, 167 Cycles _delay, int _resp_limit, const 168 std::vector<AddrRange>& _ranges); 169 170 /** 171 * Queue a response packet to be sent out later and also schedule 172 * a send if necessary. 173 * 174 * @param pkt a response to send out after a delay 175 * @param when tick when response packet should be sent 176 */ 177 void schedTimingResp(PacketPtr pkt, Tick when); 178 179 /** 180 * Retry any stalled request that we have failed to accept at 181 * an earlier point in time. This call will do nothing if no 182 * request is waiting. 183 */ 184 void retryStalledReq(); 185 186 protected: 187 188 /** When receiving a timing request from the peer port, 189 pass it to the serial_link. */ 190 bool recvTimingReq(PacketPtr pkt); 191 192 /** When receiving a retry request from the peer port, 193 pass it to the serial_link. */ 194 void recvRespRetry(); 195 196 /** When receiving a Atomic requestfrom the peer port, 197 pass it to the serial_link. */ 198 Tick recvAtomic(PacketPtr pkt); 199 200 /** When receiving a Functional request from the peer port, 201 pass it to the serial_link. */ 202 void recvFunctional(PacketPtr pkt); 203 204 /** When receiving a address range request the peer port, 205 pass it to the serial_link. */ 206 AddrRangeList getAddrRanges() const; 207 }; 208 209 210 /** 211 * Port on the side that forwards requests and receives 212 * responses. The master port has a buffer for the requests not 213 * yet sent. 214 */ 215 class SerialLinkMasterPort : public MasterPort 216 { 217 218 private: 219 220 /** The serial_link to which this port belongs. */ 221 SerialLink& serial_link; 222 223 /** 224 * The slave port on the other side of the serial_link. 225 */ 226 SerialLinkSlavePort& slavePort; 227 228 /** Minimum delay though this serial_link. */ 229 const Cycles delay; 230 231 /** 232 * Request packet queue. Request packets are held in this 233 * queue for a specified delay to model the processing delay 234 * of the serial_link. We use a deque as we need to iterate over 235 * the items for functional accesses. 236 */ 237 std::deque<DeferredPacket> transmitList; 238 239 /** Max queue size for request packets */ 240 const unsigned int reqQueueLimit; 241 242 /** 243 * Handle send event, scheduled when the packet at the head of 244 * the outbound queue is ready to transmit (for timing 245 * accesses only). 246 */ 247 void trySendTiming(); 248 249 /** Send event for the request queue. */ 250 EventFunctionWrapper sendEvent; 251 252 public: 253 254 /** 255 * Constructor for the SerialLinkMasterPort. 256 * 257 * @param _name the port name including the owner 258 * @param _serial_link the structural owner 259 * @param _slavePort the slave port on the other side of the 260 * serial_link 261 * @param _delay the delay in cycles from receiving to sending 262 * @param _req_limit the size of the request queue 263 */ 264 SerialLinkMasterPort(const std::string& _name, SerialLink& 265 _serial_link, SerialLinkSlavePort& _slavePort, Cycles 266 _delay, int _req_limit); 267 268 /** 269 * Is this side blocked from accepting new request packets. 270 * 271 * @return true if the occupied space has reached the set limit 272 */ 273 bool reqQueueFull() const; 274 275 /** 276 * Queue a request packet to be sent out later and also schedule 277 * a send if necessary. 278 * 279 * @param pkt a request to send out after a delay 280 * @param when tick when response packet should be sent 281 */ 282 void schedTimingReq(PacketPtr pkt, Tick when); 283 284 /** 285 * Check a functional request against the packets in our 286 * request queue. 287 * 288 * @param pkt packet to check against 289 * 290 * @return true if we find a match 291 */ 292 bool trySatisfyFunctional(PacketPtr pkt); 293 294 protected: 295 296 /** When receiving a timing request from the peer port, 297 pass it to the serial_link. */ 298 bool recvTimingResp(PacketPtr pkt); 299 300 /** When receiving a retry request from the peer port, 301 pass it to the serial_link. */ 302 void recvReqRetry(); 303 }; 304 305 /** Slave port of the serial_link. */ 306 SerialLinkSlavePort slavePort; 307 308 /** Master port of the serial_link. */ 309 SerialLinkMasterPort masterPort; 310 311 /** Number of parallel lanes in this serial link */ 312 unsigned num_lanes; 313 314 /** Speed of each link (Gb/s) in this serial link */ 315 uint64_t link_speed; 316 317 public: 318 319 Port &getPort(const std::string &if_name, 320 PortID idx=InvalidPortID); 321 322 virtual void init(); 323 324 typedef SerialLinkParams Params; 325 326 SerialLink(SerialLinkParams *p); 327}; 328 329#endif //__MEM_SERIAL_LINK_HH__ 330