| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | exit_gen.hh | 59 ExitGen(SimObject &obj, MasterID master_id, Tick _duration) argument
60 : BaseGen(obj, master_id, _duration)
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| H A D | idle_gen.hh | 64 IdleGen(SimObject &obj, MasterID master_id, Tick _duration) argument
65 : BaseGen(obj, master_id, _duration)
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| H A D | linear_gen.hh | 75 * @param master_id MasterID related to the memory requests
87 MasterID master_id, Tick _duration,
92 : StochasticGen(obj, master_id, _duration, start_addr, end_addr,
86 LinearGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument
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| H A D | random_gen.hh | 83 MasterID master_id, Tick _duration,
88 : StochasticGen(obj, master_id, _duration, start_addr, end_addr,
82 RandomGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument
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| H A D | base_gen.cc | 54 BaseGen::BaseGen(SimObject &obj, MasterID master_id, Tick _duration) argument
55 : _name(obj.name()), masterID(master_id),
84 MasterID master_id, Tick _duration,
89 : BaseGen(obj, master_id, _duration),
83 StochasticGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument
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| H A D | dram_rot_gen.hh | 70 * @param master_id MasterID related to the memory requests
90 DramRotGen(SimObject &obj, MasterID master_id, Tick _duration, argument
100 : DramGen(obj, master_id, _duration, start_addr, end_addr,
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| H A D | trace_gen.hh | 156 * @param master_id MasterID related to the memory requests
161 TraceGen(SimObject &obj, MasterID master_id, Tick _duration, argument
163 : BaseGen(obj, master_id, _duration),
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| H A D | dram_gen.hh | 71 * @param master_id MasterID related to the memory requests
91 MasterID master_id, Tick _duration,
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| H A D | base_gen.hh | 93 * @param master_id MasterID set on each request
96 BaseGen(SimObject &obj, MasterID master_id, Tick _duration);
141 MasterID master_id, Tick _duration,
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| H A D | dram_gen.cc | 53 MasterID master_id, Tick _duration,
63 : RandomGen(obj, master_id, _duration, start_addr, end_addr,
52 DramGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, unsigned int addr_mapping, unsigned int nbr_of_ranks) argument
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| /gem5/src/mem/ |
| H A D | mem_master.hh | 58 MasterID master_id)
59 : obj(_obj), masterName(master_name), masterId(master_id)
56 MasterInfo(const SimObject* _obj, std::string master_name, MasterID master_id) argument
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| /gem5/src/mem/cache/tags/ |
| H A D | base.cc | 109 MasterID master_id = pkt->req->masterId(); local
110 assert(master_id < system->maxMasters());
111 occupancies[master_id]++;
114 blk->insert(extractTag(pkt->getAddr()), pkt->isSecure(), master_id, local
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| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.hh | 430 MasterPort& _port, MasterID master_id,
434 masterID(master_id),
857 MasterPort& _port, MasterID master_id,
861 masterID(master_id),
429 FixedRetryGen(TraceCPU& _owner, const std::string& _name, MasterPort& _port, MasterID master_id, const std::string& trace_file) argument
856 ElasticDataGen(TraceCPU& _owner, const std::string& _name, MasterPort& _port, MasterID master_id, const std::string& trace_file, TraceCPUParams *params) argument
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| /gem5/src/sim/ |
| H A D | system.cc | 580 MasterID master_id = masters.size();
583 masters.emplace_back(master, name, master_id);
601 System::getMasterName(MasterID master_id)
603 if (master_id >= masters.size())
604 fatal("Invalid master_id passed to getMasterName()\n");
606 const auto& master_info = masters[master_id];
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| H A D | system.hh | 385 std::string getMasterName(MasterID master_id);
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| /gem5/src/mem/cache/prefetch/ |
| H A D | stride.cc | 153 MasterID master_id = useMasterId ? pfi.getMasterId() : 0; local
156 PCTable* pcTable = findTable(master_id);
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| /gem5/src/arch/arm/ |
| H A D | tlb.hh | 228 void setMMU(Stage2MMU *m, MasterID master_id);
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| H A D | table_walker.hh | 914 void setMMU(Stage2MMU *m, MasterID master_id);
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| H A D | tlb.cc | 111 TLB::setMMU(Stage2MMU *m, MasterID master_id) argument
114 tableWalker->setMMU(m, master_id);
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| H A D | table_walker.cc | 102 TableWalker::setMMU(Stage2MMU *m, MasterID master_id) argument
106 masterId = master_id;
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