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13752:135bb759ee9c |
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08-Mar-2019 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"
Reverting patch due to polymorphism limitations.
This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb.
Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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13419:aaadcfae091a |
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13-Nov-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Remove Cache dependency from Tags
Tags do not need to be aware of caches.
Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14296 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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13418:08101e89101e |
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18-Oct-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Move access latency calculation to Cache
Access latency was not being calculated properly, as it was always assuming that for hits reads take as long as writes, and that parallel accesses would produce the same latency for read and write misses.
By moving the calculation to the Cache we can use the write/ read information, reduce latency variables duplication and remove Cache dependency from Tags.
The tag lookup latency is still calculated by the Tags.
Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13697 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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13225:8d1621fc586e |
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11-Oct-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Factor ReplaceableEntry out
ReplaceableEntry is referenced by many classes that do not necessarily need access to the replacement policies. Therefore, in order to allow better compilation units, we factor it out to a new file.
Change-Id: I0823567bf1ca336ffcdf783682ef473e8878d7fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13418 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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13222:0dbcc7d7d66f |
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10-Oct-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Virtualize block print
Encapsulate and virtualize block print, so that relevant information can be easily printed anywhere.
Change-Id: I91109c29c126755183a0fd2b4446f5335e64076b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13415 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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13219:454ecc63338d |
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09-Mar-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Split Tags for indexing policies
Split indexing functionality from tags, so that code duplication is reduced when adding new classes that use different indexing policies, such as set associative, skewed associative or other hash-based policies.
An indexing policy defines the mapping between an address' set and its physical location. For example, a conventional set assoc cache maps an address to all ways in a set using an immutable function, that is, a set x is always mapped to set x. However, skewed assoc caches map an address to a different set for each way, using a skewing function.
FALRU has been left unmodified as it is a specialization with its own complexity.
Change-Id: I0838b41663f21eba0aeab7aeb7839e3703ca3324 Reviewed-on: https://gem5-review.googlesource.com/c/8885 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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13218:5e7df60c6cab |
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07-Sep-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Use set and way for ReplaceableEntry
Replaceable entries belong to table-like structures, and therefore they should be indexable by combining a row and a column. These, using conventional cache nomenclature translate to sets and ways.
Make these entries aware of their sets and ways. The idea is to make indexing policies usable by other table-like structures. In order to do so we move sets and ways to ReplaceableEntry, which will be the common base among table entries.
Change-Id: If0e3dacf9ea2f523af9cface067469ccecf82648 Reviewed-on: https://gem5-review.googlesource.com/c/12764 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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13217:725b1701b4ee |
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09-Mar-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Use possible locations to find block
Use possible locations to find block to make it placement policy independent.
Change-Id: I4c9d9e1e1ff91ce12e85ca1970f927d8f4f5a93b Reviewed-on: https://gem5-review.googlesource.com/c/8884 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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13215:82cdb8db4643 |
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06-Jun-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Remove Packet dependency in Tags
Decouple Tags from Packets, only extracting the necessary functionality for block insertion. As a side effect, create a new function to update common insertion statistics.
Change-Id: I5c58f7c17de3255beee531f72a3fd25a30d74c90 Reviewed-on: https://gem5-review.googlesource.com/c/11098 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12753:fe5b2dbe42bb |
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06-Jun-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Make packet const in insertBlock
The packet should not be modified within insertBlock.
Change-Id: If7d2b01fe131f9923194efd155c9e85eeab24d5a Reviewed-on: https://gem5-review.googlesource.com/10811 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12745:e28c117a9806 |
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02-Jun-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Move tagsInUse to children
Move tagsInUse to children, as sector caches have different tag invalidation and insertion, and thus they must handle updating this variable.
Change-Id: I875c9b7364a909c76daf610d1e226c4e82063870 Reviewed-on: https://gem5-review.googlesource.com/10721 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12728:57bdea4f96aa |
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30-May-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem-cache: Replace block visitor with std::function
This change modifies forEachBlk tags function to accept std::function as parameter. It also adds an anyBlk tags function that given a condition, it iterates through the blocks and returns whether the condition is met.
Finally, it uses forEachBlk to implement the print, computeStats and cleanupRefs functions that also work for the FALRU class.
Change-Id: I2f75f4baa1fdd5a1d343a63ecace3eb9458fbf03 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10621 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12727:56c23b54bcb1 |
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02-May-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem-cache: Fix include directives in the cache related classes
Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c Reviewed-on: https://gem5-review.googlesource.com/10433 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12722:d84f756891fe |
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10-May-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem-cache: Delegate block invalidation to block allocation
For a block replacement we first select a victim block, we invalidate it and then populate it with the new information. Prior to this change BaseTags::insertBlock() did the invalidation and filled in the block with the new information. Now that the replacements stat is moved to the BaseCache, insertBlock does not need to perform the invalidation and as a result we can unify the block eviction code in BaseCache.
Change-Id: I5bdf00b2dab2752ed2137ab7201ed1dc451333b3 Reviewed-on: https://gem5-review.googlesource.com/10429 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
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12704:4d2bcc64d469 |
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10-May-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem-cache: Move reference count stats update to blk invalidation
The tags in the cache keep track of the number of references to the blocks as well as the average number of references between an insertion and the next invalidation. Previously the stats where updated only on block insertion and invalidations were ignored. This changes moves the update of the counters to the block invalidation function.
Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612 Reviewed-on: https://gem5-review.googlesource.com/10428 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
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12703:2d0e4d2d76b3 |
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10-May-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem-cache: Remove isTouched field from the CacheBlk
At the moment isTouched is used in the warm-up detection mechanism but it keeps track of the same information as isValid(). This change removes it and substitutes its use by isValid().
Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62 Reviewed-on: https://gem5-review.googlesource.com/10427 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
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12702:27cb33a96e0f |
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10-May-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem-cache: Move replacements stat to the base cache class
Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110 Reviewed-on: https://gem5-review.googlesource.com/10426 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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12691:8e1371fde4be |
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13-Apr-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Create block insertion function
Create a block insertion function to be used when inserting blocks. This resets the number of references to 1 (the insertion is taken into account), sets the insertion tick, and set secure state.
Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e Reviewed-on: https://gem5-review.googlesource.com/9824 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12684:44ebd2bc020f |
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27-Mar-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: ReplacementPolicy specific replacement data
Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy.
Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData.
Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state.
An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure.
Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12637:bfc3cb9c7e6c |
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30-Mar-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem: Remove unused 'using namespace'
Removal of unused/barely used 'using namespace' from C++ files.
Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a Reviewed-on: https://gem5-review.googlesource.com/9601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12636:9859213e2662 |
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09-Mar-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Move insertBlock functionality in FALRU
Block insertion is being done in the getCandidates function, while the insertBlock function does not do anything.
Besides, BaseTags' stats weren't being updated.
Change-Id: Iadab9c1ea61519214f66fa24c4b91c4fc95604c0 Reviewed-on: https://gem5-review.googlesource.com/8882 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12629:c17d4dc2379e |
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22-Mar-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Fix FALRU data block seg fault
FALRU didn't initialize the blocks' data, causing seg faults. This patch does not make FALRU functional yet.
Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b Reviewed-on: https://gem5-review.googlesource.com/9302 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12548:285f1792a2da |
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26-Feb-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Vectorize C arrays in BaseSetAssoc.
Transform BaseSetAssoc's arrays into C++ vectors to avoid unnecessary resource management.
Change-Id: I656f42f29e5f9589eba491b410ca1df5a64f2f34 Reviewed-on: https://gem5-review.googlesource.com/8621 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12513:4dfc54394b5a |
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07-Feb-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem-cache: Make cache warmup percentage a parameter.
The warmupPercentage is the percentage of different tags (based on the cache size) that need to be touched in order to warm up the cache. If Warmup failed (i.e., not enough tags were touched), warmup_cycle = 0.
The warmup is not being taken into account to calculate the stats (i.e., stats acquisition starts before cache is warmed up). Maybe in the future this functionality should be added.
Change-Id: I2b93a99c19fddb99a4c60e6d4293fa355744d05e Reviewed-on: https://gem5-review.googlesource.com/8061 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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11893:3033b3e6a32a |
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30-Oct-2016 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem: Make blkAlign a common function between all tag classes
blkAlign was defined as a separate function in the base associative and fully-associative tags classes although both functions implemented identical functionality. This patch moves the blkAlign in the base tags class.
Change-Id: I3d415d0e62bddeec7ce0d559667e40a8c5fdc2d4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
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11722:f15f02d8c79e |
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30-Nov-2016 |
Sophiane Senni <sophiane.senni@gmail.com> |
mem: Split the hit_latency into tag_latency and data_latency
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
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11522:348411ec525a |
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06-Jun-2016 |
Stephan Diestelhorst <stephan.diestelhorst@arm.com> |
sim: Call regStats of base-class as well
We want to extend the stats of objects hierarchically and thus it is necessary to register the statistics of the base-class(es), as well. For now, these are empty, but generic stats will be added there.
Patch originally provided by Akash Bagdia at ARM Ltd.
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11486:f09bb73b3050 |
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26-May-2016 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem: fix headers include order in the cache related classes
Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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10693:c0979b2ebda5 |
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11-Feb-2015 |
Marco Balboni <Marco.Balboni@ARM.com> |
mem: Clarify usage of latency in the cache
This patch adds some much-needed clarity in the specification of the cache timing. For now, hit_latency and response_latency are kept as top-level parameters, but the cache itself has a number of local variables to better map the individual timing variables to different behaviours (and sub-components).
The introduced variables are: - lookupLatency: latency of tag lookup, occuring on any access - forwardLatency: latency that occurs in case of outbound miss - fillLatency: latency to fill a cache block We keep the existing responseLatency
The forwardLatency is used by allocateInternalBuffer() for: - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); - MSHR allocateMissBuffer (cacheable miss in MSHR queue); - MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR queue) It is our assumption that the time for the above three buffers is the same. Similarly, for snoop responses passing through the cache we use forwardLatency.
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10466:73b7549d979e |
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16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA.
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10360:919c02740209 |
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09-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
misc: Fix a number of unitialised variables and members
Static analysis unearther a bunch of uninitialised variables and members, and this patch addresses the problem. In all cases these omissions seem benign in the end, but at least fixing them means less false positives next time round.
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10025:fdf737112e46 |
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24-Jan-2014 |
Timothy M. Jones <timothy.jones@arm.com> |
Cache: Collect very basic stats on tag and data accesses
Adds very basic statistics on the number of tag and data accesses within the cache, which is important for power modelling. For the tags, simply count the associativity of the cache each time. For the data, this depends on whether tags and data are accessed sequentially, which is given by a new parameter. In the parallel case, all data blocks are accessed each time, but with sequential accesses, a single data block is accessed only on a hit.
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10024:fc10e1f9f124 |
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24-Jan-2014 |
Dam Sunwoo <dam.sunwoo@arm.com> |
mem: per-thread cache occupancy and per-block ages
This patch enables tracking of cache occupancy per thread along with ages (in buckets) per cache blocks. Cache occupancy stats are recalculated on each stat dump.
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9850:87d6b41749e9 |
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04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it.
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9796:485399270ca1 |
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27-Jun-2013 |
Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> |
mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to implement new replacement policies. The base tags class is now a clocked object so that derived classes can use a clock if they need one. Also having deriving from SimObject allows specialized Tag classes to be swapped in/out in .py files.
The cache set is now templatized to allow it to contain customized cache blocks with additional informaiton. This involved moving code to the .hh file and removing cacheset.cc.
The statistics belonging to the cache tags are now including ".tags" in their name. Hence, the stats need an update to reflect the change in naming.
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8833:2870638642bd |
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12-Feb-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
mem: fix cache stats to use request ids correctly
This patch fixes the cache stats to use the new request ids. Cache stats also display the requestor names in the vector subnames. Most cache stats now include "nozero" and "nonan" flags to reduce the amount of excessive cache stat dump. Also, simplified incMissCount()/incHitCount() functions.
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8240:38befb82b2c9 |
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19-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
stats: rename stats so they can be used as python expressions
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8229:78bf55f23338 |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes
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6979:7732bca47f60 |
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24-Feb-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
cache stats: account for writebacks and/or device occupancy in the cache. Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
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6978:ab05e20dc4a7 |
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23-Feb-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
cache: Make caches sharing aware and add occupancy stats. On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0).
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5338:e75d02a09806 |
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10-Feb-2008 |
Steve Reinhardt <stever@gmail.com> |
Fix #include lines for renamed cache files.
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5337:f81512eb8bdf |
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10-Feb-2008 |
Steve Reinhardt <stever@gmail.com> |
Rename cache files for brevity and consistency with rest of tree.
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