base.cc revision 13222:0dbcc7d7d66f 
1/*
2 * Copyright (c) 2013,2016,2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Definitions of BaseTags.
47 */
48
49#include "mem/cache/tags/base.hh"
50
51#include <cassert>
52
53#include "base/types.hh"
54#include "mem/cache/base.hh"
55#include "mem/cache/tags/indexing_policies/base.hh"
56#include "mem/request.hh"
57#include "sim/core.hh"
58#include "sim/sim_exit.hh"
59#include "sim/system.hh"
60
61BaseTags::BaseTags(const Params *p)
62    : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
63      size(p->size),
64      lookupLatency(p->tag_latency),
65      accessLatency(p->sequential_access ?
66                    p->tag_latency + p->data_latency :
67                    std::max(p->tag_latency, p->data_latency)),
68      cache(nullptr), indexingPolicy(p->indexing_policy),
69      warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)),
70      warmedUp(false), numBlocks(p->size / p->block_size),
71      dataBlks(new uint8_t[p->size]) // Allocate data storage in one big chunk
72{
73}
74
75void
76BaseTags::setCache(BaseCache *_cache)
77{
78    assert(!cache);
79    cache = _cache;
80}
81
82ReplaceableEntry*
83BaseTags::findBlockBySetAndWay(int set, int way) const
84{
85    return indexingPolicy->getEntry(set, way);
86}
87
88CacheBlk*
89BaseTags::findBlock(Addr addr, bool is_secure) const
90{
91    // Extract block tag
92    Addr tag = extractTag(addr);
93
94    // Find possible entries that may contain the given address
95    const std::vector<ReplaceableEntry*> entries =
96        indexingPolicy->getPossibleEntries(addr);
97
98    // Search for block
99    for (const auto& location : entries) {
100        CacheBlk* blk = static_cast<CacheBlk*>(location);
101        if ((blk->tag == tag) && blk->isValid() &&
102            (blk->isSecure() == is_secure)) {
103            return blk;
104        }
105    }
106
107    // Did not find block
108    return nullptr;
109}
110
111void
112BaseTags::insertBlock(const Addr addr, const bool is_secure,
113                      const int src_master_ID, const uint32_t task_ID,
114                      CacheBlk *blk)
115{
116    assert(!blk->isValid());
117
118    // Previous block, if existed, has been removed, and now we have
119    // to insert the new one
120    // Deal with what we are bringing in
121    assert(src_master_ID < cache->system->maxMasters());
122    occupancies[src_master_ID]++;
123
124    // Insert block with tag, src master id and task id
125    blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID);
126
127    // Check if cache warm up is done
128    if (!warmedUp && tagsInUse.value() >= warmupBound) {
129        warmedUp = true;
130        warmupCycle = curTick();
131    }
132
133    // We only need to write into one tag and one data block.
134    tagAccesses += 1;
135    dataAccesses += 1;
136}
137
138Addr
139BaseTags::extractTag(const Addr addr) const
140{
141    return indexingPolicy->extractTag(addr);
142}
143
144void
145BaseTags::cleanupRefsVisitor(CacheBlk &blk)
146{
147    if (blk.isValid()) {
148        totalRefs += blk.refCount;
149        ++sampledRefs;
150    }
151}
152
153void
154BaseTags::cleanupRefs()
155{
156    forEachBlk([this](CacheBlk &blk) { cleanupRefsVisitor(blk); });
157}
158
159void
160BaseTags::computeStatsVisitor(CacheBlk &blk)
161{
162    if (blk.isValid()) {
163        assert(blk.task_id < ContextSwitchTaskId::NumTaskId);
164        occupanciesTaskId[blk.task_id]++;
165        assert(blk.tickInserted <= curTick());
166        Tick age = curTick() - blk.tickInserted;
167
168        int age_index;
169        if (age / SimClock::Int::us < 10) { // <10us
170            age_index = 0;
171        } else if (age / SimClock::Int::us < 100) { // <100us
172            age_index = 1;
173        } else if (age / SimClock::Int::ms < 1) { // <1ms
174            age_index = 2;
175        } else if (age / SimClock::Int::ms < 10) { // <10ms
176            age_index = 3;
177        } else
178            age_index = 4; // >10ms
179
180        ageTaskId[blk.task_id][age_index]++;
181    }
182}
183
184void
185BaseTags::computeStats()
186{
187    for (unsigned i = 0; i < ContextSwitchTaskId::NumTaskId; ++i) {
188        occupanciesTaskId[i] = 0;
189        for (unsigned j = 0; j < 5; ++j) {
190            ageTaskId[i][j] = 0;
191        }
192    }
193
194    forEachBlk([this](CacheBlk &blk) { computeStatsVisitor(blk); });
195}
196
197std::string
198BaseTags::print()
199{
200    std::string str;
201
202    auto print_blk = [&str](CacheBlk &blk) {
203        if (blk.isValid())
204            str += csprintf("\tBlock: %s\n", blk.print());
205    };
206    forEachBlk(print_blk);
207
208    if (str.empty())
209        str = "no valid tags\n";
210
211    return str;
212}
213
214void
215BaseTags::regStats()
216{
217    ClockedObject::regStats();
218
219    using namespace Stats;
220
221    tagsInUse
222        .name(name() + ".tagsinuse")
223        .desc("Cycle average of tags in use")
224        ;
225
226    totalRefs
227        .name(name() + ".total_refs")
228        .desc("Total number of references to valid blocks.")
229        ;
230
231    sampledRefs
232        .name(name() + ".sampled_refs")
233        .desc("Sample count of references to valid blocks.")
234        ;
235
236    avgRefs
237        .name(name() + ".avg_refs")
238        .desc("Average number of references to valid blocks.")
239        ;
240
241    avgRefs = totalRefs/sampledRefs;
242
243    warmupCycle
244        .name(name() + ".warmup_cycle")
245        .desc("Cycle when the warmup percentage was hit.")
246        ;
247
248    occupancies
249        .init(cache->system->maxMasters())
250        .name(name() + ".occ_blocks")
251        .desc("Average occupied blocks per requestor")
252        .flags(nozero | nonan)
253        ;
254    for (int i = 0; i < cache->system->maxMasters(); i++) {
255        occupancies.subname(i, cache->system->getMasterName(i));
256    }
257
258    avgOccs
259        .name(name() + ".occ_percent")
260        .desc("Average percentage of cache occupancy")
261        .flags(nozero | total)
262        ;
263    for (int i = 0; i < cache->system->maxMasters(); i++) {
264        avgOccs.subname(i, cache->system->getMasterName(i));
265    }
266
267    avgOccs = occupancies / Stats::constant(numBlocks);
268
269    occupanciesTaskId
270        .init(ContextSwitchTaskId::NumTaskId)
271        .name(name() + ".occ_task_id_blocks")
272        .desc("Occupied blocks per task id")
273        .flags(nozero | nonan)
274        ;
275
276    ageTaskId
277        .init(ContextSwitchTaskId::NumTaskId, 5)
278        .name(name() + ".age_task_id_blocks")
279        .desc("Occupied blocks per task id")
280        .flags(nozero | nonan)
281        ;
282
283    percentOccsTaskId
284        .name(name() + ".occ_task_id_percent")
285        .desc("Percentage of cache occupancy per task id")
286        .flags(nozero)
287        ;
288
289    percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
290
291    tagAccesses
292        .name(name() + ".tag_accesses")
293        .desc("Number of tag accesses")
294        ;
295
296    dataAccesses
297        .name(name() + ".data_accesses")
298        .desc("Number of data accesses")
299        ;
300
301    registerDumpCallback(new BaseTagsDumpCallback(this));
302    registerExitCallback(new BaseTagsCallback(this));
303}
304