Searched refs:int_slave (Results 1 - 12 of 12) sorted by relevance

/gem5/src/arch/x86/
H A DX86LocalApic.py53 int_slave = SlavePort("Port for receiving interrupt messages") variable in class:X86LocalApic
/gem5/configs/learning_gem5/part1/
H A Dsimple.py79 system.cpu.interrupts[0].int_slave = system.membus.master
H A Dtwo_level.py131 system.cpu.interrupts[0].int_slave = system.membus.master
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py78 system.cpu.interrupts[0].int_slave = system.membus.master
H A Dsimple_memobj.py76 system.cpu.interrupts[0].int_slave = system.membus.master
/gem5/tests/configs/
H A Dpc-simple-timing-ruby.py90 cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
/gem5/tests/gem5/cpu_tests/
H A Drun.py156 system.cpu.interrupts[0].int_slave = system.membus.master
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py116 cpu.interrupts[0].int_slave = self.sequencers[i].master
H A Druby_caches_MI_example.py114 cpu.interrupts[0].int_slave = self.sequencers[i].master
/gem5/configs/example/
H A Dse.py269 system.cpu[i].interrupts[0].int_slave = ruby_port.master
H A Dapu_se.py466 system.cpu[i].interrupts[0].int_slave = system.piobus.master
508 system.cpu[cp_idx].interrupts[0].int_slave = system.piobus.master
H A Dfs.py181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master

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