/gem5/src/base/ |
H A D | condcodes.hh | 43 findCarry(int width, uint64_t dest, uint64_t src1, uint64_t src2) { argument 45 return ((~(dest >> shift) & 1) + 55 findOverflow(int width, uint64_t dest, uint64_t src1, uint64_t src2) { argument 57 return ((src1 ^ ~src2) & (src1 ^ dest)) & (1ULL << shift); 65 findParity(int width, uint64_t dest) { argument 66 dest &= mask(width); 67 dest ^= (dest >> 32); 68 dest ^= (dest >> 1 81 findNegative(int width, uint64_t dest) argument 90 findZero(int width, uint64_t dest) argument [all...] |
/gem5/src/arch/sparc/ |
H A D | utility.cc | 68 copyMiscRegs(ThreadContext *src, ThreadContext *dest) argument 76 dest->setMiscRegNoEffect(MISCREG_TL, i); 78 dest->setMiscRegNoEffect(MISCREG_TT, 80 dest->setMiscRegNoEffect(MISCREG_TPC, 82 dest->setMiscRegNoEffect(MISCREG_TNPC, 84 dest->setMiscRegNoEffect(MISCREG_TSTATE, 89 dest->setMiscRegNoEffect(MISCREG_TL, tl); 94 // dest->setMiscRegNoEffect(MISCREG_Y, 96 // dest->setMiscRegNoEffect(MISCREG_CCR, 98 dest 204 copyRegs(ThreadContext *src, ThreadContext *dest) argument [all...] |
/gem5/tests/test-progs/asmtest/src/riscv/env/v/ |
H A D | string.c | 5 void* memcpy(void* dest, const void* src, size_t len) argument 7 if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { 9 uintptr_t *d = dest; 10 while (d < (uintptr_t*)(dest + len)) 14 char *d = dest; 15 while (d < (char*)(dest + len)) 18 return dest; 21 void* memset(void* dest, int byte, size_t len) argument 23 if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { 29 uintptr_t *d = dest; 87 strcpy(char* dest, const char* src) argument [all...] |
/gem5/src/arch/power/ |
H A D | utility.cc | 42 copyRegs(ThreadContext *src, ThreadContext *dest) argument 46 dest->setIntReg(i, src->readIntReg(i)); 50 dest->setFloatReg(i, src->readFloatReg(i)); 56 copyMiscRegs(src, dest); 59 dest->pcState(src->pcState());
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H A D | utility.hh | 66 copyRegs(ThreadContext *src, ThreadContext *dest); 69 copyMiscRegs(ThreadContext *src, ThreadContext *dest) argument
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/gem5/src/arch/alpha/ |
H A D | utility.cc | 65 copyRegs(ThreadContext *src, ThreadContext *dest) argument 69 dest->setIntReg(i, src->readIntReg(i)); 73 dest->setFloatReg(i, src->readFloatReg(i)); 79 copyMiscRegs(src, dest); 82 dest->pcState(src->pcState()); 86 copyMiscRegs(ThreadContext *src, ThreadContext *dest) argument 88 dest->setMiscRegNoEffect(MISCREG_FPCR, 90 dest->setMiscRegNoEffect(MISCREG_UNIQ, 92 dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, 94 dest [all...] |
/gem5/src/arch/arm/insts/ |
H A D | sve.hh | 60 IntRegIndex dest; member in class:ArmISA::SveIndexIIOp 68 dest(_dest), imm1(_imm1), imm2(_imm2) 75 IntRegIndex dest; member in class:ArmISA::SveIndexIROp 83 dest(_dest), imm1(_imm1), op2(_op2) 90 IntRegIndex dest; member in class:ArmISA::SveIndexRIOp 98 dest(_dest), op1(_op1), imm2(_imm2) 105 IntRegIndex dest; member in class:ArmISA::SveIndexRROp 113 dest(_dest), op1(_op1), op2(_op2) 121 IntRegIndex dest; member in class:ArmISA::SvePredCountOp 130 dest(_des 139 IntRegIndex dest; member in class:ArmISA::SvePredCountPredOp 155 IntRegIndex dest, op1, op2; member in class:ArmISA::SveWhileOp 183 IntRegIndex dest, op1, gp; member in class:ArmISA::SveUnaryPredOp 197 IntRegIndex dest, op1; member in class:ArmISA::SveUnaryUnpredOp 211 IntRegIndex dest; member in class:ArmISA::SveUnaryWideImmUnpredOp 227 IntRegIndex dest; member in class:ArmISA::SveUnaryWideImmPredOp 246 IntRegIndex dest, op1; member in class:ArmISA::SveBinImmUnpredConstrOp 262 IntRegIndex dest, gp; member in class:ArmISA::SveBinImmPredOp 277 IntRegIndex dest; member in class:ArmISA::SveBinWideImmUnpredOp 293 IntRegIndex dest, op2, gp; member in class:ArmISA::SveBinDestrPredOp 308 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveBinConstrPredOp 325 IntRegIndex dest, op1, op2; member in class:ArmISA::SveBinUnpredOp 339 IntRegIndex dest, op1, op2; member in class:ArmISA::SveBinIdxUnpredOp 355 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SvePredLogicalOp 371 IntRegIndex dest, op1, op2; member in class:ArmISA::SvePredBinPermOp 386 IntRegIndex dest, gp, op1, op2; member in class:ArmISA::SveCmpOp 401 IntRegIndex dest, gp, op1; member in class:ArmISA::SveCmpImmOp 417 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveTerPredOp 432 IntRegIndex dest, op2; member in class:ArmISA::SveTerImmUnpredOp 448 IntRegIndex dest, op1, gp; member in class:ArmISA::SveReducOp 462 IntRegIndex dest, op1, gp; member in class:ArmISA::SveOrdReducOp 476 IntRegIndex dest; member in class:ArmISA::SvePtrueOp 491 IntRegIndex dest; member in class:ArmISA::SveIntCmpOp 508 IntRegIndex dest; member in class:ArmISA::SveIntCmpImmOp 532 IntRegIndex dest, op1, op2; member in class:ArmISA::SveAdrOp 550 IntRegIndex dest; member in class:ArmISA::SveElemCountOp 570 IntRegIndex dest; member in class:ArmISA::SvePartBrkOp 587 IntRegIndex dest; member in class:ArmISA::SvePartBrkPropOp 604 IntRegIndex dest; member in class:ArmISA::SveSelectOp 627 IntRegIndex dest; member in class:ArmISA::SveUnaryPredPredOp 643 IntRegIndex dest; member in class:ArmISA::SveTblOp 658 IntRegIndex dest; member in class:ArmISA::SveUnpackOp 686 IntRegIndex dest; member in class:ArmISA::SvePredUnaryWImplicitSrcOp 699 IntRegIndex dest; member in class:ArmISA::SvePredUnaryWImplicitSrcPredOp 737 IntRegIndex dest; member in class:ArmISA::SveBinImmUnpredDestrOp 753 IntRegIndex dest, op1; member in class:ArmISA::SveBinImmIdxUnpredOp 769 IntRegIndex dest, op1; member in class:ArmISA::SveUnarySca2VecUnpredOp 785 IntRegIndex dest, op1, op2; member in class:ArmISA::SveDotProdIdxOp 803 IntRegIndex dest, op1, op2; member in class:ArmISA::SveDotProdOp 820 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveComplexOp 837 IntRegIndex dest, op1, op2; member in class:ArmISA::SveComplexIdxOp [all...] |
H A D | neon64_mem.hh | 60 writeVecElem(VReg *dest, XReg src, int index, int eSize) argument 86 dest->lo = (dest->lo & (~maskBits)) | ((src & sMask) << shiftAmt); 88 dest->hi = (dest->hi & (~maskBits)) | ((src & sMask) << shiftAmt);
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H A D | sve_mem.hh | 52 IntRegIndex dest; member in class:ArmISA::SveMemVecFillSpill 65 dest(_dest), base(_base), imm(_imm), 77 IntRegIndex dest; member in class:ArmISA::SveMemPredFillSpill 90 dest(_dest), base(_base), imm(_imm), 102 IntRegIndex dest; member in class:ArmISA::SveContigMemSS 116 dest(_dest), gp(_gp), base(_base), offset(_offset), 128 IntRegIndex dest; member in class:ArmISA::SveContigMemSI 142 dest(_dest), gp(_gp), base(_base), imm(_imm),
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H A D | misc.hh | 48 IntRegIndex dest; member in class:MrsOp 52 PredOp(mnem, _machInst, __opClass), dest(_dest) 104 IntRegIndex dest; member in class:MrrcOp 111 PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest), 124 MiscRegIndex dest; member in class:McrrOp 131 dest(_dest), imm(_imm) 155 IntRegIndex dest; member in class:RegImmOp 160 PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm) 170 IntRegIndex dest; member in class:RegRegOp 175 PredOp(mnem, _machInst, __opClass), dest(_des 185 IntRegIndex dest; member in class:RegImmRegOp 202 IntRegIndex dest; member in class:RegRegRegImmOp 221 IntRegIndex dest; member in class:RegRegRegRegOp 240 IntRegIndex dest; member in class:RegRegRegOp 257 IntRegIndex dest; member in class:RegRegImmOp 275 MiscRegIndex dest; member in class:MiscRegRegImmOp 293 IntRegIndex dest; member in class:RegMiscRegImmOp 311 IntRegIndex dest; member in class:RegImmImmOp 328 IntRegIndex dest; member in class:RegRegImmImmOp 347 IntRegIndex dest; member in class:RegImmRegShiftOp [all...] |
H A D | data64.hh | 51 IntRegIndex dest, op1; member in class:ArmISA::DataXImmOp 57 dest(_dest), op1(_op1), imm(_imm) 67 IntRegIndex dest; member in class:ArmISA::DataXImmOnlyOp 73 dest(_dest), imm(_imm) 83 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXSRegOp 91 dest(_dest), op1(_op1), op2(_op2), 102 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXERegOp 110 dest(_dest), op1(_op1), op2(_op2), 121 IntRegIndex dest, op1; member in class:ArmISA::DataX1RegOp 125 ArmStaticInst(mnem, _machInst, __opClass), dest(_des 135 IntRegIndex dest, op1; member in class:ArmISA::DataX1RegImmOp 151 IntRegIndex dest, op1; member in class:ArmISA::DataX1Reg2ImmOp 168 IntRegIndex dest, op1, op2; member in class:ArmISA::DataX2RegOp 183 IntRegIndex dest, op1, op2; member in class:ArmISA::DataX2RegImmOp 200 IntRegIndex dest, op1, op2, op3; member in class:ArmISA::DataX3RegOp 253 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXCondSelOp [all...] |
H A D | sve.cc | 65 printIntReg(ss, dest); 79 printVecReg(ss, dest, true); 81 printIntReg(ss, dest); 89 printIntReg(ss, dest, opWidth); 98 printVecReg(ss, dest, true); 108 printVecReg(ss, dest, true); 119 printVecReg(ss, dest, true); 131 printVecReg(ss, dest, true); 144 printVecPredReg(ss, dest); 173 printVecReg(ss, dest, tru [all...] |
H A D | vfp.cc | 69 printIntReg(ss, dest); 84 printFloatReg(ss, dest); 95 printFloatReg(ss, dest); 105 printFloatReg(ss, dest); 117 printFloatReg(ss, dest); 132 printFloatReg(ss, dest); 145 printFloatReg(ss, dest); 160 printFloatReg(ss, dest); 912 fpType dest = 0.0; local 922 dest 963 fpType dest = func(op1, op2, op3); local 1041 fpType dest = func(op1, op2); local 1111 fpType dest = func(op1); local 1170 nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2) argument 1182 nextIdxs(IntRegIndex &dest, IntRegIndex &op1) argument 1193 nextIdxs(IntRegIndex &dest) argument [all...] |
H A D | sve_mem.cc | 51 printVecReg(ss, dest, true); 67 printVecPredReg(ss, dest); 84 printVecReg(ss, dest, true); 103 printVecReg(ss, dest, true);
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H A D | misc.cc | 50 printIntReg(ss, dest); 152 printIntReg(ss, dest); 165 printMiscReg(ss, dest); 187 printIntReg(ss, dest); 197 printIntReg(ss, dest); 208 printIntReg(ss, dest); 222 printIntReg(ss, dest); 237 printIntReg(ss, dest); 250 printIntReg(ss, dest); 262 printMiscReg(ss, dest); [all...] |
H A D | data64.cc | 49 printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, 59 printIntReg(ss, dest); 68 printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, 77 printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, 87 printIntReg(ss, dest); 98 printIntReg(ss, dest); 110 printIntReg(ss, dest); 122 printIntReg(ss, dest); 135 printIntReg(ss, dest); 149 printIntReg(ss, dest); [all...] |
H A D | misc64.hh | 63 IntRegIndex dest; member in class:RegRegImmImmOp64 72 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 82 IntRegIndex dest; member in class:RegRegRegImmOp64 91 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 149 MiscRegIndex dest; member in class:MiscRegImmOp64 156 dest(_dest), imm(_imm) 173 MiscRegIndex dest; member in class:MiscRegRegImmOp64 181 dest(_dest), op1(_op1), imm(_imm) 191 IntRegIndex dest; member in class:RegMiscRegImmOp64 199 dest(_des [all...] |
H A D | mem64.cc | 68 printPFflags(os, dest); 70 printIntReg(os, dest); 106 printIntReg(ss, dest); 124 printIntReg(ss, dest); 179 printIntReg(ss, dest); 193 printIntReg(ss, dest);
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/gem5/src/mem/ruby/network/simple/ |
H A D | SimpleNetwork.hh | 62 void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, 64 void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, 66 void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, 77 void addLink(SwitchID src, SwitchID dest, int link_latency); 78 void makeLink(SwitchID src, SwitchID dest,
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H A D | SimpleNetwork.cc | 82 SimpleNetwork::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, argument 85 assert(dest < m_nodes); 91 m_switches[src]->addOutPort(m_fromNetQueues[dest], routing_table_entry, 98 SimpleNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, argument 102 m_switches[dest]->addInPort(m_toNetQueues[src]); 107 SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, argument 126 m_switches[dest]->addInPort(queues);
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/gem5/src/python/m5/ |
H A D | options.py | 44 dest = getattr(parser.values, option.dest) 45 if dest is None: 46 setattr(parser.values, option.dest, values) 48 dest.extend(values) 85 dest = option.dest 86 if dest not in self._allopts: 87 self._allopts[dest] = option 97 dest [all...] |
/gem5/src/arch/x86/insts/ |
H A D | microfpop.hh | 56 const RegIndex dest; member in class:X86ISA::FpOp 69 src1(_src1.index()), src2(_src2.index()), dest(_dest.index()),
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/gem5/src/arch/hsail/insts/ |
H A D | decl.hh | 106 typename DestOperandType::DestOperand dest; member in class:HsailISA::CommonInstBase 113 dest.disassemble()); 132 dest.init(op_offs, obj); 145 return dest.isVectorRegister(); 152 return dest.isCondRegister(); 159 return dest.isScalarRegister(); 179 return dest.opSize(); 189 return dest.regIndex(); 200 int numDstRegOperands() { return dest.isVectorRegister(); } 226 typename DestOperandType::DestOperand dest; member in class:HsailISA::ThreeNonUniformSourceInstBase 407 typename DestOperandType::DestOperand dest; member in class:HsailISA::TwoNonUniformSourceInstBase 811 typename DestOperandType::DestOperand dest; member in class:HsailISA::SpecialInstNoSrcBase 879 typename DestOperandType::DestOperand dest; member in class:HsailISA::SpecialInst1SrcBase 1181 ListOperand dest; member in class:HsailISA::Call [all...] |
/gem5/src/mem/ruby/slicc_interface/ |
H A D | RubySlicc_ComponentMapping.hh | 41 NetDest dest; local 44 dest.add(mach); 46 return dest;
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/gem5/src/mem/ruby/network/ |
H A D | Topology.cc | 162 Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, argument 167 assert(dest <= m_number_of_switches+m_nodes+m_nodes); 173 src_dest_pair.second = dest; 181 Topology::makeLink(Network *net, SwitchID src, SwitchID dest, argument 186 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); 193 src_dest.second = dest; 195 net->makeExtInLink(src, dest - (2 * m_nodes), link_entry.link, 197 } else if (dest < 2*m_nodes) { 198 assert(dest >= m_nodes); 199 NodeID node = dest [all...] |