16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2003-2005 The Regents of The University of Michigan 36691Stjones1@inf.ed.ac.uk * Copyright (c) 2007-2008 The Florida State University 46691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 56691Stjones1@inf.ed.ac.uk * All rights reserved. 66691Stjones1@inf.ed.ac.uk * 76691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 86691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 96691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 106691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 116691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 126691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 136691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 146691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 156691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 166691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 176691Stjones1@inf.ed.ac.uk * 186691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 196691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 206691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 216691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 226691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 236691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 246691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 256691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 266691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 276691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 286691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 296691Stjones1@inf.ed.ac.uk * 306691Stjones1@inf.ed.ac.uk * Authors: Korey Sewell 316691Stjones1@inf.ed.ac.uk * Stephen Hines 326691Stjones1@inf.ed.ac.uk * Timothy M. Jones 336691Stjones1@inf.ed.ac.uk */ 346691Stjones1@inf.ed.ac.uk 356691Stjones1@inf.ed.ac.uk#ifndef __ARCH_POWER_UTILITY_HH__ 366691Stjones1@inf.ed.ac.uk#define __ARCH_POWER_UTILITY_HH__ 376691Stjones1@inf.ed.ac.uk 386691Stjones1@inf.ed.ac.uk#include "base/types.hh" 397720Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 406691Stjones1@inf.ed.ac.uk#include "cpu/thread_context.hh" 416691Stjones1@inf.ed.ac.uk 426691Stjones1@inf.ed.ac.uknamespace PowerISA { 436691Stjones1@inf.ed.ac.uk 447720Sgblack@eecs.umich.eduinline PCState 457720Sgblack@eecs.umich.edubuildRetPC(const PCState &curPC, const PCState &callPC) 467720Sgblack@eecs.umich.edu{ 477720Sgblack@eecs.umich.edu PCState retPC = callPC; 487720Sgblack@eecs.umich.edu retPC.advance(); 497720Sgblack@eecs.umich.edu return retPC; 507720Sgblack@eecs.umich.edu} 517720Sgblack@eecs.umich.edu 526691Stjones1@inf.ed.ac.uk/** 536691Stjones1@inf.ed.ac.uk * Function to ensure ISA semantics about 0 registers. 546691Stjones1@inf.ed.ac.uk * @param tc The thread context. 556691Stjones1@inf.ed.ac.uk */ 566691Stjones1@inf.ed.ac.uktemplate <class TC> 576691Stjones1@inf.ed.ac.ukvoid zeroRegisters(TC *tc); 586691Stjones1@inf.ed.ac.uk 596691Stjones1@inf.ed.ac.ukinline void 606691Stjones1@inf.ed.ac.ukstartupCPU(ThreadContext *tc, int cpuId) 616691Stjones1@inf.ed.ac.uk{ 6210407Smitch.hayenga@arm.com tc->activate(); 636691Stjones1@inf.ed.ac.uk} 646691Stjones1@inf.ed.ac.uk 657506Stjones1@inf.ed.ac.ukvoid 667506Stjones1@inf.ed.ac.ukcopyRegs(ThreadContext *src, ThreadContext *dest); 676691Stjones1@inf.ed.ac.uk 686691Stjones1@inf.ed.ac.ukstatic inline void 696691Stjones1@inf.ed.ac.ukcopyMiscRegs(ThreadContext *src, ThreadContext *dest) 706691Stjones1@inf.ed.ac.uk{ 716691Stjones1@inf.ed.ac.uk} 726691Stjones1@inf.ed.ac.uk 737693SAli.Saidi@ARM.comvoid skipFunction(ThreadContext *tc); 747693SAli.Saidi@ARM.com 757720Sgblack@eecs.umich.eduinline void 7610417Sandreas.hansson@arm.comadvancePC(PCState &pc, const StaticInstPtr &inst) 777720Sgblack@eecs.umich.edu{ 787720Sgblack@eecs.umich.edu pc.advance(); 797720Sgblack@eecs.umich.edu} 807720Sgblack@eecs.umich.edu 818787Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 828787Sgblack@eecs.umich.edu 838300Schander.sudanthi@arm.comstatic inline bool 848300Schander.sudanthi@arm.cominUserMode(ThreadContext *tc) 858300Schander.sudanthi@arm.com{ 868300Schander.sudanthi@arm.com return 0; 878300Schander.sudanthi@arm.com} 888300Schander.sudanthi@arm.com 898300Schander.sudanthi@arm.cominline uint64_t 908300Schander.sudanthi@arm.comgetExecutingAsid(ThreadContext *tc) 918300Schander.sudanthi@arm.com{ 928300Schander.sudanthi@arm.com return 0; 938300Schander.sudanthi@arm.com} 948300Schander.sudanthi@arm.com 958791Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *, int cpuId); 968791Sgblack@eecs.umich.edu 977811Ssteve.reinhardt@amd.com} // namespace PowerISA 986691Stjones1@inf.ed.ac.uk 998300Schander.sudanthi@arm.com 1006691Stjones1@inf.ed.ac.uk#endif // __ARCH_POWER_UTILITY_HH__ 101