113759Sgiacomo.gabrielli@arm.com/* 213759Sgiacomo.gabrielli@arm.com * Copyright (c) 2017-2019 ARM Limited 313759Sgiacomo.gabrielli@arm.com * All rights reserved 413759Sgiacomo.gabrielli@arm.com * 513759Sgiacomo.gabrielli@arm.com * The license below extends only to copyright in the software and shall 613759Sgiacomo.gabrielli@arm.com * not be construed as granting a license to any other intellectual 713759Sgiacomo.gabrielli@arm.com * property including but not limited to intellectual property relating 813759Sgiacomo.gabrielli@arm.com * to a hardware implementation of the functionality of the software 913759Sgiacomo.gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 1013759Sgiacomo.gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 1113759Sgiacomo.gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 1213759Sgiacomo.gabrielli@arm.com * modified or unmodified, in source code or in binary form. 1313759Sgiacomo.gabrielli@arm.com * 1413759Sgiacomo.gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 1513759Sgiacomo.gabrielli@arm.com * modification, are permitted provided that the following conditions are 1613759Sgiacomo.gabrielli@arm.com * met: redistributions of source code must retain the above copyright 1713759Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 1813759Sgiacomo.gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 1913759Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 2013759Sgiacomo.gabrielli@arm.com * documentation and/or other materials provided with the distribution; 2113759Sgiacomo.gabrielli@arm.com * neither the name of the copyright holders nor the names of its 2213759Sgiacomo.gabrielli@arm.com * contributors may be used to endorse or promote products derived from 2313759Sgiacomo.gabrielli@arm.com * this software without specific prior written permission. 2413759Sgiacomo.gabrielli@arm.com * 2513759Sgiacomo.gabrielli@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2613759Sgiacomo.gabrielli@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2713759Sgiacomo.gabrielli@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2813759Sgiacomo.gabrielli@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2913759Sgiacomo.gabrielli@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3013759Sgiacomo.gabrielli@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3113759Sgiacomo.gabrielli@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3213759Sgiacomo.gabrielli@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3313759Sgiacomo.gabrielli@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3413759Sgiacomo.gabrielli@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3513759Sgiacomo.gabrielli@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3613759Sgiacomo.gabrielli@arm.com * 3713759Sgiacomo.gabrielli@arm.com * Authors: Giacomo Gabrielli 3813759Sgiacomo.gabrielli@arm.com */ 3913759Sgiacomo.gabrielli@arm.com 4013759Sgiacomo.gabrielli@arm.com#ifndef __ARCH_ARM_INSTS_SVE_HH__ 4113759Sgiacomo.gabrielli@arm.com#define __ARCH_ARM_INSTS_SVE_HH__ 4213759Sgiacomo.gabrielli@arm.com 4313759Sgiacomo.gabrielli@arm.com#include "arch/arm/insts/static_inst.hh" 4413759Sgiacomo.gabrielli@arm.com 4513759Sgiacomo.gabrielli@arm.comnamespace ArmISA { 4613759Sgiacomo.gabrielli@arm.com 4713759Sgiacomo.gabrielli@arm.comenum class SvePredType { 4813759Sgiacomo.gabrielli@arm.com NONE, 4913759Sgiacomo.gabrielli@arm.com MERGE, 5013759Sgiacomo.gabrielli@arm.com ZERO, 5113759Sgiacomo.gabrielli@arm.com SELECT 5213759Sgiacomo.gabrielli@arm.com}; 5313759Sgiacomo.gabrielli@arm.com 5413759Sgiacomo.gabrielli@arm.com/// Returns the specifier for the predication type `pt` as a string. 5513759Sgiacomo.gabrielli@arm.comconst char* svePredTypeToStr(SvePredType pt); 5613759Sgiacomo.gabrielli@arm.com 5713759Sgiacomo.gabrielli@arm.com/// Index generation instruction, immediate operands 5813759Sgiacomo.gabrielli@arm.comclass SveIndexIIOp : public ArmStaticInst { 5913759Sgiacomo.gabrielli@arm.com protected: 6013759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 6113759Sgiacomo.gabrielli@arm.com int8_t imm1; 6213759Sgiacomo.gabrielli@arm.com int8_t imm2; 6313759Sgiacomo.gabrielli@arm.com 6413759Sgiacomo.gabrielli@arm.com SveIndexIIOp(const char* mnem, ExtMachInst _machInst, 6513759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 6613759Sgiacomo.gabrielli@arm.com int8_t _imm1, int8_t _imm2) : 6713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 6813759Sgiacomo.gabrielli@arm.com dest(_dest), imm1(_imm1), imm2(_imm2) 6913759Sgiacomo.gabrielli@arm.com {} 7013759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 7113759Sgiacomo.gabrielli@arm.com}; 7213759Sgiacomo.gabrielli@arm.com 7313759Sgiacomo.gabrielli@arm.comclass SveIndexIROp : public ArmStaticInst { 7413759Sgiacomo.gabrielli@arm.com protected: 7513759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 7613759Sgiacomo.gabrielli@arm.com int8_t imm1; 7713759Sgiacomo.gabrielli@arm.com IntRegIndex op2; 7813759Sgiacomo.gabrielli@arm.com 7913759Sgiacomo.gabrielli@arm.com SveIndexIROp(const char* mnem, ExtMachInst _machInst, 8013759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 8113759Sgiacomo.gabrielli@arm.com int8_t _imm1, IntRegIndex _op2) : 8213759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 8313759Sgiacomo.gabrielli@arm.com dest(_dest), imm1(_imm1), op2(_op2) 8413759Sgiacomo.gabrielli@arm.com {} 8513759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 8613759Sgiacomo.gabrielli@arm.com}; 8713759Sgiacomo.gabrielli@arm.com 8813759Sgiacomo.gabrielli@arm.comclass SveIndexRIOp : public ArmStaticInst { 8913759Sgiacomo.gabrielli@arm.com protected: 9013759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 9113759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 9213759Sgiacomo.gabrielli@arm.com int8_t imm2; 9313759Sgiacomo.gabrielli@arm.com 9413759Sgiacomo.gabrielli@arm.com SveIndexRIOp(const char* mnem, ExtMachInst _machInst, 9513759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 9613759Sgiacomo.gabrielli@arm.com IntRegIndex _op1, int8_t _imm2) : 9713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 9813759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), imm2(_imm2) 9913759Sgiacomo.gabrielli@arm.com {} 10013759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 10113759Sgiacomo.gabrielli@arm.com}; 10213759Sgiacomo.gabrielli@arm.com 10313759Sgiacomo.gabrielli@arm.comclass SveIndexRROp : public ArmStaticInst { 10413759Sgiacomo.gabrielli@arm.com protected: 10513759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 10613759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 10713759Sgiacomo.gabrielli@arm.com IntRegIndex op2; 10813759Sgiacomo.gabrielli@arm.com 10913759Sgiacomo.gabrielli@arm.com SveIndexRROp(const char* mnem, ExtMachInst _machInst, 11013759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 11113759Sgiacomo.gabrielli@arm.com IntRegIndex _op1, IntRegIndex _op2) : 11213759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 11313759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2) 11413759Sgiacomo.gabrielli@arm.com {} 11513759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 11613759Sgiacomo.gabrielli@arm.com}; 11713759Sgiacomo.gabrielli@arm.com 11813759Sgiacomo.gabrielli@arm.com// Predicate count SVE instruction. 11913759Sgiacomo.gabrielli@arm.comclass SvePredCountOp : public ArmStaticInst { 12013759Sgiacomo.gabrielli@arm.com protected: 12113759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 12213759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 12313759Sgiacomo.gabrielli@arm.com bool srcIs32b; 12413759Sgiacomo.gabrielli@arm.com bool destIsVec; 12513759Sgiacomo.gabrielli@arm.com 12613759Sgiacomo.gabrielli@arm.com SvePredCountOp(const char* mnem, ExtMachInst _machInst, 12713759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, 12813759Sgiacomo.gabrielli@arm.com bool _srcIs32b = false, bool _destIsVec = false) : 12913759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 13013759Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp), 13113759Sgiacomo.gabrielli@arm.com srcIs32b(_srcIs32b), destIsVec(_destIsVec) 13213759Sgiacomo.gabrielli@arm.com {} 13313759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 13413759Sgiacomo.gabrielli@arm.com}; 13513759Sgiacomo.gabrielli@arm.com 13613759Sgiacomo.gabrielli@arm.com// Predicate count SVE instruction (predicated). 13713759Sgiacomo.gabrielli@arm.comclass SvePredCountPredOp : public ArmStaticInst { 13813759Sgiacomo.gabrielli@arm.com protected: 13913759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 14013759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 14113759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 14213759Sgiacomo.gabrielli@arm.com 14313759Sgiacomo.gabrielli@arm.com SvePredCountPredOp(const char* mnem, ExtMachInst _machInst, 14413759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 14513759Sgiacomo.gabrielli@arm.com IntRegIndex _gp) : 14613759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 14713759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), gp(_gp) 14813759Sgiacomo.gabrielli@arm.com {} 14913759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 15013759Sgiacomo.gabrielli@arm.com}; 15113759Sgiacomo.gabrielli@arm.com 15213759Sgiacomo.gabrielli@arm.com/// While predicate generation SVE instruction. 15313759Sgiacomo.gabrielli@arm.comclass SveWhileOp : public ArmStaticInst { 15413759Sgiacomo.gabrielli@arm.com protected: 15513759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 15613759Sgiacomo.gabrielli@arm.com bool srcIs32b; 15713759Sgiacomo.gabrielli@arm.com 15813759Sgiacomo.gabrielli@arm.com SveWhileOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 15913759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 16013759Sgiacomo.gabrielli@arm.com bool _srcIs32b) : 16113759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 16213759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b) 16313759Sgiacomo.gabrielli@arm.com {} 16413759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 16513759Sgiacomo.gabrielli@arm.com}; 16613759Sgiacomo.gabrielli@arm.com 16713759Sgiacomo.gabrielli@arm.com/// Compare and terminate loop SVE instruction. 16813759Sgiacomo.gabrielli@arm.comclass SveCompTermOp : public ArmStaticInst { 16913759Sgiacomo.gabrielli@arm.com protected: 17013759Sgiacomo.gabrielli@arm.com IntRegIndex op1, op2; 17113759Sgiacomo.gabrielli@arm.com 17213759Sgiacomo.gabrielli@arm.com SveCompTermOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 17313759Sgiacomo.gabrielli@arm.com IntRegIndex _op1, IntRegIndex _op2) : 17413759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 17513759Sgiacomo.gabrielli@arm.com op1(_op1), op2(_op2) 17613759Sgiacomo.gabrielli@arm.com {} 17713759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 17813759Sgiacomo.gabrielli@arm.com}; 17913759Sgiacomo.gabrielli@arm.com 18013759Sgiacomo.gabrielli@arm.com/// Unary, constructive, predicated (merging) SVE instruction. 18113759Sgiacomo.gabrielli@arm.comclass SveUnaryPredOp : public ArmStaticInst { 18213759Sgiacomo.gabrielli@arm.com protected: 18313759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, gp; 18413759Sgiacomo.gabrielli@arm.com 18513759Sgiacomo.gabrielli@arm.com SveUnaryPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 18613759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) : 18713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 18813759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), gp(_gp) 18913759Sgiacomo.gabrielli@arm.com {} 19013759Sgiacomo.gabrielli@arm.com 19113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 19213759Sgiacomo.gabrielli@arm.com}; 19313759Sgiacomo.gabrielli@arm.com 19413759Sgiacomo.gabrielli@arm.com/// Unary, constructive, unpredicated SVE instruction. 19513759Sgiacomo.gabrielli@arm.comclass SveUnaryUnpredOp : public ArmStaticInst { 19613759Sgiacomo.gabrielli@arm.com protected: 19713759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1; 19813759Sgiacomo.gabrielli@arm.com 19913759Sgiacomo.gabrielli@arm.com SveUnaryUnpredOp(const char* mnem, ExtMachInst _machInst, 20013759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1) : 20113759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 20213759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1) 20313759Sgiacomo.gabrielli@arm.com {} 20413759Sgiacomo.gabrielli@arm.com 20513759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 20613759Sgiacomo.gabrielli@arm.com}; 20713759Sgiacomo.gabrielli@arm.com 20813759Sgiacomo.gabrielli@arm.com/// Unary with wide immediate, constructive, unpredicated SVE instruction. 20913759Sgiacomo.gabrielli@arm.comclass SveUnaryWideImmUnpredOp : public ArmStaticInst { 21013759Sgiacomo.gabrielli@arm.com protected: 21113759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 21213759Sgiacomo.gabrielli@arm.com uint64_t imm; 21313759Sgiacomo.gabrielli@arm.com 21413759Sgiacomo.gabrielli@arm.com SveUnaryWideImmUnpredOp(const char* mnem, ExtMachInst _machInst, 21513759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 21613759Sgiacomo.gabrielli@arm.com uint64_t _imm) : 21713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 21813759Sgiacomo.gabrielli@arm.com dest(_dest), imm(_imm) 21913759Sgiacomo.gabrielli@arm.com {} 22013759Sgiacomo.gabrielli@arm.com 22113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 22213759Sgiacomo.gabrielli@arm.com}; 22313759Sgiacomo.gabrielli@arm.com 22413759Sgiacomo.gabrielli@arm.com/// Unary with wide immediate, constructive, predicated SVE instruction. 22513759Sgiacomo.gabrielli@arm.comclass SveUnaryWideImmPredOp : public ArmStaticInst { 22613759Sgiacomo.gabrielli@arm.com protected: 22713759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 22813759Sgiacomo.gabrielli@arm.com uint64_t imm; 22913759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 23013759Sgiacomo.gabrielli@arm.com 23113759Sgiacomo.gabrielli@arm.com bool isMerging; 23213759Sgiacomo.gabrielli@arm.com 23313759Sgiacomo.gabrielli@arm.com SveUnaryWideImmPredOp(const char* mnem, ExtMachInst _machInst, 23413759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 23513759Sgiacomo.gabrielli@arm.com uint64_t _imm, IntRegIndex _gp, bool _isMerging) : 23613759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 23713759Sgiacomo.gabrielli@arm.com dest(_dest), imm(_imm), gp(_gp), isMerging(_isMerging) 23813759Sgiacomo.gabrielli@arm.com {} 23913759Sgiacomo.gabrielli@arm.com 24013759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 24113759Sgiacomo.gabrielli@arm.com}; 24213759Sgiacomo.gabrielli@arm.com 24313759Sgiacomo.gabrielli@arm.com/// Binary with immediate, destructive, unpredicated SVE instruction. 24413759Sgiacomo.gabrielli@arm.comclass SveBinImmUnpredConstrOp : public ArmStaticInst { 24513759Sgiacomo.gabrielli@arm.com protected: 24613759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1; 24713759Sgiacomo.gabrielli@arm.com uint64_t imm; 24813759Sgiacomo.gabrielli@arm.com 24913759Sgiacomo.gabrielli@arm.com SveBinImmUnpredConstrOp(const char* mnem, ExtMachInst _machInst, 25013759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 25113759Sgiacomo.gabrielli@arm.com uint64_t _imm) : 25213759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 25313759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), imm(_imm) 25413759Sgiacomo.gabrielli@arm.com {} 25513759Sgiacomo.gabrielli@arm.com 25613759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 25713759Sgiacomo.gabrielli@arm.com}; 25813759Sgiacomo.gabrielli@arm.com 25913759Sgiacomo.gabrielli@arm.com/// Binary with immediate, destructive, predicated (merging) SVE instruction. 26013759Sgiacomo.gabrielli@arm.comclass SveBinImmPredOp : public ArmStaticInst { 26113759Sgiacomo.gabrielli@arm.com protected: 26213759Sgiacomo.gabrielli@arm.com IntRegIndex dest, gp; 26313759Sgiacomo.gabrielli@arm.com uint64_t imm; 26413759Sgiacomo.gabrielli@arm.com 26513759Sgiacomo.gabrielli@arm.com SveBinImmPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 26613759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp) : 26713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 26813759Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp), imm(_imm) 26913759Sgiacomo.gabrielli@arm.com {} 27013759Sgiacomo.gabrielli@arm.com 27113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 27213759Sgiacomo.gabrielli@arm.com}; 27313759Sgiacomo.gabrielli@arm.com 27413759Sgiacomo.gabrielli@arm.com/// Binary with wide immediate, destructive, unpredicated SVE instruction. 27513759Sgiacomo.gabrielli@arm.comclass SveBinWideImmUnpredOp : public ArmStaticInst { 27613759Sgiacomo.gabrielli@arm.com protected: 27713759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 27813759Sgiacomo.gabrielli@arm.com uint64_t imm; 27913759Sgiacomo.gabrielli@arm.com 28013759Sgiacomo.gabrielli@arm.com SveBinWideImmUnpredOp(const char* mnem, ExtMachInst _machInst, 28113759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 28213759Sgiacomo.gabrielli@arm.com uint64_t _imm) : 28313759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 28413759Sgiacomo.gabrielli@arm.com dest(_dest), imm(_imm) 28513759Sgiacomo.gabrielli@arm.com {} 28613759Sgiacomo.gabrielli@arm.com 28713759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 28813759Sgiacomo.gabrielli@arm.com}; 28913759Sgiacomo.gabrielli@arm.com 29013759Sgiacomo.gabrielli@arm.com/// Binary, destructive, predicated (merging) SVE instruction. 29113759Sgiacomo.gabrielli@arm.comclass SveBinDestrPredOp : public ArmStaticInst { 29213759Sgiacomo.gabrielli@arm.com protected: 29313759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op2, gp; 29413759Sgiacomo.gabrielli@arm.com 29513759Sgiacomo.gabrielli@arm.com SveBinDestrPredOp(const char* mnem, ExtMachInst _machInst, 29613759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2, 29713759Sgiacomo.gabrielli@arm.com IntRegIndex _gp) : 29813759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 29913759Sgiacomo.gabrielli@arm.com dest(_dest), op2(_op2), gp(_gp) 30013759Sgiacomo.gabrielli@arm.com {} 30113759Sgiacomo.gabrielli@arm.com 30213759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 30313759Sgiacomo.gabrielli@arm.com}; 30413759Sgiacomo.gabrielli@arm.com 30513759Sgiacomo.gabrielli@arm.com/// Binary, constructive, predicated SVE instruction. 30613759Sgiacomo.gabrielli@arm.comclass SveBinConstrPredOp : public ArmStaticInst { 30713759Sgiacomo.gabrielli@arm.com protected: 30813759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2, gp; 30913759Sgiacomo.gabrielli@arm.com SvePredType predType; 31013759Sgiacomo.gabrielli@arm.com 31113759Sgiacomo.gabrielli@arm.com SveBinConstrPredOp(const char* mnem, ExtMachInst _machInst, 31213759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 31313759Sgiacomo.gabrielli@arm.com IntRegIndex _op2, IntRegIndex _gp, 31413759Sgiacomo.gabrielli@arm.com SvePredType _predType) : 31513759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 31613759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), gp(_gp), predType(_predType) 31713759Sgiacomo.gabrielli@arm.com {} 31813759Sgiacomo.gabrielli@arm.com 31913759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 32013759Sgiacomo.gabrielli@arm.com}; 32113759Sgiacomo.gabrielli@arm.com 32213759Sgiacomo.gabrielli@arm.com/// Binary, unpredicated SVE instruction with indexed operand 32313759Sgiacomo.gabrielli@arm.comclass SveBinUnpredOp : public ArmStaticInst { 32413759Sgiacomo.gabrielli@arm.com protected: 32513759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 32613759Sgiacomo.gabrielli@arm.com 32713759Sgiacomo.gabrielli@arm.com SveBinUnpredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 32813759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 32913759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 33013759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2) 33113759Sgiacomo.gabrielli@arm.com {} 33213759Sgiacomo.gabrielli@arm.com 33313759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 33413759Sgiacomo.gabrielli@arm.com}; 33513759Sgiacomo.gabrielli@arm.com 33613759Sgiacomo.gabrielli@arm.com/// Binary, unpredicated SVE instruction 33713759Sgiacomo.gabrielli@arm.comclass SveBinIdxUnpredOp : public ArmStaticInst { 33813759Sgiacomo.gabrielli@arm.com protected: 33913759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 34013759Sgiacomo.gabrielli@arm.com uint8_t index; 34113759Sgiacomo.gabrielli@arm.com 34213759Sgiacomo.gabrielli@arm.com SveBinIdxUnpredOp(const char* mnem, ExtMachInst _machInst, 34313759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 34413759Sgiacomo.gabrielli@arm.com IntRegIndex _op2, uint8_t _index) : 34513759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 34613759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), index(_index) 34713759Sgiacomo.gabrielli@arm.com {} 34813759Sgiacomo.gabrielli@arm.com 34913759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 35013759Sgiacomo.gabrielli@arm.com}; 35113759Sgiacomo.gabrielli@arm.com 35213759Sgiacomo.gabrielli@arm.com/// Predicate logical instruction. 35313759Sgiacomo.gabrielli@arm.comclass SvePredLogicalOp : public ArmStaticInst { 35413759Sgiacomo.gabrielli@arm.com protected: 35513759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2, gp; 35613759Sgiacomo.gabrielli@arm.com bool isSel; 35713759Sgiacomo.gabrielli@arm.com 35813759Sgiacomo.gabrielli@arm.com SvePredLogicalOp(const char* mnem, ExtMachInst _machInst, 35913759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 36013759Sgiacomo.gabrielli@arm.com IntRegIndex _op2, IntRegIndex _gp, bool _isSel = false) : 36113759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 36213759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), gp(_gp), isSel(_isSel) 36313759Sgiacomo.gabrielli@arm.com {} 36413759Sgiacomo.gabrielli@arm.com 36513759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 36613759Sgiacomo.gabrielli@arm.com}; 36713759Sgiacomo.gabrielli@arm.com 36813759Sgiacomo.gabrielli@arm.com/// Predicate binary permute instruction. 36913759Sgiacomo.gabrielli@arm.comclass SvePredBinPermOp : public ArmStaticInst { 37013759Sgiacomo.gabrielli@arm.com protected: 37113759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 37213759Sgiacomo.gabrielli@arm.com 37313759Sgiacomo.gabrielli@arm.com SvePredBinPermOp(const char* mnem, ExtMachInst _machInst, 37413759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 37513759Sgiacomo.gabrielli@arm.com IntRegIndex _op2) : 37613759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 37713759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2) 37813759Sgiacomo.gabrielli@arm.com {} 37913759Sgiacomo.gabrielli@arm.com 38013759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 38113759Sgiacomo.gabrielli@arm.com}; 38213759Sgiacomo.gabrielli@arm.com 38313759Sgiacomo.gabrielli@arm.com/// SVE compare instructions, predicated (zeroing). 38413759Sgiacomo.gabrielli@arm.comclass SveCmpOp : public ArmStaticInst { 38513759Sgiacomo.gabrielli@arm.com protected: 38613759Sgiacomo.gabrielli@arm.com IntRegIndex dest, gp, op1, op2; 38713759Sgiacomo.gabrielli@arm.com 38813759Sgiacomo.gabrielli@arm.com SveCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 38913759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 39013759Sgiacomo.gabrielli@arm.com IntRegIndex _gp) : 39113759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 39213759Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp), op1(_op1), op2(_op2) 39313759Sgiacomo.gabrielli@arm.com {} 39413759Sgiacomo.gabrielli@arm.com 39513759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 39613759Sgiacomo.gabrielli@arm.com}; 39713759Sgiacomo.gabrielli@arm.com 39813759Sgiacomo.gabrielli@arm.com/// SVE compare-with-immediate instructions, predicated (zeroing). 39913759Sgiacomo.gabrielli@arm.comclass SveCmpImmOp : public ArmStaticInst { 40013759Sgiacomo.gabrielli@arm.com protected: 40113759Sgiacomo.gabrielli@arm.com IntRegIndex dest, gp, op1; 40213759Sgiacomo.gabrielli@arm.com uint64_t imm; 40313759Sgiacomo.gabrielli@arm.com 40413759Sgiacomo.gabrielli@arm.com SveCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 40513759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, 40613759Sgiacomo.gabrielli@arm.com IntRegIndex _gp) : 40713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 40813759Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp), op1(_op1), imm(_imm) 40913759Sgiacomo.gabrielli@arm.com {} 41013759Sgiacomo.gabrielli@arm.com 41113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 41213759Sgiacomo.gabrielli@arm.com}; 41313759Sgiacomo.gabrielli@arm.com 41413759Sgiacomo.gabrielli@arm.com/// Ternary, destructive, predicated (merging) SVE instruction. 41513759Sgiacomo.gabrielli@arm.comclass SveTerPredOp : public ArmStaticInst { 41613759Sgiacomo.gabrielli@arm.com protected: 41713759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2, gp; 41813759Sgiacomo.gabrielli@arm.com 41913759Sgiacomo.gabrielli@arm.com SveTerPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 42013759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 42113759Sgiacomo.gabrielli@arm.com IntRegIndex _gp) : 42213759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 42313759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), gp(_gp) 42413759Sgiacomo.gabrielli@arm.com {} 42513759Sgiacomo.gabrielli@arm.com 42613759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 42713759Sgiacomo.gabrielli@arm.com}; 42813759Sgiacomo.gabrielli@arm.com 42913759Sgiacomo.gabrielli@arm.com/// Ternary with immediate, destructive, unpredicated SVE instruction. 43013759Sgiacomo.gabrielli@arm.comclass SveTerImmUnpredOp : public ArmStaticInst { 43113759Sgiacomo.gabrielli@arm.com protected: 43213759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op2; 43313759Sgiacomo.gabrielli@arm.com uint64_t imm; 43413759Sgiacomo.gabrielli@arm.com 43513759Sgiacomo.gabrielli@arm.com SveTerImmUnpredOp(const char* mnem, ExtMachInst _machInst, 43613759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2, 43713759Sgiacomo.gabrielli@arm.com uint64_t _imm) : 43813759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 43913759Sgiacomo.gabrielli@arm.com dest(_dest), op2(_op2), imm(_imm) 44013759Sgiacomo.gabrielli@arm.com {} 44113759Sgiacomo.gabrielli@arm.com 44213759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 44313759Sgiacomo.gabrielli@arm.com}; 44413759Sgiacomo.gabrielli@arm.com 44513759Sgiacomo.gabrielli@arm.com/// SVE reductions. 44613759Sgiacomo.gabrielli@arm.comclass SveReducOp : public ArmStaticInst { 44713759Sgiacomo.gabrielli@arm.com protected: 44813759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, gp; 44913759Sgiacomo.gabrielli@arm.com 45013759Sgiacomo.gabrielli@arm.com SveReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 45113759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) : 45213759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 45313759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), gp(_gp) 45413759Sgiacomo.gabrielli@arm.com {} 45513759Sgiacomo.gabrielli@arm.com 45613759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 45713759Sgiacomo.gabrielli@arm.com}; 45813759Sgiacomo.gabrielli@arm.com 45913759Sgiacomo.gabrielli@arm.com/// SVE ordered reductions. 46013759Sgiacomo.gabrielli@arm.comclass SveOrdReducOp : public ArmStaticInst { 46113759Sgiacomo.gabrielli@arm.com protected: 46213759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, gp; 46313759Sgiacomo.gabrielli@arm.com 46413759Sgiacomo.gabrielli@arm.com SveOrdReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 46513759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) : 46613759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 46713759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), gp(_gp) 46813759Sgiacomo.gabrielli@arm.com {} 46913759Sgiacomo.gabrielli@arm.com 47013759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 47113759Sgiacomo.gabrielli@arm.com}; 47213759Sgiacomo.gabrielli@arm.com 47313759Sgiacomo.gabrielli@arm.com/// PTRUE, PTRUES. 47413759Sgiacomo.gabrielli@arm.comclass SvePtrueOp : public ArmStaticInst { 47513759Sgiacomo.gabrielli@arm.com protected: 47613759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 47713759Sgiacomo.gabrielli@arm.com uint8_t imm; 47813759Sgiacomo.gabrielli@arm.com 47913759Sgiacomo.gabrielli@arm.com SvePtrueOp(const char* mnem, ExtMachInst _machInst, 48013759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, uint8_t _imm) : 48113759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 48213759Sgiacomo.gabrielli@arm.com dest(_dest), imm(_imm) 48313759Sgiacomo.gabrielli@arm.com {} 48413759Sgiacomo.gabrielli@arm.com 48513759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 48613759Sgiacomo.gabrielli@arm.com}; 48713759Sgiacomo.gabrielli@arm.com 48813759Sgiacomo.gabrielli@arm.com/// Integer compare SVE instruction. 48913759Sgiacomo.gabrielli@arm.comclass SveIntCmpOp : public ArmStaticInst { 49013759Sgiacomo.gabrielli@arm.com protected: 49113759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 49213759Sgiacomo.gabrielli@arm.com IntRegIndex op1, op2; 49313759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 49413759Sgiacomo.gabrielli@arm.com bool op2IsWide; 49513759Sgiacomo.gabrielli@arm.com 49613759Sgiacomo.gabrielli@arm.com SveIntCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 49713759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 49813759Sgiacomo.gabrielli@arm.com IntRegIndex _gp, bool _op2IsWide = false) : 49913759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 50013759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide) 50113759Sgiacomo.gabrielli@arm.com {} 50213759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 50313759Sgiacomo.gabrielli@arm.com}; 50413759Sgiacomo.gabrielli@arm.com 50513759Sgiacomo.gabrielli@arm.com/// Integer compare with immediate SVE instruction. 50613759Sgiacomo.gabrielli@arm.comclass SveIntCmpImmOp : public ArmStaticInst { 50713759Sgiacomo.gabrielli@arm.com protected: 50813759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 50913759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 51013759Sgiacomo.gabrielli@arm.com int64_t imm; 51113759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 51213759Sgiacomo.gabrielli@arm.com 51313759Sgiacomo.gabrielli@arm.com SveIntCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 51413759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, int64_t _imm, 51513759Sgiacomo.gabrielli@arm.com IntRegIndex _gp) : 51613759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 51713759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), imm(_imm), gp(_gp) 51813759Sgiacomo.gabrielli@arm.com {} 51913759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 52013759Sgiacomo.gabrielli@arm.com}; 52113759Sgiacomo.gabrielli@arm.com 52213759Sgiacomo.gabrielli@arm.com/// ADR. 52313759Sgiacomo.gabrielli@arm.comclass SveAdrOp : public ArmStaticInst { 52413759Sgiacomo.gabrielli@arm.com public: 52513759Sgiacomo.gabrielli@arm.com enum SveAdrOffsetFormat { 52613759Sgiacomo.gabrielli@arm.com SveAdrOffsetPacked, 52713759Sgiacomo.gabrielli@arm.com SveAdrOffsetUnpackedSigned, 52813759Sgiacomo.gabrielli@arm.com SveAdrOffsetUnpackedUnsigned 52913759Sgiacomo.gabrielli@arm.com }; 53013759Sgiacomo.gabrielli@arm.com 53113759Sgiacomo.gabrielli@arm.com protected: 53213759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 53313759Sgiacomo.gabrielli@arm.com uint8_t mult; 53413759Sgiacomo.gabrielli@arm.com SveAdrOffsetFormat offsetFormat; 53513759Sgiacomo.gabrielli@arm.com 53613759Sgiacomo.gabrielli@arm.com SveAdrOp(const char* mnem, ExtMachInst _machInst, 53713759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 53813759Sgiacomo.gabrielli@arm.com IntRegIndex _op2, uint8_t _mult, 53913759Sgiacomo.gabrielli@arm.com SveAdrOffsetFormat _offsetFormat) : 54013759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 54113759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), mult(_mult), 54213759Sgiacomo.gabrielli@arm.com offsetFormat(_offsetFormat) 54313759Sgiacomo.gabrielli@arm.com {} 54413759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 54513759Sgiacomo.gabrielli@arm.com}; 54613759Sgiacomo.gabrielli@arm.com 54713759Sgiacomo.gabrielli@arm.com/// Element count SVE instruction. 54813759Sgiacomo.gabrielli@arm.comclass SveElemCountOp : public ArmStaticInst { 54913759Sgiacomo.gabrielli@arm.com protected: 55013759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 55113759Sgiacomo.gabrielli@arm.com uint8_t pattern; 55213759Sgiacomo.gabrielli@arm.com uint8_t imm; 55313759Sgiacomo.gabrielli@arm.com bool dstIsVec; 55413759Sgiacomo.gabrielli@arm.com bool dstIs32b; 55513759Sgiacomo.gabrielli@arm.com uint8_t esize; 55613759Sgiacomo.gabrielli@arm.com 55713759Sgiacomo.gabrielli@arm.com SveElemCountOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 55813759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, uint8_t _pattern, uint8_t _imm, 55913759Sgiacomo.gabrielli@arm.com bool _dstIsVec, bool _dstIs32b) : 56013759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 56113759Sgiacomo.gabrielli@arm.com dest(_dest), pattern(_pattern), imm(_imm), dstIsVec(_dstIsVec), 56213759Sgiacomo.gabrielli@arm.com dstIs32b(_dstIs32b) 56313759Sgiacomo.gabrielli@arm.com {} 56413759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 56513759Sgiacomo.gabrielli@arm.com}; 56613759Sgiacomo.gabrielli@arm.com 56713759Sgiacomo.gabrielli@arm.com/// Partition break SVE instruction. 56813759Sgiacomo.gabrielli@arm.comclass SvePartBrkOp : public ArmStaticInst { 56913759Sgiacomo.gabrielli@arm.com protected: 57013759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 57113759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 57213759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 57313759Sgiacomo.gabrielli@arm.com bool isMerging; 57413759Sgiacomo.gabrielli@arm.com 57513759Sgiacomo.gabrielli@arm.com SvePartBrkOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 57613759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _op1, 57713759Sgiacomo.gabrielli@arm.com bool _isMerging) : 57813759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 57913759Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging) 58013759Sgiacomo.gabrielli@arm.com {} 58113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 58213759Sgiacomo.gabrielli@arm.com}; 58313759Sgiacomo.gabrielli@arm.com 58413759Sgiacomo.gabrielli@arm.com/// Partition break with propagation SVE instruction. 58513759Sgiacomo.gabrielli@arm.comclass SvePartBrkPropOp : public ArmStaticInst { 58613759Sgiacomo.gabrielli@arm.com protected: 58713759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 58813759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 58913759Sgiacomo.gabrielli@arm.com IntRegIndex op2; 59013759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 59113759Sgiacomo.gabrielli@arm.com 59213759Sgiacomo.gabrielli@arm.com SvePartBrkPropOp(const char* mnem, ExtMachInst _machInst, 59313759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 59413759Sgiacomo.gabrielli@arm.com IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) : 59513759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 59613759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), gp(_gp) 59713759Sgiacomo.gabrielli@arm.com {} 59813759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 59913759Sgiacomo.gabrielli@arm.com}; 60013759Sgiacomo.gabrielli@arm.com 60113759Sgiacomo.gabrielli@arm.com/// Scalar element select SVE instruction. 60213759Sgiacomo.gabrielli@arm.comclass SveSelectOp : public ArmStaticInst { 60313759Sgiacomo.gabrielli@arm.com protected: 60413759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 60513759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 60613759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 60713759Sgiacomo.gabrielli@arm.com bool conditional; 60813759Sgiacomo.gabrielli@arm.com bool scalar; 60913759Sgiacomo.gabrielli@arm.com bool simdFp; 61013759Sgiacomo.gabrielli@arm.com size_t scalar_width; 61113759Sgiacomo.gabrielli@arm.com 61213759Sgiacomo.gabrielli@arm.com SveSelectOp(const char* mnem, ExtMachInst _machInst, 61313759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 61413759Sgiacomo.gabrielli@arm.com IntRegIndex _op1, IntRegIndex _gp, 61513759Sgiacomo.gabrielli@arm.com bool _conditional, bool _scalar, 61613759Sgiacomo.gabrielli@arm.com bool _simdFp) : 61713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 61813759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), gp(_gp), conditional(_conditional), 61913759Sgiacomo.gabrielli@arm.com scalar(_scalar), simdFp(_simdFp) 62013759Sgiacomo.gabrielli@arm.com {} 62113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 62213759Sgiacomo.gabrielli@arm.com}; 62313759Sgiacomo.gabrielli@arm.com 62413759Sgiacomo.gabrielli@arm.com/// SVE unary operation on predicate (predicated) 62513759Sgiacomo.gabrielli@arm.comclass SveUnaryPredPredOp : public ArmStaticInst { 62613759Sgiacomo.gabrielli@arm.com protected: 62713759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 62813759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 62913759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 63013759Sgiacomo.gabrielli@arm.com 63113759Sgiacomo.gabrielli@arm.com SveUnaryPredPredOp(const char* mnem, ExtMachInst _machInst, 63213759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 63313759Sgiacomo.gabrielli@arm.com IntRegIndex _op1, IntRegIndex _gp) : 63413759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 63513759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), gp(_gp) 63613759Sgiacomo.gabrielli@arm.com {} 63713759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 63813759Sgiacomo.gabrielli@arm.com}; 63913759Sgiacomo.gabrielli@arm.com 64013759Sgiacomo.gabrielli@arm.com/// SVE table lookup/permute using vector of element indices (TBL) 64113759Sgiacomo.gabrielli@arm.comclass SveTblOp : public ArmStaticInst { 64213759Sgiacomo.gabrielli@arm.com protected: 64313759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 64413759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 64513759Sgiacomo.gabrielli@arm.com IntRegIndex op2; 64613759Sgiacomo.gabrielli@arm.com 64713759Sgiacomo.gabrielli@arm.com SveTblOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 64813759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 64913759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 65013759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2) 65113759Sgiacomo.gabrielli@arm.com {} 65213759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 65313759Sgiacomo.gabrielli@arm.com}; 65413759Sgiacomo.gabrielli@arm.com 65513759Sgiacomo.gabrielli@arm.com/// SVE unpack and widen predicate 65613759Sgiacomo.gabrielli@arm.comclass SveUnpackOp : public ArmStaticInst { 65713759Sgiacomo.gabrielli@arm.com protected: 65813759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 65913759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 66013759Sgiacomo.gabrielli@arm.com 66113759Sgiacomo.gabrielli@arm.com SveUnpackOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 66213759Sgiacomo.gabrielli@arm.com IntRegIndex _dest, IntRegIndex _op1) : 66313759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 66413759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1) 66513759Sgiacomo.gabrielli@arm.com {} 66613759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 66713759Sgiacomo.gabrielli@arm.com}; 66813759Sgiacomo.gabrielli@arm.com 66913759Sgiacomo.gabrielli@arm.com/// SVE predicate test 67013759Sgiacomo.gabrielli@arm.comclass SvePredTestOp : public ArmStaticInst { 67113759Sgiacomo.gabrielli@arm.com protected: 67213759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 67313759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 67413759Sgiacomo.gabrielli@arm.com 67513759Sgiacomo.gabrielli@arm.com SvePredTestOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass, 67613759Sgiacomo.gabrielli@arm.com IntRegIndex _op1, IntRegIndex _gp) : 67713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 67813759Sgiacomo.gabrielli@arm.com op1(_op1), gp(_gp) 67913759Sgiacomo.gabrielli@arm.com {} 68013759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 68113759Sgiacomo.gabrielli@arm.com}; 68213759Sgiacomo.gabrielli@arm.com 68313759Sgiacomo.gabrielli@arm.com/// SVE unary predicate instructions with implicit source operand 68413759Sgiacomo.gabrielli@arm.comclass SvePredUnaryWImplicitSrcOp : public ArmStaticInst { 68513759Sgiacomo.gabrielli@arm.com protected: 68613759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 68713759Sgiacomo.gabrielli@arm.com 68813759Sgiacomo.gabrielli@arm.com SvePredUnaryWImplicitSrcOp(const char* mnem, ExtMachInst _machInst, 68913759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest) : 69013759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 69113759Sgiacomo.gabrielli@arm.com dest(_dest) 69213759Sgiacomo.gabrielli@arm.com {} 69313759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 69413759Sgiacomo.gabrielli@arm.com}; 69513759Sgiacomo.gabrielli@arm.com 69613759Sgiacomo.gabrielli@arm.com/// SVE unary predicate instructions, predicated, with implicit source operand 69713759Sgiacomo.gabrielli@arm.comclass SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst { 69813759Sgiacomo.gabrielli@arm.com protected: 69913759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 70013759Sgiacomo.gabrielli@arm.com IntRegIndex gp; 70113759Sgiacomo.gabrielli@arm.com 70213759Sgiacomo.gabrielli@arm.com SvePredUnaryWImplicitSrcPredOp(const char* mnem, ExtMachInst _machInst, 70313759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, 70413759Sgiacomo.gabrielli@arm.com IntRegIndex _gp) : 70513759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 70613759Sgiacomo.gabrielli@arm.com dest(_dest), gp(_gp) 70713759Sgiacomo.gabrielli@arm.com {} 70813759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 70913759Sgiacomo.gabrielli@arm.com}; 71013759Sgiacomo.gabrielli@arm.com 71113759Sgiacomo.gabrielli@arm.com/// SVE unary predicate instructions with implicit destination operand 71213759Sgiacomo.gabrielli@arm.comclass SvePredUnaryWImplicitDstOp : public ArmStaticInst { 71313759Sgiacomo.gabrielli@arm.com protected: 71413759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 71513759Sgiacomo.gabrielli@arm.com 71613759Sgiacomo.gabrielli@arm.com SvePredUnaryWImplicitDstOp(const char* mnem, ExtMachInst _machInst, 71713759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _op1) : 71813759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 71913759Sgiacomo.gabrielli@arm.com op1(_op1) 72013759Sgiacomo.gabrielli@arm.com {} 72113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 72213759Sgiacomo.gabrielli@arm.com}; 72313759Sgiacomo.gabrielli@arm.com 72413759Sgiacomo.gabrielli@arm.com/// SVE unary predicate instructions with implicit destination operand 72513759Sgiacomo.gabrielli@arm.comclass SveWImplicitSrcDstOp : public ArmStaticInst { 72613759Sgiacomo.gabrielli@arm.com protected: 72713759Sgiacomo.gabrielli@arm.com SveWImplicitSrcDstOp(const char* mnem, ExtMachInst _machInst, 72813759Sgiacomo.gabrielli@arm.com OpClass __opClass) : 72913759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass) 73013759Sgiacomo.gabrielli@arm.com {} 73113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 73213759Sgiacomo.gabrielli@arm.com}; 73313759Sgiacomo.gabrielli@arm.com 73413759Sgiacomo.gabrielli@arm.com/// SVE vector - immediate binary operation 73513759Sgiacomo.gabrielli@arm.comclass SveBinImmUnpredDestrOp : public ArmStaticInst { 73613759Sgiacomo.gabrielli@arm.com protected: 73713759Sgiacomo.gabrielli@arm.com IntRegIndex dest; 73813759Sgiacomo.gabrielli@arm.com IntRegIndex op1; 73913759Sgiacomo.gabrielli@arm.com uint64_t imm; 74013759Sgiacomo.gabrielli@arm.com 74113759Sgiacomo.gabrielli@arm.com SveBinImmUnpredDestrOp(const char* mnem, ExtMachInst _machInst, 74213759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 74313759Sgiacomo.gabrielli@arm.com uint64_t _imm) : 74413759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 74513759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), imm(_imm) 74613759Sgiacomo.gabrielli@arm.com {} 74713759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 74813759Sgiacomo.gabrielli@arm.com}; 74913759Sgiacomo.gabrielli@arm.com 75013759Sgiacomo.gabrielli@arm.com/// Binary with immediate index, destructive, unpredicated SVE instruction. 75113759Sgiacomo.gabrielli@arm.comclass SveBinImmIdxUnpredOp : public ArmStaticInst { 75213759Sgiacomo.gabrielli@arm.com protected: 75313759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1; 75413759Sgiacomo.gabrielli@arm.com uint64_t imm; 75513759Sgiacomo.gabrielli@arm.com 75613759Sgiacomo.gabrielli@arm.com SveBinImmIdxUnpredOp(const char* mnem, ExtMachInst _machInst, 75713759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 75813759Sgiacomo.gabrielli@arm.com uint64_t _imm) : 75913759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 76013759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), imm(_imm) 76113759Sgiacomo.gabrielli@arm.com {} 76213759Sgiacomo.gabrielli@arm.com 76313759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 76413759Sgiacomo.gabrielli@arm.com}; 76513759Sgiacomo.gabrielli@arm.com 76613759Sgiacomo.gabrielli@arm.com/// Unary unpredicated scalar to vector instruction 76713759Sgiacomo.gabrielli@arm.comclass SveUnarySca2VecUnpredOp : public ArmStaticInst { 76813759Sgiacomo.gabrielli@arm.com protected: 76913759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1; 77013759Sgiacomo.gabrielli@arm.com bool simdFp; 77113759Sgiacomo.gabrielli@arm.com 77213759Sgiacomo.gabrielli@arm.com SveUnarySca2VecUnpredOp(const char* mnem, ExtMachInst _machInst, 77313759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 77413759Sgiacomo.gabrielli@arm.com bool _simdFp) : 77513759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 77613759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), simdFp(_simdFp) 77713759Sgiacomo.gabrielli@arm.com {} 77813759Sgiacomo.gabrielli@arm.com 77913759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 78013759Sgiacomo.gabrielli@arm.com}; 78113759Sgiacomo.gabrielli@arm.com 78213759Sgiacomo.gabrielli@arm.com/// SVE dot product instruction (indexed) 78313759Sgiacomo.gabrielli@arm.comclass SveDotProdIdxOp : public ArmStaticInst { 78413759Sgiacomo.gabrielli@arm.com protected: 78513759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 78613759Sgiacomo.gabrielli@arm.com uint64_t imm; 78713759Sgiacomo.gabrielli@arm.com uint8_t esize; 78813759Sgiacomo.gabrielli@arm.com 78913759Sgiacomo.gabrielli@arm.com public: 79013759Sgiacomo.gabrielli@arm.com SveDotProdIdxOp(const char* mnem, ExtMachInst _machInst, 79113759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 79213759Sgiacomo.gabrielli@arm.com IntRegIndex _op2, uint64_t _imm) : 79313759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 79413759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), imm(_imm) 79513759Sgiacomo.gabrielli@arm.com {} 79613759Sgiacomo.gabrielli@arm.com 79713759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 79813759Sgiacomo.gabrielli@arm.com}; 79913759Sgiacomo.gabrielli@arm.com 80013759Sgiacomo.gabrielli@arm.com/// SVE dot product instruction (vectors) 80113759Sgiacomo.gabrielli@arm.comclass SveDotProdOp : public ArmStaticInst { 80213759Sgiacomo.gabrielli@arm.com protected: 80313759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 80413759Sgiacomo.gabrielli@arm.com uint8_t esize; 80513759Sgiacomo.gabrielli@arm.com 80613759Sgiacomo.gabrielli@arm.com public: 80713759Sgiacomo.gabrielli@arm.com SveDotProdOp(const char* mnem, ExtMachInst _machInst, 80813759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 80913759Sgiacomo.gabrielli@arm.com IntRegIndex _op2) : 81013759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 81113759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2) 81213759Sgiacomo.gabrielli@arm.com {} 81313759Sgiacomo.gabrielli@arm.com 81413759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 81513759Sgiacomo.gabrielli@arm.com}; 81613759Sgiacomo.gabrielli@arm.com 81713759Sgiacomo.gabrielli@arm.com/// SVE Complex Instructions (vectors) 81813759Sgiacomo.gabrielli@arm.comclass SveComplexOp : public ArmStaticInst { 81913759Sgiacomo.gabrielli@arm.com protected: 82013759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2, gp; 82113759Sgiacomo.gabrielli@arm.com uint8_t rot; 82213759Sgiacomo.gabrielli@arm.com 82313759Sgiacomo.gabrielli@arm.com public: 82413759Sgiacomo.gabrielli@arm.com SveComplexOp(const char* mnem, ExtMachInst _machInst, 82513759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 82613759Sgiacomo.gabrielli@arm.com IntRegIndex _op2, IntRegIndex _gp, uint8_t _rot) : 82713759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 82813759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), gp(_gp), rot(_rot) 82913759Sgiacomo.gabrielli@arm.com {} 83013759Sgiacomo.gabrielli@arm.com 83113759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 83213759Sgiacomo.gabrielli@arm.com}; 83313759Sgiacomo.gabrielli@arm.com 83413759Sgiacomo.gabrielli@arm.com/// SVE Complex Instructions (indexed) 83513759Sgiacomo.gabrielli@arm.comclass SveComplexIdxOp : public ArmStaticInst { 83613759Sgiacomo.gabrielli@arm.com protected: 83713759Sgiacomo.gabrielli@arm.com IntRegIndex dest, op1, op2; 83813759Sgiacomo.gabrielli@arm.com uint8_t rot, imm; 83913759Sgiacomo.gabrielli@arm.com 84013759Sgiacomo.gabrielli@arm.com public: 84113759Sgiacomo.gabrielli@arm.com SveComplexIdxOp(const char* mnem, ExtMachInst _machInst, 84213759Sgiacomo.gabrielli@arm.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 84313759Sgiacomo.gabrielli@arm.com IntRegIndex _op2, uint8_t _rot, uint8_t _imm) : 84413759Sgiacomo.gabrielli@arm.com ArmStaticInst(mnem, _machInst, __opClass), 84513759Sgiacomo.gabrielli@arm.com dest(_dest), op1(_op1), op2(_op2), rot(_rot), imm(_imm) 84613759Sgiacomo.gabrielli@arm.com {} 84713759Sgiacomo.gabrielli@arm.com 84813759Sgiacomo.gabrielli@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 84913759Sgiacomo.gabrielli@arm.com}; 85013759Sgiacomo.gabrielli@arm.com 85113759Sgiacomo.gabrielli@arm.com 85213759Sgiacomo.gabrielli@arm.com/// Returns the symbolic name associated with pattern `imm` for PTRUE(S) 85313759Sgiacomo.gabrielli@arm.com/// instructions. 85413759Sgiacomo.gabrielli@arm.comstd::string sveDisasmPredCountImm(uint8_t imm); 85513759Sgiacomo.gabrielli@arm.com 85613759Sgiacomo.gabrielli@arm.com/// Returns the actual number of elements active for PTRUE(S) instructions. 85713759Sgiacomo.gabrielli@arm.com/// @param imm 5-bit immediate encoding the predicate pattern. 85813759Sgiacomo.gabrielli@arm.com/// @param num_elems Current number of elements per vector (depending on 85913759Sgiacomo.gabrielli@arm.com/// current vector length and element size). 86013759Sgiacomo.gabrielli@arm.comunsigned int sveDecodePredCount(uint8_t imm, unsigned int num_elems); 86113759Sgiacomo.gabrielli@arm.com 86213759Sgiacomo.gabrielli@arm.com/// Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR). 86313759Sgiacomo.gabrielli@arm.com/// @param imm 1-bit immediate. 86413759Sgiacomo.gabrielli@arm.com/// @param size Encoding of the vector element size. 86513759Sgiacomo.gabrielli@arm.com/// @return Encoding of the expanded value. 86613759Sgiacomo.gabrielli@arm.comuint64_t sveExpandFpImmAddSub(uint8_t imm, uint8_t size); 86713759Sgiacomo.gabrielli@arm.com 86813759Sgiacomo.gabrielli@arm.com/// Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, 86913759Sgiacomo.gabrielli@arm.com/// FMINNM). 87013759Sgiacomo.gabrielli@arm.com/// @param imm 1-bit immediate. 87113759Sgiacomo.gabrielli@arm.com/// @param size Encoding of the vector element size. 87213759Sgiacomo.gabrielli@arm.com/// @return Encoding of the expanded value. 87313759Sgiacomo.gabrielli@arm.comuint64_t sveExpandFpImmMaxMin(uint8_t imm, uint8_t size); 87413759Sgiacomo.gabrielli@arm.com 87513759Sgiacomo.gabrielli@arm.com/// Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL). 87613759Sgiacomo.gabrielli@arm.com/// @param imm 1-bit immediate. 87713759Sgiacomo.gabrielli@arm.com/// @param size Encoding of the vector element size. 87813759Sgiacomo.gabrielli@arm.com/// @return Encoding of the expanded value. 87913759Sgiacomo.gabrielli@arm.comuint64_t sveExpandFpImmMul(uint8_t imm, uint8_t size); 88013759Sgiacomo.gabrielli@arm.com 88113759Sgiacomo.gabrielli@arm.com} // namespace ArmISA 88213759Sgiacomo.gabrielli@arm.com 88313759Sgiacomo.gabrielli@arm.com#endif // __ARCH_ARM_INSTS_SVE_HH__ 884