Searched refs:banks (Results 1 - 15 of 15) sorted by relevance

/gem5/src/mem/ruby/structures/
H A DBankedArray.cc37 BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, argument
41 this->banks = banks;
45 if (banks != 0) {
46 bankBits = floorLog2(banks);
49 busyBanks.resize(banks);
59 assert(bank < banks);
75 assert(bank < banks);
97 if (banks == 1) {
100 return idx % banks;
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H A DBankedArray.hh44 unsigned int banks; member in class:BankedArray
66 BankedArray(unsigned int banks, Cycles accessLatency,
/gem5/src/gpu-compute/
H A DLdsState.py48 banks = Param.Int(32, 'Number of LDS banks') variable in class:LdsState
H A Dlds_state.cc57 banks(params->banks)
59 fatal_if(params->banks <= 0,
60 "Number of LDS banks should be positive number");
61 fatal_if((params->banks & (params->banks - 1)) != 0,
62 "Number of LDS banks should be a power of 2");
121 // the number of LDS banks being touched by the memory instruction
122 int numBanks = std::min(parent->wfSize(), banks);
123 // if the wavefront size is larger than the number of LDS banks, w
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H A Dlds_state.hh409 return banks;
505 // the number of banks in the LDS underlying data store
506 int banks = 0;
/gem5/util/plot_dram/
H A Ddram_sweep_plot.py54 # different combinations of parallel banks, and stride size, as
84 # Get the burst size, number of banks and the maximum stride from
90 "burst: (\d+), banks: (\d+), max stride: (\d+)", line)
93 banks = int(match.groups(0)[1])
155 # We should have a 2D grid with as many columns as banks
156 if len(zs) != banks:
163 Y = np.arange(1, banks + 1, 1)
166 # the values in the util are banks major, so we see groups for each
/gem5/src/mem/
H A Ddram_ctrl.cc155 fatal("banks per rank (%d) must be equal to or larger than "
156 "banks groups per rank (%d)\n",
159 // must have same number of banks in each bank group
162 "per rank (%d) for equal banks per bank group\n",
333 // over the banks
355 // over the banks
408 size, ranks[rank]->banks[bank], *ranks[rank]);
887 // bank is amongst first available banks
995 if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) {
999 rank_ref.banks[
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H A Ddram_ctrl.hh202 * PWR_IDLE : The idle state in which all banks are closed
218 * PWR_ACT : Activate state in which one or more banks are open
251 * Next state dependent on whether banks are open
254 * REF_PRE : Close (precharge) all open banks
274 * Rank class includes a vector of banks. Refresh and Power state
425 * banks are added out of order. Will only pass commands up to
432 * term are made from several banks.
434 std::vector<Bank> banks; member in class:DRAMCtrl::Rank
437 * To track number of banks which are currently active for
474 * Check if the current rank has all banks close
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/gem5/configs/dram/
H A Dsweep.py54 # controller configuration, by varying the number of banks accessed,
79 DRAM_ROTATE: Traffic rotating across banks and ranks")
141 # get the number of banks
202 print("DRAM sweep with burst: %d, banks: %d, max stride: %d" %
/gem5/ext/mcpat/cacti/
H A Dcacti_interface.h357 int banks,
411 int banks,
H A Dio.cc505 cout << "Cache banks (UCA) : " << nbanks << endl;
679 int banks,
744 g_ip->nbanks = banks;
870 int banks,
934 g_ip->nbanks = banks;
1096 // // If multiple banks and multiple ports are specified, then if number of ports is less than or equal to
1097 // // the number of banks, we assume that the multiple ports are implemented via the multiple banks.
1294 file << "Number of banks, ";
1476 cout << " Number of banks
671 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int banks, double tech_node, int page_sz, int burst_length, int pre_width, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int is_nuca, int core_count, int cache_level, int nuca_bank_count, int nuca_obj_func_delay, int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, int nuca_obj_func_area, int nuca_obj_func_cycle_time, int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, int nuca_dev_func_leakage_power, int nuca_dev_func_area, int nuca_dev_func_cycle_time, int REPEATERS_IN_HTREE_SEGMENTS_in, int p_input) argument
861 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int search_ports, int banks, double tech_node, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_cycle_time, int obj_func_area, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, int PAGE_SIZE_BITS_in, int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, int wiretype, int force_config, int ndwl, int ndbl, int nspd, int ndcm, int ndsam1, int ndsam2, int ecc) argument
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/gem5/tests/configs/
H A Dgpu-ruby.py148 help="number of physical banks per LDS module")
225 LdsState(banks = options.numLdsBanks,
/gem5/ext/mcpat/
H A Dcacheunit.cc71 double banks; local
75 banks = cache_params.nbanks;
96 interface_ip.nbanks = (int)banks;
H A Dcore.cc61 int idx, tag, data, size, line, assoc, banks; local
142 banks = inst_fetch_params.btb_num_banks;
150 interface_ip.nbanks = banks;
/gem5/configs/example/
H A Dapu_se.py150 help="number of physical banks per LDS module")
252 LdsState(banks = options.numLdsBanks,

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