110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu#include <algorithm> 3410152Satgutier@umich.edu#include <cassert> 3510152Satgutier@umich.edu#include <cmath> 3610152Satgutier@umich.edu#include <iostream> 3710234Syasuko.eckert@amd.com#include <sstream> 3810152Satgutier@umich.edu#include <string> 3910152Satgutier@umich.edu 4010152Satgutier@umich.edu#include "basic_circuit.h" 4110234Syasuko.eckert@amd.com#include "basic_components.h" 4210234Syasuko.eckert@amd.com#include "common.h" 4310152Satgutier@umich.edu#include "const.h" 4410152Satgutier@umich.edu#include "core.h" 4510152Satgutier@umich.edu#include "io.h" 4610152Satgutier@umich.edu#include "parameter.h" 4710234Syasuko.eckert@amd.com 4810234Syasuko.eckert@amd.comint RegFU::RFWIN_ACCESS_MULTIPLIER = 16; 4910234Syasuko.eckert@amd.com 5010234Syasuko.eckert@amd.com// The five bits are: busy, Issued, Finished, speculative, valid 5110234Syasuko.eckert@amd.comint SchedulerU::ROB_STATUS_BITS = 5; 5210234Syasuko.eckert@amd.com 5310234Syasuko.eckert@amd.comInstFetchU::InstFetchU(XMLNode* _xml_data, InputParameter* interface_ip_, 5410234Syasuko.eckert@amd.com const CoreParameters & _core_params, 5510234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_) 5610234Syasuko.eckert@amd.com : McPATComponent(_xml_data), icache(NULL), IB(NULL), BTB(NULL), 5710234Syasuko.eckert@amd.com BPT(NULL), ID_inst(NULL), ID_operand(NULL), ID_misc(NULL), 5810234Syasuko.eckert@amd.com interface_ip(*interface_ip_), 5910234Syasuko.eckert@amd.com core_params(_core_params), core_stats(_core_stats), exist(exist_) { 6010234Syasuko.eckert@amd.com if (!exist) return; 6110234Syasuko.eckert@amd.com int idx, tag, data, size, line, assoc, banks; 6210234Syasuko.eckert@amd.com bool is_default = true; 6310234Syasuko.eckert@amd.com 6410234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 6510234Syasuko.eckert@amd.com name = "Instruction Fetch Unit"; 6610234Syasuko.eckert@amd.com // Check if there is an icache child: 6710234Syasuko.eckert@amd.com int i; 6810234Syasuko.eckert@amd.com icache = NULL; 6910234Syasuko.eckert@amd.com for( i = 0; i < xml_data->nChildNode("component"); i++ ) { 7010234Syasuko.eckert@amd.com XMLNode* childXML = xml_data->getChildNodePtr("component", &i); 7110234Syasuko.eckert@amd.com XMLCSTR type = childXML->getAttribute("type"); 7210234Syasuko.eckert@amd.com 7310234Syasuko.eckert@amd.com if (!type) 7410234Syasuko.eckert@amd.com warnMissingComponentType(childXML->getAttribute("id")); 7510234Syasuko.eckert@amd.com 7610234Syasuko.eckert@amd.com STRCMP(type, "CacheUnit") { 7710234Syasuko.eckert@amd.com XMLCSTR name = childXML->getAttribute("name"); 7810234Syasuko.eckert@amd.com if (strcmp(name, "Instruction Cache") == 0 || 7910234Syasuko.eckert@amd.com strcmp(name, "icache") == 0) { 8010234Syasuko.eckert@amd.com icache = new CacheUnit(childXML, &interface_ip); 8110234Syasuko.eckert@amd.com children.push_back(icache); 8210234Syasuko.eckert@amd.com } 8310234Syasuko.eckert@amd.com } 8410234Syasuko.eckert@amd.com } 8510234Syasuko.eckert@amd.com 8610234Syasuko.eckert@amd.com set_params_stats(); 8710234Syasuko.eckert@amd.com 8810234Syasuko.eckert@amd.com //Instruction buffer 8910234Syasuko.eckert@amd.com data = core_params.instruction_length * core_params.peak_issueW; 9010234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 9110234Syasuko.eckert@amd.com size = core_params.num_hthreads * core_params.instruction_buffer_size * 9210234Syasuko.eckert@amd.com line; 9310234Syasuko.eckert@amd.com if (size < MIN_BUFFER_SIZE) { 9410234Syasuko.eckert@amd.com size = MIN_BUFFER_SIZE; 9510234Syasuko.eckert@amd.com } 9610234Syasuko.eckert@amd.com 9710234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 9810234Syasuko.eckert@amd.com interface_ip.line_sz = line; 9910234Syasuko.eckert@amd.com interface_ip.assoc = core_params.instruction_buffer_assoc; 10010234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.instruction_buffer_nbanks; 10110234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 10210234Syasuko.eckert@amd.com interface_ip.specific_tag = core_params.instruction_buffer_tag_width > 0; 10310234Syasuko.eckert@amd.com interface_ip.tag_w = core_params.instruction_buffer_tag_width; 10410234Syasuko.eckert@amd.com interface_ip.access_mode = Normal; 10510234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 10610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 10710234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 10810234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 10910234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 11010234Syasuko.eckert@amd.com core_params.number_instruction_fetch_ports; 11110234Syasuko.eckert@amd.com interface_ip.num_rd_ports = 0; 11210234Syasuko.eckert@amd.com interface_ip.num_wr_ports = 0; 11310234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 11410234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 11510234Syasuko.eckert@amd.com interface_ip.is_cache = false; 11610234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 11710234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 11810234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 11910234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 12010234Syasuko.eckert@amd.com 12110234Syasuko.eckert@amd.com IB = new ArrayST(xml_data, &interface_ip, "Instruction Buffer", 12210234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 12310234Syasuko.eckert@amd.com core_params.core_ty); 12410234Syasuko.eckert@amd.com IB->area.set_area(IB->area.get_area() + IB->local_result.area); 12510234Syasuko.eckert@amd.com area.set_area(area.get_area() + IB->local_result.area); 12610234Syasuko.eckert@amd.com 12710234Syasuko.eckert@amd.com if (core_params.predictionW > 0) { 12810234Syasuko.eckert@amd.com /* 12910234Syasuko.eckert@amd.com * BTB branch target buffer, accessed during IF stage. Virtually indexed and virtually tagged 13010234Syasuko.eckert@amd.com * It is only a cache without all the buffers in the cache controller since it is more like a 13110234Syasuko.eckert@amd.com * look up table than a cache with cache controller. When access miss, no load from other places 13210234Syasuko.eckert@amd.com * such as main memory (not actively fill the misses), it is passively updated under two circumstances: 13310234Syasuko.eckert@amd.com * 1) when BPT@ID stage finds out current is a taken branch while BTB missed 13410234Syasuko.eckert@amd.com * 2) When BPT@ID stage predicts differently than BTB 13510234Syasuko.eckert@amd.com * 3) When ID stage finds out current instruction is not a branch while BTB had a hit.(mark as invalid) 13610234Syasuko.eckert@amd.com * 4) when EXEU find out wrong target has been provided from BTB. 13710234Syasuko.eckert@amd.com * 13810234Syasuko.eckert@amd.com */ 13910234Syasuko.eckert@amd.com size = inst_fetch_params.btb_size; 14010234Syasuko.eckert@amd.com line = inst_fetch_params.btb_block_size; 14110234Syasuko.eckert@amd.com assoc = inst_fetch_params.btb_assoc; 14210234Syasuko.eckert@amd.com banks = inst_fetch_params.btb_num_banks; 14310234Syasuko.eckert@amd.com idx = int(ceil(log2(size / line / assoc))); 14410234Syasuko.eckert@amd.com tag = virtual_address_width + int(ceil(log2(core_params.num_hthreads))) 14510234Syasuko.eckert@amd.com + EXTRA_TAG_BITS; 14610234Syasuko.eckert@amd.com 14710234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 14810234Syasuko.eckert@amd.com interface_ip.line_sz = line; 14910234Syasuko.eckert@amd.com interface_ip.assoc = assoc; 15010234Syasuko.eckert@amd.com interface_ip.nbanks = banks; 15110234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 15210234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 15310234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 15410234Syasuko.eckert@amd.com interface_ip.access_mode = Normal; 15510234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 15610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 15710234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 15810234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 15910234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 1; 16010234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.predictionW; 16110234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.predictionW; 16210234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 16310234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 16410234Syasuko.eckert@amd.com interface_ip.is_cache = true; 16510234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 16610234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 16710234Syasuko.eckert@amd.com interface_ip.throughput = inst_fetch_params.btb_throughput / clockRate; 16810234Syasuko.eckert@amd.com interface_ip.latency = inst_fetch_params.btb_latency / clockRate; 16910234Syasuko.eckert@amd.com 17010234Syasuko.eckert@amd.com BTB = new ArrayST(xml_data, &interface_ip, "Branch Target Buffer", 17110234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 17210234Syasuko.eckert@amd.com core_params.core_ty); 17310234Syasuko.eckert@amd.com area.set_area(area.get_area() + BTB->local_result.area); 17410234Syasuko.eckert@amd.com 17510234Syasuko.eckert@amd.com BPT = new BranchPredictor(xml_data, &interface_ip, 17610234Syasuko.eckert@amd.com core_params, core_stats); 17710234Syasuko.eckert@amd.com area.set_area(area.get_area() + BPT->area.get_area()); 17810234Syasuko.eckert@amd.com } 17910234Syasuko.eckert@amd.com 18010234Syasuko.eckert@amd.com ID_inst = new InstructionDecoder(xml_data, "Instruction Opcode Decoder", 18110234Syasuko.eckert@amd.com is_default, &interface_ip, 18210234Syasuko.eckert@amd.com core_params.opcode_width, 18310234Syasuko.eckert@amd.com core_params.decodeW, 18410234Syasuko.eckert@amd.com core_params.x86, clockRate, 18510234Syasuko.eckert@amd.com Core_device, core_params.core_ty); 18610234Syasuko.eckert@amd.com 18710234Syasuko.eckert@amd.com ID_operand = new InstructionDecoder(xml_data, 18810234Syasuko.eckert@amd.com "Instruction Operand Decoder", 18910234Syasuko.eckert@amd.com is_default, &interface_ip, 19010234Syasuko.eckert@amd.com core_params.arch_ireg_width, 19110234Syasuko.eckert@amd.com core_params.decodeW, 19210234Syasuko.eckert@amd.com core_params.x86, clockRate, 19310234Syasuko.eckert@amd.com Core_device, core_params.core_ty); 19410234Syasuko.eckert@amd.com 19510234Syasuko.eckert@amd.com ID_misc = new InstructionDecoder(xml_data, "Instruction Microcode Decoder", 19610234Syasuko.eckert@amd.com is_default, &interface_ip, 19710234Syasuko.eckert@amd.com core_params.micro_opcode_length, 19810234Syasuko.eckert@amd.com core_params.decodeW, 19910234Syasuko.eckert@amd.com core_params.x86, clockRate, 20010234Syasuko.eckert@amd.com Core_device, core_params.core_ty); 20110234Syasuko.eckert@amd.com area.set_area(area.get_area()+ (ID_inst->area.get_area() 20210234Syasuko.eckert@amd.com + ID_operand->area.get_area() 20310234Syasuko.eckert@amd.com + ID_misc->area.get_area()) 20410234Syasuko.eckert@amd.com * core_params.decodeW); 20510152Satgutier@umich.edu} 20610152Satgutier@umich.edu 20710234Syasuko.eckert@amd.comvoid 20810234Syasuko.eckert@amd.comInstFetchU::set_params_stats() { 20910234Syasuko.eckert@amd.com int num_children = xml_data->nChildNode("component"); 21010234Syasuko.eckert@amd.com int i; 21110234Syasuko.eckert@amd.com memset(&inst_fetch_params,0,sizeof(InstFetchParameters)); 21210234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 21310234Syasuko.eckert@amd.com XMLNode* child = xml_data->getChildNodePtr("component", &i); 21410234Syasuko.eckert@amd.com XMLCSTR type = child->getAttribute("type"); 21510234Syasuko.eckert@amd.com 21610234Syasuko.eckert@amd.com if (!type) 21710234Syasuko.eckert@amd.com warnMissingComponentType(child->getAttribute("id")); 21810234Syasuko.eckert@amd.com 21910234Syasuko.eckert@amd.com STRCMP(type, "BranchTargetBuffer") { 22010234Syasuko.eckert@amd.com int sub_num_children = child->nChildNode("param"); 22110234Syasuko.eckert@amd.com int j; 22210234Syasuko.eckert@amd.com for (j = 0; j < sub_num_children; j++) { 22310234Syasuko.eckert@amd.com XMLNode* paramNode = child->getChildNodePtr("param", &j); 22410234Syasuko.eckert@amd.com XMLCSTR node_name = paramNode->getAttribute("name"); 22510234Syasuko.eckert@amd.com XMLCSTR value = paramNode->getAttribute("value"); 22610234Syasuko.eckert@amd.com 22710234Syasuko.eckert@amd.com if (!node_name) 22810234Syasuko.eckert@amd.com warnMissingParamName(paramNode->getAttribute("id")); 22910234Syasuko.eckert@amd.com 23010234Syasuko.eckert@amd.com ASSIGN_INT_IF("size", inst_fetch_params.btb_size); 23110234Syasuko.eckert@amd.com ASSIGN_INT_IF("block_size", inst_fetch_params.btb_block_size); 23210234Syasuko.eckert@amd.com ASSIGN_INT_IF("assoc", inst_fetch_params.btb_assoc); 23310234Syasuko.eckert@amd.com ASSIGN_INT_IF("num_banks", inst_fetch_params.btb_num_banks); 23410234Syasuko.eckert@amd.com ASSIGN_INT_IF("latency", inst_fetch_params.btb_latency); 23510234Syasuko.eckert@amd.com ASSIGN_INT_IF("throughput", inst_fetch_params.btb_throughput); 23610234Syasuko.eckert@amd.com ASSIGN_INT_IF("rw_ports", inst_fetch_params.btb_rw_ports); 23710234Syasuko.eckert@amd.com 23810234Syasuko.eckert@amd.com else { 23910234Syasuko.eckert@amd.com warnUnrecognizedParam(node_name); 24010234Syasuko.eckert@amd.com } 24110234Syasuko.eckert@amd.com } 24210234Syasuko.eckert@amd.com 24310234Syasuko.eckert@amd.com sub_num_children = child->nChildNode("stat"); 24410234Syasuko.eckert@amd.com for (j = 0; j < sub_num_children; j++) { 24510234Syasuko.eckert@amd.com XMLNode* statNode = child->getChildNodePtr("stat", &j); 24610234Syasuko.eckert@amd.com XMLCSTR node_name = statNode->getAttribute("name"); 24710234Syasuko.eckert@amd.com XMLCSTR value = statNode->getAttribute("value"); 24810234Syasuko.eckert@amd.com 24910234Syasuko.eckert@amd.com if (!node_name) 25010234Syasuko.eckert@amd.com warnMissingStatName(statNode->getAttribute("id")); 25110234Syasuko.eckert@amd.com 25210234Syasuko.eckert@amd.com ASSIGN_FP_IF("read_accesses", 25310234Syasuko.eckert@amd.com inst_fetch_stats.btb_read_accesses); 25410234Syasuko.eckert@amd.com ASSIGN_FP_IF("write_accesses", 25510234Syasuko.eckert@amd.com inst_fetch_stats.btb_write_accesses); 25610234Syasuko.eckert@amd.com else { 25710234Syasuko.eckert@amd.com warnUnrecognizedStat(node_name); 25810234Syasuko.eckert@amd.com } 25910234Syasuko.eckert@amd.com } 26010234Syasuko.eckert@amd.com } 26110234Syasuko.eckert@amd.com } 26210234Syasuko.eckert@amd.com 26310234Syasuko.eckert@amd.com // Parameter sanity check 26410234Syasuko.eckert@amd.com if (inst_fetch_params.btb_size <= 0) { 26510234Syasuko.eckert@amd.com errorNonPositiveParam("size"); 26610234Syasuko.eckert@amd.com } 26710234Syasuko.eckert@amd.com 26810234Syasuko.eckert@amd.com if (inst_fetch_params.btb_block_size <= 0) { 26910234Syasuko.eckert@amd.com errorNonPositiveParam("block_size"); 27010234Syasuko.eckert@amd.com } 27110234Syasuko.eckert@amd.com 27210234Syasuko.eckert@amd.com if (inst_fetch_params.btb_assoc <= 0) { 27310234Syasuko.eckert@amd.com errorNonPositiveParam("assoc"); 27410234Syasuko.eckert@amd.com } 27510234Syasuko.eckert@amd.com 27610234Syasuko.eckert@amd.com if (inst_fetch_params.btb_num_banks <= 0) { 27710234Syasuko.eckert@amd.com errorNonPositiveParam("num_banks"); 27810234Syasuko.eckert@amd.com } 27910234Syasuko.eckert@amd.com} 28010234Syasuko.eckert@amd.com 28110234Syasuko.eckert@amd.comBranchPredictor::BranchPredictor(XMLNode* _xml_data, 28210234Syasuko.eckert@amd.com InputParameter* interface_ip_, 28310234Syasuko.eckert@amd.com const CoreParameters & _core_params, 28410234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, 28510234Syasuko.eckert@amd.com bool exist_) 28610234Syasuko.eckert@amd.com : McPATComponent(_xml_data), globalBPT(NULL), localBPT(NULL), 28710234Syasuko.eckert@amd.com L1_localBPT(NULL), L2_localBPT(NULL), chooser(NULL), RAS(NULL), 28810234Syasuko.eckert@amd.com interface_ip(*interface_ip_), 28910234Syasuko.eckert@amd.com core_params(_core_params), core_stats(_core_stats), exist(exist_) { 29010234Syasuko.eckert@amd.com if (!exist) return; 29110234Syasuko.eckert@amd.com int tag; 29210234Syasuko.eckert@amd.com int data; 29310234Syasuko.eckert@amd.com int size; 29410234Syasuko.eckert@amd.com 29510234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 29610234Syasuko.eckert@amd.com name = "Branch Predictor"; 29710234Syasuko.eckert@amd.com 29810234Syasuko.eckert@amd.com // Common interface parameters for the branch predictor structures 29910234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 30010234Syasuko.eckert@amd.com 30110234Syasuko.eckert@amd.com if (core_params.multithreaded) { 30210234Syasuko.eckert@amd.com tag = int(log2(core_params.num_hthreads) + EXTRA_TAG_BITS); 30310234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 30410234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 30510234Syasuko.eckert@amd.com interface_ip.is_cache = true; 30610234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 30710234Syasuko.eckert@amd.com } else { 30810234Syasuko.eckert@amd.com interface_ip.specific_tag = 0; 30910234Syasuko.eckert@amd.com interface_ip.tag_w = 0; 31010234Syasuko.eckert@amd.com interface_ip.is_cache = false; 31110234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 31210234Syasuko.eckert@amd.com } 31310234Syasuko.eckert@amd.com 31410234Syasuko.eckert@amd.com // Parse params and stats from XML 31510234Syasuko.eckert@amd.com set_params_stats(); 31610234Syasuko.eckert@amd.com 31710234Syasuko.eckert@amd.com // Common interface parameters for the branch predictor structures 31810234Syasuko.eckert@amd.com interface_ip.assoc = branch_pred_params.assoc; 31910234Syasuko.eckert@amd.com interface_ip.nbanks = branch_pred_params.nbanks; 32010234Syasuko.eckert@amd.com 32110234Syasuko.eckert@amd.com //Global predictor 32210234Syasuko.eckert@amd.com data = int(ceil(branch_pred_params.global_predictor_bits / BITS_PER_BYTE)); 32310234Syasuko.eckert@amd.com size = data * branch_pred_params.global_predictor_entries; 32410234Syasuko.eckert@amd.com 32510234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 32610234Syasuko.eckert@amd.com interface_ip.line_sz = data; 32710234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 32810234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 32910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 33010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 33110234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 33210234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 33310234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 33410234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.predictionW; 33510234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.predictionW; 33610234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 33710234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 33810234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 33910234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 34010234Syasuko.eckert@amd.com globalBPT = new ArrayST(xml_data, &interface_ip, "Global Predictor", 34110234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 34210234Syasuko.eckert@amd.com core_params.core_ty); 34310234Syasuko.eckert@amd.com area.set_area(area.get_area() + globalBPT->local_result.area); 34410234Syasuko.eckert@amd.com 34510234Syasuko.eckert@amd.com //Local BPT (Level 1) 34610234Syasuko.eckert@amd.com data = int(ceil(branch_pred_params.local_l1_predictor_size / 34710234Syasuko.eckert@amd.com BITS_PER_BYTE)); 34810234Syasuko.eckert@amd.com size = data * branch_pred_params.local_predictor_entries; 34910234Syasuko.eckert@amd.com 35010234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 35110234Syasuko.eckert@amd.com interface_ip.line_sz = data; 35210234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 35310234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 35410234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 35510234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 35610234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 35710234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 35810234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 35910234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.predictionW; 36010234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.predictionW; 36110234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 36210234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 36310234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 36410234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 36510234Syasuko.eckert@amd.com L1_localBPT = new ArrayST(xml_data, &interface_ip, 36610234Syasuko.eckert@amd.com "Local Predictor, Level 1", 36710234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 36810234Syasuko.eckert@amd.com core_params.core_ty); 36910234Syasuko.eckert@amd.com L1_localBPT->area.set_area(L1_localBPT->area.get_area() + 37010234Syasuko.eckert@amd.com L1_localBPT->local_result.area); 37110234Syasuko.eckert@amd.com area.set_area(area.get_area()+ L1_localBPT->local_result.area); 37210234Syasuko.eckert@amd.com 37310234Syasuko.eckert@amd.com //Local BPT (Level 2) 37410234Syasuko.eckert@amd.com data = int(ceil(branch_pred_params.local_l2_predictor_size / 37510234Syasuko.eckert@amd.com BITS_PER_BYTE)); 37610234Syasuko.eckert@amd.com size = data * branch_pred_params.local_predictor_entries; 37710234Syasuko.eckert@amd.com 37810234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 37910234Syasuko.eckert@amd.com interface_ip.line_sz = data; 38010234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 38110234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 38210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 38310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 38410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 38510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 38610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 38710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.predictionW; 38810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.predictionW; 38910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 39010234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 39110234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 39210234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 39310234Syasuko.eckert@amd.com L2_localBPT = new ArrayST(xml_data, &interface_ip, 39410234Syasuko.eckert@amd.com "Local Predictor, Level 2", 39510234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 39610234Syasuko.eckert@amd.com core_params.core_ty); 39710234Syasuko.eckert@amd.com area.set_area(area.get_area() + L2_localBPT->local_result.area); 39810234Syasuko.eckert@amd.com 39910234Syasuko.eckert@amd.com //Chooser 40010234Syasuko.eckert@amd.com data = int(ceil(branch_pred_params.chooser_predictor_bits / 40110234Syasuko.eckert@amd.com BITS_PER_BYTE)); 40210234Syasuko.eckert@amd.com size = data * branch_pred_params.chooser_predictor_entries; 40310234Syasuko.eckert@amd.com 40410234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 40510234Syasuko.eckert@amd.com interface_ip.line_sz = data; 40610234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 40710234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 40810234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 40910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 41010234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 41110234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 41210234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 41310234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.predictionW; 41410234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.predictionW; 41510234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 41610234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 41710234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 41810234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 41910234Syasuko.eckert@amd.com chooser = new ArrayST(xml_data, &interface_ip, "Predictor Chooser", 42010234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 42110234Syasuko.eckert@amd.com core_params.core_ty); 42210234Syasuko.eckert@amd.com area.set_area(area.get_area() + chooser->local_result.area); 42310234Syasuko.eckert@amd.com 42410234Syasuko.eckert@amd.com //RAS return address stacks are Duplicated for each thread. 42510234Syasuko.eckert@amd.com data = int(ceil(core_params.pc_width / BITS_PER_BYTE)); 42610234Syasuko.eckert@amd.com size = data * core_params.RAS_size; 42710234Syasuko.eckert@amd.com 42810234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 42910234Syasuko.eckert@amd.com interface_ip.line_sz = data; 43010234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 43110234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 43210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 43310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 43410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 43510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 43610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 43710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.predictionW; 43810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.predictionW; 43910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 44010234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 44110234Syasuko.eckert@amd.com interface_ip.is_cache = false; 44210234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 44310234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 44410234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 44510234Syasuko.eckert@amd.com RAS = new ArrayST(xml_data, &interface_ip, "RAS", Core_device, clockRate, 44610234Syasuko.eckert@amd.com core_params.opt_local, core_params.core_ty); 44710234Syasuko.eckert@amd.com RAS->output_data.area *= core_params.num_hthreads; 44810234Syasuko.eckert@amd.com area.set_area(area.get_area() + RAS->local_result.area * 44910234Syasuko.eckert@amd.com core_params.num_hthreads); 45010234Syasuko.eckert@amd.com 45110234Syasuko.eckert@amd.com} 45210234Syasuko.eckert@amd.com 45310234Syasuko.eckert@amd.comvoid 45410234Syasuko.eckert@amd.comBranchPredictor::set_params_stats() { 45510234Syasuko.eckert@amd.com int num_children = xml_data->nChildNode("component"); 45610234Syasuko.eckert@amd.com int i; 45710234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 45810234Syasuko.eckert@amd.com XMLNode* child = xml_data->getChildNodePtr("component", &i); 45910234Syasuko.eckert@amd.com XMLCSTR type = child->getAttribute("type"); 46010234Syasuko.eckert@amd.com 46110234Syasuko.eckert@amd.com if (!type) 46210234Syasuko.eckert@amd.com warnMissingComponentType(child->getAttribute("id")); 46310234Syasuko.eckert@amd.com 46410234Syasuko.eckert@amd.com STRCMP(type, "BranchPredictor") { 46510234Syasuko.eckert@amd.com int sub_num_children = child->nChildNode("param"); 46610234Syasuko.eckert@amd.com int j; 46710234Syasuko.eckert@amd.com for (j = 0; j < sub_num_children; j++) { 46810234Syasuko.eckert@amd.com XMLNode* paramNode = child->getChildNodePtr("param", &j); 46910234Syasuko.eckert@amd.com XMLCSTR node_name = paramNode->getAttribute("name"); 47010234Syasuko.eckert@amd.com XMLCSTR value = paramNode->getAttribute("value"); 47110234Syasuko.eckert@amd.com 47210234Syasuko.eckert@amd.com if (!node_name) 47310234Syasuko.eckert@amd.com warnMissingParamName(paramNode->getAttribute("id")); 47410234Syasuko.eckert@amd.com 47510234Syasuko.eckert@amd.com ASSIGN_INT_IF("assoc", branch_pred_params.assoc); 47610234Syasuko.eckert@amd.com ASSIGN_INT_IF("nbanks", branch_pred_params.nbanks); 47710234Syasuko.eckert@amd.com ASSIGN_INT_IF("local_l1_predictor_size", 47810234Syasuko.eckert@amd.com branch_pred_params.local_l1_predictor_size); 47910234Syasuko.eckert@amd.com ASSIGN_INT_IF("local_l2_predictor_size", 48010234Syasuko.eckert@amd.com branch_pred_params.local_l2_predictor_size); 48110234Syasuko.eckert@amd.com ASSIGN_INT_IF("local_predictor_entries", 48210234Syasuko.eckert@amd.com branch_pred_params.local_predictor_entries); 48310234Syasuko.eckert@amd.com ASSIGN_INT_IF("global_predictor_entries", 48410234Syasuko.eckert@amd.com branch_pred_params.global_predictor_entries); 48510234Syasuko.eckert@amd.com ASSIGN_INT_IF("global_predictor_bits", 48610234Syasuko.eckert@amd.com branch_pred_params.global_predictor_bits); 48710234Syasuko.eckert@amd.com ASSIGN_INT_IF("chooser_predictor_entries", 48810234Syasuko.eckert@amd.com branch_pred_params.chooser_predictor_entries); 48910234Syasuko.eckert@amd.com ASSIGN_INT_IF("chooser_predictor_bits", 49010234Syasuko.eckert@amd.com branch_pred_params.chooser_predictor_bits); 49110234Syasuko.eckert@amd.com 49210234Syasuko.eckert@amd.com else { 49310234Syasuko.eckert@amd.com warnUnrecognizedParam(node_name); 49410234Syasuko.eckert@amd.com } 49510234Syasuko.eckert@amd.com } 49610234Syasuko.eckert@amd.com // The core reads in the number of branches and the number of 49710234Syasuko.eckert@amd.com // function calls and these values are passed through the 49810234Syasuko.eckert@amd.com // core_stats variable, so we don't need to read them in here 49910234Syasuko.eckert@amd.com } 50010234Syasuko.eckert@amd.com } 50110234Syasuko.eckert@amd.com} 50210234Syasuko.eckert@amd.com 50310234Syasuko.eckert@amd.comSchedulerU::SchedulerU(XMLNode* _xml_data, InputParameter* interface_ip_, 50410234Syasuko.eckert@amd.com const CoreParameters & _core_params, 50510234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_) 50610234Syasuko.eckert@amd.com : McPATComponent(_xml_data), int_inst_window(NULL), 50710234Syasuko.eckert@amd.com fp_inst_window(NULL), ROB(NULL), int_instruction_selection(NULL), 50810234Syasuko.eckert@amd.com fp_instruction_selection(NULL), 50910234Syasuko.eckert@amd.com interface_ip(*interface_ip_), 51010234Syasuko.eckert@amd.com core_params(_core_params), core_stats(_core_stats), exist(exist_) { 51110234Syasuko.eckert@amd.com if (!exist) return; 51210234Syasuko.eckert@amd.com int tag; 51310234Syasuko.eckert@amd.com int data; 51410234Syasuko.eckert@amd.com int size; 51510234Syasuko.eckert@amd.com int line; 51610234Syasuko.eckert@amd.com bool is_default = true; 51710234Syasuko.eckert@amd.com string tmp_name; 51810234Syasuko.eckert@amd.com 51910234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 52010234Syasuko.eckert@amd.com name = "Instruction Scheduler"; 52110234Syasuko.eckert@amd.com if ((core_params.core_ty == Inorder && core_params.multithreaded)) { 52210234Syasuko.eckert@amd.com //Instruction issue queue, in-order multi-issue or multithreaded 52310234Syasuko.eckert@amd.com //processor also has this structure. Unified window for Inorder 52410234Syasuko.eckert@amd.com //processors 52510234Syasuko.eckert@amd.com //This tag width is the normal thread state bits based on 52610234Syasuko.eckert@amd.com //Niagara Design 52710234Syasuko.eckert@amd.com tag = int(log2(core_params.num_hthreads) * core_params.perThreadState); 52810234Syasuko.eckert@amd.com data = core_params.instruction_length; 52910234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 53010234Syasuko.eckert@amd.com size = core_params.instruction_window_size * line; 53110234Syasuko.eckert@amd.com if (size < MIN_BUFFER_SIZE) { 53210234Syasuko.eckert@amd.com size = MIN_BUFFER_SIZE; 53310234Syasuko.eckert@amd.com } 53410234Syasuko.eckert@amd.com 53510234Syasuko.eckert@amd.com //NOTE: x86 inst can be very lengthy, up to 15B. 53610234Syasuko.eckert@amd.com //Source: Intel® 64 and IA-32 Architectures 53710234Syasuko.eckert@amd.com //Software Developer’s Manual 53810234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 53910234Syasuko.eckert@amd.com interface_ip.line_sz = line; 54010234Syasuko.eckert@amd.com interface_ip.assoc = core_params.scheduler_assoc; 54110234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.scheduler_nbanks; 54210234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 54310234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 54410234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 54510234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 54610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 54710234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 54810234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 54910234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 55010234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 55110234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.peak_issueW; 55210234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.peak_issueW; 55310234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 55410234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.peak_issueW; 55510234Syasuko.eckert@amd.com interface_ip.is_cache = true; 55610234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 55710234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 55810234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 55910234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 56010234Syasuko.eckert@amd.com int_inst_window = new ArrayST(xml_data, &interface_ip, 56110234Syasuko.eckert@amd.com "InstFetchQueue", Core_device, clockRate, 56210234Syasuko.eckert@amd.com core_params.opt_local, 56310234Syasuko.eckert@amd.com core_params.core_ty); 56410234Syasuko.eckert@amd.com int_inst_window->output_data.area *= core_params.num_pipelines; 56510234Syasuko.eckert@amd.com area.set_area(area.get_area() + int_inst_window->local_result.area * 56610234Syasuko.eckert@amd.com core_params.num_pipelines); 56710234Syasuko.eckert@amd.com Iw_height = int_inst_window->local_result.cache_ht; 56810234Syasuko.eckert@amd.com 56910152Satgutier@umich.edu /* 57010234Syasuko.eckert@amd.com * selection logic 57110234Syasuko.eckert@amd.com * In a single-issue Inorder multithreaded processor like Niagara, issue width=1*number_of_threads since the processor does need to pick up 57210234Syasuko.eckert@amd.com * instructions from multiple ready ones(although these ready ones are from different threads).While SMT processors do not distinguish which thread belongs to who 57310234Syasuko.eckert@amd.com * at the issue stage. 57410152Satgutier@umich.edu */ 57510234Syasuko.eckert@amd.com 57610234Syasuko.eckert@amd.com int_instruction_selection = 57710234Syasuko.eckert@amd.com new selection_logic(xml_data, is_default, 57810234Syasuko.eckert@amd.com core_params.instruction_window_size, 57910234Syasuko.eckert@amd.com core_params.peak_issueW * 58010234Syasuko.eckert@amd.com core_params.num_hthreads, 58110234Syasuko.eckert@amd.com &interface_ip, 58210234Syasuko.eckert@amd.com "Int Instruction Selection Logic", 58310234Syasuko.eckert@amd.com core_stats.inst_window_wakeup_accesses, 58410234Syasuko.eckert@amd.com clockRate, Core_device, core_params.core_ty); 58510234Syasuko.eckert@amd.com 58610234Syasuko.eckert@amd.com if (core_params.fp_instruction_window_size > 0) { 58710234Syasuko.eckert@amd.com fp_instruction_selection = 58810234Syasuko.eckert@amd.com new selection_logic(xml_data, is_default, 58910234Syasuko.eckert@amd.com core_params.fp_instruction_window_size, 59010234Syasuko.eckert@amd.com core_params.fp_issueW * 59110234Syasuko.eckert@amd.com core_params.num_hthreads, 59210234Syasuko.eckert@amd.com &interface_ip, 59310234Syasuko.eckert@amd.com "FP Instruction Selection Logic", 59410234Syasuko.eckert@amd.com core_stats.fp_inst_window_wakeup_accesses, 59510234Syasuko.eckert@amd.com clockRate, Core_device, 59610234Syasuko.eckert@amd.com core_params.core_ty); 59710152Satgutier@umich.edu } 59810234Syasuko.eckert@amd.com } 59910234Syasuko.eckert@amd.com 60010234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 60110152Satgutier@umich.edu /* 60210152Satgutier@umich.edu * CAM based instruction window 60310152Satgutier@umich.edu * For physicalRegFilebased OOO it is the instruction issue queue, where only tags of phy regs are stored 60410152Satgutier@umich.edu * For RS based OOO it is the Reservation station, where both tags and values of phy regs are stored 60510152Satgutier@umich.edu * It is written once and read twice(two operands) before an instruction can be issued. 60610152Satgutier@umich.edu * X86 instruction can be very long up to 15B. add instruction length in XML 60710152Satgutier@umich.edu */ 60810234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 60910234Syasuko.eckert@amd.com tag = core_params.phy_ireg_width; 61010234Syasuko.eckert@amd.com data = int((ceil((core_params.instruction_length + 61110234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * 61210234Syasuko.eckert@amd.com (core_params.phy_ireg_width - 61310234Syasuko.eckert@amd.com core_params.arch_ireg_width)) / 61410234Syasuko.eckert@amd.com (double)NUM_SOURCE_OPERANDS) / 61510234Syasuko.eckert@amd.com BITS_PER_BYTE)); 61610234Syasuko.eckert@amd.com tmp_name = "Integer Instruction Window"; 61710234Syasuko.eckert@amd.com } else { 61810234Syasuko.eckert@amd.com tag = core_params.phy_ireg_width; 61910234Syasuko.eckert@amd.com data = int(ceil(((core_params.instruction_length + 62010234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * 62110234Syasuko.eckert@amd.com (core_params.phy_ireg_width - 62210234Syasuko.eckert@amd.com core_params.arch_ireg_width) + 62310234Syasuko.eckert@amd.com 2 * core_params.int_data_width) / 62410234Syasuko.eckert@amd.com (double)NUM_SOURCE_OPERANDS) / 62510234Syasuko.eckert@amd.com BITS_PER_BYTE)); 62610234Syasuko.eckert@amd.com tmp_name = "Integer Reservation Station"; 62710152Satgutier@umich.edu } 62810234Syasuko.eckert@amd.com 62910234Syasuko.eckert@amd.com size = data * core_params.instruction_window_size; 63010234Syasuko.eckert@amd.com 63110234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 63210234Syasuko.eckert@amd.com interface_ip.line_sz = data; 63310234Syasuko.eckert@amd.com interface_ip.assoc = core_params.scheduler_assoc; 63410234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.scheduler_nbanks; 63510234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 63610234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 63710234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 63810234Syasuko.eckert@amd.com interface_ip.access_mode = Normal; 63910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 64010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 64110234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 64210234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 64310234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 64410234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.peak_issueW; 64510234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.peak_issueW; 64610234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 64710234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.peak_issueW; 64810234Syasuko.eckert@amd.com interface_ip.is_cache = true; 64910234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 65010234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 65110234Syasuko.eckert@amd.com interface_ip.throughput = NUM_SOURCE_OPERANDS * 1.0 / clockRate; 65210234Syasuko.eckert@amd.com interface_ip.latency = NUM_SOURCE_OPERANDS * 1.0 / clockRate; 65310234Syasuko.eckert@amd.com int_inst_window = new ArrayST(xml_data, &interface_ip, tmp_name, 65410234Syasuko.eckert@amd.com Core_device, clockRate, 65510234Syasuko.eckert@amd.com core_params.opt_local, 65610234Syasuko.eckert@amd.com core_params.core_ty); 65710234Syasuko.eckert@amd.com int_inst_window->output_data.area *= core_params.num_pipelines; 65810234Syasuko.eckert@amd.com area.set_area(area.get_area() + int_inst_window->local_result.area * 65910234Syasuko.eckert@amd.com core_params.num_pipelines); 66010234Syasuko.eckert@amd.com Iw_height = int_inst_window->local_result.cache_ht; 66110234Syasuko.eckert@amd.com 66210234Syasuko.eckert@amd.com //FU inst window 66310234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 66410234Syasuko.eckert@amd.com tag = NUM_SOURCE_OPERANDS * core_params.phy_freg_width; 66510234Syasuko.eckert@amd.com data = int(ceil((core_params.instruction_length + 66610234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * 66710234Syasuko.eckert@amd.com (core_params.phy_freg_width - 66810234Syasuko.eckert@amd.com core_params.arch_freg_width)) / BITS_PER_BYTE)); 66910234Syasuko.eckert@amd.com tmp_name = "FP Instruction Window"; 67010234Syasuko.eckert@amd.com } else { 67110234Syasuko.eckert@amd.com tag = NUM_SOURCE_OPERANDS * core_params.phy_ireg_width; 67210234Syasuko.eckert@amd.com data = int(ceil((core_params.instruction_length + 67310234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * 67410234Syasuko.eckert@amd.com (core_params.phy_freg_width - 67510234Syasuko.eckert@amd.com core_params.arch_freg_width) + 67610234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.fp_data_width) / 67710234Syasuko.eckert@amd.com BITS_PER_BYTE)); 67810234Syasuko.eckert@amd.com tmp_name = "FP Reservation Station"; 67910152Satgutier@umich.edu } 68010234Syasuko.eckert@amd.com 68110234Syasuko.eckert@amd.com size = data * core_params.fp_instruction_window_size; 68210234Syasuko.eckert@amd.com 68310234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 68410234Syasuko.eckert@amd.com interface_ip.line_sz = data; 68510234Syasuko.eckert@amd.com interface_ip.assoc = core_params.scheduler_assoc; 68610234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.scheduler_nbanks; 68710234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 68810234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 68910234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 69010234Syasuko.eckert@amd.com interface_ip.access_mode = Normal; 69110152Satgutier@umich.edu interface_ip.obj_func_dyn_energy = 0; 69210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 69310152Satgutier@umich.edu interface_ip.obj_func_leak_power = 0; 69410234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 69510234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 69610234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.fp_issueW; 69710234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.fp_issueW; 69810234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 69910234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.fp_issueW; 70010234Syasuko.eckert@amd.com interface_ip.is_cache = true; 70110234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 70210234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 70310234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 70410234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 70510234Syasuko.eckert@amd.com fp_inst_window = 70610234Syasuko.eckert@amd.com new ArrayST(xml_data, &interface_ip, tmp_name, Core_device, 70710234Syasuko.eckert@amd.com clockRate, core_params.opt_local, core_params.core_ty); 70810234Syasuko.eckert@amd.com fp_inst_window->output_data.area *= core_params.num_fp_pipelines; 70910234Syasuko.eckert@amd.com area.set_area(area.get_area() + fp_inst_window->local_result.area 71010234Syasuko.eckert@amd.com *core_params.num_fp_pipelines); 71110234Syasuko.eckert@amd.com fp_Iw_height = fp_inst_window->local_result.cache_ht; 71210234Syasuko.eckert@amd.com 71310234Syasuko.eckert@amd.com if (core_params.ROB_size > 0) { 71410234Syasuko.eckert@amd.com /* 71510234Syasuko.eckert@amd.com * if ROB_size = 0, then the target processor does not support hardware-based 71610234Syasuko.eckert@amd.com * speculation, i.e. , the processor allow OOO issue as well as OOO completion, which 71710234Syasuko.eckert@amd.com * means branch must be resolved before instruction issued into instruction window, since 71810234Syasuko.eckert@amd.com * there is no change to flush miss-predict branch path after instructions are issued in this situation. 71910234Syasuko.eckert@amd.com * 72010234Syasuko.eckert@amd.com * ROB.ROB size = inflight inst. ROB is unified for int and fp inst. 72110234Syasuko.eckert@amd.com * One old approach is to combine the RAT and ROB as a huge CAM structure as in AMD K7. 72210234Syasuko.eckert@amd.com * However, this approach is abandoned due to its high power and poor scalablility. 72310234Syasuko.eckert@amd.com * McPAT uses current implementation of ROB as circular buffer. 72410234Syasuko.eckert@amd.com * ROB is written once when instruction is issued and read once when the instruction is committed. * 72510234Syasuko.eckert@amd.com */ 72610234Syasuko.eckert@amd.com int robExtra = int(ceil(ROB_STATUS_BITS + 72710234Syasuko.eckert@amd.com log2(core_params.num_hthreads))); 72810234Syasuko.eckert@amd.com 72910234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 73010234Syasuko.eckert@amd.com //PC is to id the instruction for recover exception. 73110234Syasuko.eckert@amd.com //inst is used to map the renamed dest. registers. so that 73210234Syasuko.eckert@amd.com //commit stage can know which reg/RRAT to update 73310234Syasuko.eckert@amd.com data = int(ceil((robExtra + core_params.pc_width + 73410234Syasuko.eckert@amd.com core_params.phy_ireg_width) / BITS_PER_BYTE)); 73510234Syasuko.eckert@amd.com } else { 73610234Syasuko.eckert@amd.com //in RS based OOO, ROB also contains value of destination reg 73710234Syasuko.eckert@amd.com data = int(ceil((robExtra + core_params.pc_width + 73810234Syasuko.eckert@amd.com core_params.phy_ireg_width + 73910234Syasuko.eckert@amd.com core_params.fp_data_width) / BITS_PER_BYTE)); 74010234Syasuko.eckert@amd.com } 74110234Syasuko.eckert@amd.com 74210234Syasuko.eckert@amd.com interface_ip.cache_sz = data * core_params.ROB_size; 74310234Syasuko.eckert@amd.com interface_ip.line_sz = data; 74410234Syasuko.eckert@amd.com interface_ip.assoc = core_params.ROB_assoc; 74510234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.ROB_nbanks; 74610234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 74710234Syasuko.eckert@amd.com interface_ip.specific_tag = core_params.ROB_tag_width > 0; 74810234Syasuko.eckert@amd.com interface_ip.tag_w = core_params.ROB_tag_width; 74910234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 75010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 75110234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 75210234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 75310234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 75410234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 75510234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.peak_commitW; 75610234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.peak_issueW; 75710234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 75810234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 75910234Syasuko.eckert@amd.com interface_ip.is_cache = false; 76010234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 76110234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 76210234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 76310234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 76410234Syasuko.eckert@amd.com ROB = new ArrayST(xml_data, &interface_ip, "Reorder Buffer", 76510234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 76610234Syasuko.eckert@amd.com core_params.core_ty); 76710234Syasuko.eckert@amd.com ROB->output_data.area *= core_params.num_pipelines; 76810234Syasuko.eckert@amd.com area.set_area(area.get_area() + ROB->local_result.area * 76910234Syasuko.eckert@amd.com core_params.num_pipelines); 77010234Syasuko.eckert@amd.com ROB_height = ROB->local_result.cache_ht; 77110152Satgutier@umich.edu } 77210234Syasuko.eckert@amd.com 77310234Syasuko.eckert@amd.com int_instruction_selection = 77410234Syasuko.eckert@amd.com new selection_logic(xml_data, is_default, 77510234Syasuko.eckert@amd.com core_params.instruction_window_size, 77610234Syasuko.eckert@amd.com core_params.peak_issueW, &interface_ip, 77710234Syasuko.eckert@amd.com "Int Instruction Selection Logic", 77810234Syasuko.eckert@amd.com core_stats.inst_window_wakeup_accesses, 77910234Syasuko.eckert@amd.com clockRate, Core_device, core_params.core_ty); 78010234Syasuko.eckert@amd.com 78110234Syasuko.eckert@amd.com if (core_params.fp_instruction_window_size > 0) { 78210234Syasuko.eckert@amd.com fp_instruction_selection = 78310234Syasuko.eckert@amd.com new selection_logic(xml_data, is_default, 78410234Syasuko.eckert@amd.com core_params.fp_instruction_window_size, 78510234Syasuko.eckert@amd.com core_params.fp_issueW, &interface_ip, 78610234Syasuko.eckert@amd.com "FP Instruction Selection Logic", 78710234Syasuko.eckert@amd.com core_stats.fp_inst_window_wakeup_accesses, 78810234Syasuko.eckert@amd.com clockRate, Core_device, 78910234Syasuko.eckert@amd.com core_params.core_ty); 79010152Satgutier@umich.edu } 79110234Syasuko.eckert@amd.com 79210152Satgutier@umich.edu } 79310152Satgutier@umich.edu} 79410152Satgutier@umich.edu 79510234Syasuko.eckert@amd.comLoadStoreU::LoadStoreU(XMLNode* _xml_data, InputParameter* interface_ip_, 79610234Syasuko.eckert@amd.com const CoreParameters & _core_params, 79710234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_) 79810234Syasuko.eckert@amd.com : McPATComponent(_xml_data), dcache(NULL), LSQ(NULL), LoadQ(NULL), 79910234Syasuko.eckert@amd.com interface_ip(*interface_ip_), 80010234Syasuko.eckert@amd.com core_params(_core_params), core_stats(_core_stats), exist(exist_) { 80110234Syasuko.eckert@amd.com if (!exist) return; 80210234Syasuko.eckert@amd.com int tag; 80310234Syasuko.eckert@amd.com int line; 80410234Syasuko.eckert@amd.com int size; 80510234Syasuko.eckert@amd.com int ldst_opcode = core_params.opcode_width; 80610234Syasuko.eckert@amd.com 80710234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 80810234Syasuko.eckert@amd.com name = "Load/Store Unit"; 80910234Syasuko.eckert@amd.com 81010234Syasuko.eckert@amd.com // Check if there is a dcache child: 81110234Syasuko.eckert@amd.com int i; 81210234Syasuko.eckert@amd.com dcache = NULL; 81310234Syasuko.eckert@amd.com for( i = 0; i < xml_data->nChildNode("component"); i++ ) { 81410234Syasuko.eckert@amd.com XMLNode* childXML = xml_data->getChildNodePtr("component", &i); 81510234Syasuko.eckert@amd.com XMLCSTR type = childXML->getAttribute("type"); 81610234Syasuko.eckert@amd.com 81710234Syasuko.eckert@amd.com if (!type) 81810234Syasuko.eckert@amd.com warnMissingComponentType(childXML->getAttribute("id")); 81910234Syasuko.eckert@amd.com 82010234Syasuko.eckert@amd.com STRCMP(type, "CacheUnit") { 82110234Syasuko.eckert@amd.com XMLCSTR name = childXML->getAttribute("name"); 82210234Syasuko.eckert@amd.com if (strcmp(name, "Data Cache") == 0 || 82310234Syasuko.eckert@amd.com strcmp(name, "dcache") == 0) { 82410234Syasuko.eckert@amd.com dcache = new CacheUnit(childXML, &interface_ip); 82510234Syasuko.eckert@amd.com children.push_back(dcache); 82610234Syasuko.eckert@amd.com } 82710152Satgutier@umich.edu } 82810152Satgutier@umich.edu } 82910234Syasuko.eckert@amd.com 83010234Syasuko.eckert@amd.com /* 83110234Syasuko.eckert@amd.com * LSU--in-order processors do not have separate load queue: unified lsq 83210234Syasuko.eckert@amd.com * partitioned among threads 83310234Syasuko.eckert@amd.com * it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ 83410234Syasuko.eckert@amd.com */ 83510234Syasuko.eckert@amd.com tag = ldst_opcode + virtual_address_width + 83610234Syasuko.eckert@amd.com int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS; 83710234Syasuko.eckert@amd.com line = int(ceil(data_path_width / BITS_PER_BYTE)); 83810234Syasuko.eckert@amd.com size = core_params.store_buffer_size * line * core_params.num_hthreads; 83910234Syasuko.eckert@amd.com 84010234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 84110234Syasuko.eckert@amd.com interface_ip.line_sz = line; 84210234Syasuko.eckert@amd.com interface_ip.assoc = core_params.store_buffer_assoc; 84310234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.store_buffer_nbanks; 84410234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 84510234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 84610234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 84710234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 84810234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 84910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 85010234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 85110234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 85210234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 85310234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.memory_ports; 85410234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.memory_ports; 85510234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 85610234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.memory_ports; 85710234Syasuko.eckert@amd.com interface_ip.is_cache = true; 85810234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 85910234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 86010234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 86110234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 86210234Syasuko.eckert@amd.com LSQ = new ArrayST(xml_data, &interface_ip, "Store Queue", Core_device, 86310234Syasuko.eckert@amd.com clockRate, core_params.opt_local, core_params.core_ty); 86410234Syasuko.eckert@amd.com area.set_area(area.get_area() + LSQ->local_result.area); 86510234Syasuko.eckert@amd.com area.set_area(area.get_area()*cdb_overhead); 86610234Syasuko.eckert@amd.com lsq_height = LSQ->local_result.cache_ht * sqrt(cdb_overhead); 86710234Syasuko.eckert@amd.com 86810234Syasuko.eckert@amd.com if ((core_params.core_ty == OOO) && (core_params.load_buffer_size > 0)) { 86910234Syasuko.eckert@amd.com tag = ldst_opcode + virtual_address_width + 87010234Syasuko.eckert@amd.com int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS; 87110234Syasuko.eckert@amd.com line = int(ceil(data_path_width / BITS_PER_BYTE)); 87210234Syasuko.eckert@amd.com size = core_params.load_buffer_size * line * core_params.num_hthreads; 87310234Syasuko.eckert@amd.com 87410234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 87510234Syasuko.eckert@amd.com interface_ip.line_sz = line; 87610234Syasuko.eckert@amd.com interface_ip.assoc = core_params.load_buffer_assoc; 87710234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.load_buffer_nbanks; 87810234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 87910234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 88010234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 88110234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 88210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 88310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 88410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 88510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 88610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 88710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.memory_ports; 88810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.memory_ports; 88910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 89010234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.memory_ports; 89110234Syasuko.eckert@amd.com interface_ip.is_cache = true; 89210234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 89310234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 89410234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 89510234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 89610234Syasuko.eckert@amd.com LoadQ = new ArrayST(xml_data, &interface_ip, "Load Queue", Core_device, 89710234Syasuko.eckert@amd.com clockRate, core_params.opt_local, 89810234Syasuko.eckert@amd.com core_params.core_ty); 89910234Syasuko.eckert@amd.com LoadQ->area.set_area(LoadQ->area.get_area() + 90010234Syasuko.eckert@amd.com LoadQ->local_result.area); 90110234Syasuko.eckert@amd.com area.set_area(area.get_area()*cdb_overhead); 90210234Syasuko.eckert@amd.com lsq_height = (LSQ->local_result.cache_ht + 90310234Syasuko.eckert@amd.com LoadQ->local_result.cache_ht) * sqrt(cdb_overhead); 90410234Syasuko.eckert@amd.com } 90510234Syasuko.eckert@amd.com 90610152Satgutier@umich.edu} 90710152Satgutier@umich.edu 90810234Syasuko.eckert@amd.comMemManU::MemManU(XMLNode* _xml_data, InputParameter* interface_ip_, 90910234Syasuko.eckert@amd.com const CoreParameters & _core_params, 91010234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_) 91110234Syasuko.eckert@amd.com : McPATComponent(_xml_data), itlb(NULL), dtlb(NULL), 91210234Syasuko.eckert@amd.com interface_ip(*interface_ip_), 91310234Syasuko.eckert@amd.com core_params(_core_params), core_stats(_core_stats), exist(exist_) { 91410234Syasuko.eckert@amd.com if (!exist) return; 91510234Syasuko.eckert@amd.com int tag; 91610234Syasuko.eckert@amd.com int data; 91710234Syasuko.eckert@amd.com int line; 91810234Syasuko.eckert@amd.com 91910234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 92010234Syasuko.eckert@amd.com name = "Memory Management Unit"; 92110234Syasuko.eckert@amd.com 92210234Syasuko.eckert@amd.com set_params_stats(); 92310234Syasuko.eckert@amd.com 92410234Syasuko.eckert@amd.com // These are shared between ITLB and DTLB 92510234Syasuko.eckert@amd.com interface_ip.is_cache = true; 92610234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 92710234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 92810234Syasuko.eckert@amd.com //Itlb TLBs are partioned among threads according to Nigara and Nehalem 92910234Syasuko.eckert@amd.com tag = virtual_address_width - int(floor(log2(virtual_memory_page_size))) + 93010234Syasuko.eckert@amd.com int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS; 93110234Syasuko.eckert@amd.com data = physical_address_width - int(floor(log2(virtual_memory_page_size))); 93210234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 93310234Syasuko.eckert@amd.com 93410234Syasuko.eckert@amd.com interface_ip.cache_sz = mem_man_params.itlb_number_entries * line; 93510234Syasuko.eckert@amd.com interface_ip.line_sz = line; 93610234Syasuko.eckert@amd.com interface_ip.assoc = mem_man_params.itlb_assoc; 93710234Syasuko.eckert@amd.com interface_ip.nbanks = mem_man_params.itlb_nbanks; 93810234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 93910234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 94010234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 94110234Syasuko.eckert@amd.com interface_ip.access_mode = Normal; 94210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 94310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 94410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 94510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 94610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.number_instruction_fetch_ports; 94710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = 0; 94810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = 0; 94910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 95010234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.number_instruction_fetch_ports; 95110234Syasuko.eckert@amd.com interface_ip.throughput = mem_man_params.itlb_throughput / clockRate; 95210234Syasuko.eckert@amd.com interface_ip.latency = mem_man_params.itlb_latency / clockRate; 95310234Syasuko.eckert@amd.com itlb = new ArrayST(xml_data, &interface_ip, "Instruction TLB", Core_device, 95410234Syasuko.eckert@amd.com clockRate, core_params.opt_local, core_params.core_ty); 95510234Syasuko.eckert@amd.com area.set_area(area.get_area() + itlb->local_result.area); 95610234Syasuko.eckert@amd.com 95710234Syasuko.eckert@amd.com //dtlb 95810234Syasuko.eckert@amd.com tag = virtual_address_width - int(floor(log2(virtual_memory_page_size))) + 95910234Syasuko.eckert@amd.com int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS; 96010234Syasuko.eckert@amd.com data = physical_address_width - int(floor(log2(virtual_memory_page_size))); 96110234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 96210234Syasuko.eckert@amd.com 96310234Syasuko.eckert@amd.com interface_ip.cache_sz = mem_man_params.dtlb_number_entries * line; 96410234Syasuko.eckert@amd.com interface_ip.line_sz = line; 96510234Syasuko.eckert@amd.com interface_ip.assoc = mem_man_params.dtlb_assoc; 96610234Syasuko.eckert@amd.com interface_ip.nbanks = mem_man_params.dtlb_nbanks; 96710234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 96810234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 96910234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 97010234Syasuko.eckert@amd.com interface_ip.access_mode = Normal; 97110234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 97210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 97310234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 97410234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 97510234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 97610234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.memory_ports; 97710234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.memory_ports; 97810234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 97910234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.memory_ports; 98010234Syasuko.eckert@amd.com interface_ip.throughput = mem_man_params.dtlb_throughput / clockRate; 98110234Syasuko.eckert@amd.com interface_ip.latency = mem_man_params.dtlb_latency / clockRate; 98210234Syasuko.eckert@amd.com dtlb = new ArrayST(xml_data, &interface_ip, "Data TLB", Core_device, 98310234Syasuko.eckert@amd.com clockRate, core_params.opt_local, core_params.core_ty); 98410234Syasuko.eckert@amd.com area.set_area(area.get_area() + dtlb->local_result.area); 98510152Satgutier@umich.edu 98610152Satgutier@umich.edu} 98710152Satgutier@umich.edu 98810234Syasuko.eckert@amd.comvoid 98910234Syasuko.eckert@amd.comMemManU::set_params_stats() { 99010234Syasuko.eckert@amd.com memset(&mem_man_params, 0, sizeof(MemoryManagementParams)); 99110234Syasuko.eckert@amd.com memset(&mem_man_stats, 0, sizeof(MemoryManagementStats)); 99210234Syasuko.eckert@amd.com int num_children = xml_data->nChildNode("component"); 99310234Syasuko.eckert@amd.com int i; 99410234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 99510234Syasuko.eckert@amd.com XMLNode* child = xml_data->getChildNodePtr("component", &i); 99610234Syasuko.eckert@amd.com XMLCSTR type = child->getAttribute("type"); 99710234Syasuko.eckert@amd.com 99810234Syasuko.eckert@amd.com if (!type) 99910234Syasuko.eckert@amd.com warnMissingComponentType(child->getAttribute("id")); 100010234Syasuko.eckert@amd.com 100110234Syasuko.eckert@amd.com STRCMP(type, "InstructionTLB") { 100210234Syasuko.eckert@amd.com int sub_num_children = child->nChildNode("param"); 100310234Syasuko.eckert@amd.com int j; 100410234Syasuko.eckert@amd.com for (j = 0; j < sub_num_children; j++) { 100510234Syasuko.eckert@amd.com XMLNode* paramNode = child->getChildNodePtr("param", &j); 100610234Syasuko.eckert@amd.com XMLCSTR node_name = paramNode->getAttribute("name"); 100710234Syasuko.eckert@amd.com XMLCSTR value = paramNode->getAttribute("value"); 100810234Syasuko.eckert@amd.com 100910234Syasuko.eckert@amd.com if (!node_name) 101010234Syasuko.eckert@amd.com warnMissingParamName(paramNode->getAttribute("id")); 101110234Syasuko.eckert@amd.com 101210234Syasuko.eckert@amd.com ASSIGN_INT_IF("number_entries", 101310234Syasuko.eckert@amd.com mem_man_params.itlb_number_entries); 101410234Syasuko.eckert@amd.com ASSIGN_FP_IF("latency", mem_man_params.itlb_latency); 101510234Syasuko.eckert@amd.com ASSIGN_FP_IF("throughput", mem_man_params.itlb_throughput); 101610234Syasuko.eckert@amd.com ASSIGN_FP_IF("assoc", mem_man_params.itlb_assoc); 101710234Syasuko.eckert@amd.com ASSIGN_FP_IF("nbanks", mem_man_params.itlb_nbanks); 101810234Syasuko.eckert@amd.com 101910234Syasuko.eckert@amd.com else { 102010234Syasuko.eckert@amd.com warnUnrecognizedParam(node_name); 102110152Satgutier@umich.edu } 102210152Satgutier@umich.edu } 102310234Syasuko.eckert@amd.com sub_num_children = child->nChildNode("stat"); 102410234Syasuko.eckert@amd.com for (j = 0; j < sub_num_children; j++) { 102510234Syasuko.eckert@amd.com XMLNode* statNode = child->getChildNodePtr("stat", &j); 102610234Syasuko.eckert@amd.com XMLCSTR node_name = statNode->getAttribute("name"); 102710234Syasuko.eckert@amd.com XMLCSTR value = statNode->getAttribute("value"); 102810234Syasuko.eckert@amd.com 102910234Syasuko.eckert@amd.com if (!node_name) 103010234Syasuko.eckert@amd.com warnMissingStatName(statNode->getAttribute("id")); 103110234Syasuko.eckert@amd.com 103210234Syasuko.eckert@amd.com ASSIGN_FP_IF("total_accesses", 103310234Syasuko.eckert@amd.com mem_man_stats.itlb_total_accesses); 103410234Syasuko.eckert@amd.com ASSIGN_FP_IF("total_misses", mem_man_stats.itlb_total_misses); 103510234Syasuko.eckert@amd.com ASSIGN_FP_IF("conflicts", mem_man_stats.itlb_conflicts); 103610234Syasuko.eckert@amd.com 103710234Syasuko.eckert@amd.com else { 103810234Syasuko.eckert@amd.com warnUnrecognizedStat(node_name); 103910152Satgutier@umich.edu } 104010234Syasuko.eckert@amd.com } 104110234Syasuko.eckert@amd.com } STRCMP(type, "DataTLB") { 104210234Syasuko.eckert@amd.com int sub_num_children = child->nChildNode("param"); 104310234Syasuko.eckert@amd.com int j; 104410234Syasuko.eckert@amd.com for (j = 0; j < sub_num_children; j++) { 104510234Syasuko.eckert@amd.com XMLNode* paramNode = child->getChildNodePtr("param", &j); 104610234Syasuko.eckert@amd.com XMLCSTR node_name = paramNode->getAttribute("name"); 104710234Syasuko.eckert@amd.com XMLCSTR value = paramNode->getAttribute("value"); 104810234Syasuko.eckert@amd.com 104910234Syasuko.eckert@amd.com if (!node_name) 105010234Syasuko.eckert@amd.com warnMissingParamName(paramNode->getAttribute("id")); 105110234Syasuko.eckert@amd.com 105210234Syasuko.eckert@amd.com ASSIGN_INT_IF("number_entries", 105310234Syasuko.eckert@amd.com mem_man_params.dtlb_number_entries); 105410234Syasuko.eckert@amd.com ASSIGN_FP_IF("latency", mem_man_params.dtlb_latency); 105510234Syasuko.eckert@amd.com ASSIGN_FP_IF("throughput", mem_man_params.dtlb_throughput); 105610234Syasuko.eckert@amd.com ASSIGN_FP_IF("assoc", mem_man_params.dtlb_assoc); 105710234Syasuko.eckert@amd.com ASSIGN_FP_IF("nbanks", mem_man_params.dtlb_nbanks); 105810234Syasuko.eckert@amd.com 105910234Syasuko.eckert@amd.com else { 106010234Syasuko.eckert@amd.com warnUnrecognizedParam(node_name); 106110152Satgutier@umich.edu } 106210234Syasuko.eckert@amd.com } 106310234Syasuko.eckert@amd.com sub_num_children = child->nChildNode("stat"); 106410234Syasuko.eckert@amd.com for (j = 0; j < sub_num_children; j++) { 106510234Syasuko.eckert@amd.com XMLNode* statNode = child->getChildNodePtr("stat", &j); 106610234Syasuko.eckert@amd.com XMLCSTR node_name = statNode->getAttribute("name"); 106710234Syasuko.eckert@amd.com XMLCSTR value = statNode->getAttribute("value"); 106810234Syasuko.eckert@amd.com 106910234Syasuko.eckert@amd.com if (!node_name) 107010234Syasuko.eckert@amd.com warnMissingStatName(statNode->getAttribute("id")); 107110234Syasuko.eckert@amd.com 107210234Syasuko.eckert@amd.com ASSIGN_FP_IF("read_accesses", 107310234Syasuko.eckert@amd.com mem_man_stats.dtlb_read_accesses); 107410234Syasuko.eckert@amd.com ASSIGN_FP_IF("read_misses", mem_man_stats.dtlb_read_misses); 107510234Syasuko.eckert@amd.com ASSIGN_FP_IF("write_accesses", 107610234Syasuko.eckert@amd.com mem_man_stats.dtlb_write_accesses); 107710234Syasuko.eckert@amd.com ASSIGN_FP_IF("write_misses", mem_man_stats.dtlb_write_misses); 107810234Syasuko.eckert@amd.com ASSIGN_FP_IF("conflicts", mem_man_stats.dtlb_conflicts); 107910234Syasuko.eckert@amd.com 108010234Syasuko.eckert@amd.com else { 108110234Syasuko.eckert@amd.com warnUnrecognizedStat(node_name); 108210152Satgutier@umich.edu } 108310152Satgutier@umich.edu } 108410152Satgutier@umich.edu } 108510152Satgutier@umich.edu } 108610152Satgutier@umich.edu} 108710152Satgutier@umich.edu 108810234Syasuko.eckert@amd.comRegFU::RegFU(XMLNode* _xml_data, InputParameter* interface_ip_, 108910234Syasuko.eckert@amd.com const CoreParameters & _core_params, 109010234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_) 109110234Syasuko.eckert@amd.com : McPATComponent(_xml_data), IRF(NULL), FRF(NULL), RFWIN(NULL), 109210234Syasuko.eckert@amd.com interface_ip(*interface_ip_), 109310234Syasuko.eckert@amd.com core_params(_core_params), core_stats(_core_stats), exist(exist_) { 109410234Syasuko.eckert@amd.com /* 109510234Syasuko.eckert@amd.com * processors have separate architectural register files for each thread. 109610234Syasuko.eckert@amd.com * therefore, the bypass buses need to travel across all the register files. 109710234Syasuko.eckert@amd.com */ 109810234Syasuko.eckert@amd.com if (!exist) return; 109910234Syasuko.eckert@amd.com int data; 110010234Syasuko.eckert@amd.com int line; 110110234Syasuko.eckert@amd.com 110210234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 110310234Syasuko.eckert@amd.com name = "Register File Unit"; 110410234Syasuko.eckert@amd.com 110510234Syasuko.eckert@amd.com //**********************************IRF************************************ 110610234Syasuko.eckert@amd.com data = core_params.int_data_width; 110710234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 110810234Syasuko.eckert@amd.com 110910234Syasuko.eckert@amd.com interface_ip.cache_sz = core_params.num_IRF_entry * line; 111010234Syasuko.eckert@amd.com interface_ip.line_sz = line; 111110234Syasuko.eckert@amd.com interface_ip.assoc = core_params.phy_Regs_IRF_assoc; 111210234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.phy_Regs_IRF_nbanks; 111310234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 111410234Syasuko.eckert@amd.com interface_ip.specific_tag = core_params.phy_Regs_IRF_tag_width > 0; 111510234Syasuko.eckert@amd.com interface_ip.tag_w = core_params.phy_Regs_IRF_tag_width; 111610234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 111710234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 111810234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 111910234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 112010234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 112110234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 112210234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.phy_Regs_IRF_rd_ports; 112310234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.phy_Regs_IRF_wr_ports; 112410234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 112510234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 112610234Syasuko.eckert@amd.com interface_ip.is_cache = false; 112710234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 112810234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 112910234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 113010234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 113110234Syasuko.eckert@amd.com IRF = new ArrayST(xml_data, &interface_ip, "Integer Register File", 113210234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 113310234Syasuko.eckert@amd.com core_params.core_ty); 113410234Syasuko.eckert@amd.com IRF->output_data.area *= core_params.num_hthreads * 113510234Syasuko.eckert@amd.com core_params.num_pipelines * cdb_overhead; 113610234Syasuko.eckert@amd.com area.set_area(area.get_area() + IRF->local_result.area * 113710234Syasuko.eckert@amd.com core_params.num_hthreads * core_params.num_pipelines * 113810234Syasuko.eckert@amd.com cdb_overhead); 113910234Syasuko.eckert@amd.com 114010234Syasuko.eckert@amd.com //**********************************FRF************************************ 114110234Syasuko.eckert@amd.com data = core_params.fp_data_width; 114210234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 114310234Syasuko.eckert@amd.com 114410234Syasuko.eckert@amd.com interface_ip.cache_sz = core_params.num_FRF_entry * line; 114510234Syasuko.eckert@amd.com interface_ip.line_sz = line; 114610234Syasuko.eckert@amd.com interface_ip.assoc = core_params.phy_Regs_FRF_assoc; 114710234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.phy_Regs_FRF_nbanks; 114810234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 114910234Syasuko.eckert@amd.com interface_ip.specific_tag = core_params.phy_Regs_FRF_tag_width > 0; 115010234Syasuko.eckert@amd.com interface_ip.tag_w = core_params.phy_Regs_FRF_tag_width; 115110234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 115210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 115310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 115410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 115510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 115610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = 0; 115710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.phy_Regs_FRF_rd_ports; 115810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.phy_Regs_FRF_wr_ports; 115910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 116010234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 116110234Syasuko.eckert@amd.com interface_ip.is_cache = false; 116210234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 116310234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 116410234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 116510234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 116610234Syasuko.eckert@amd.com FRF = new ArrayST(xml_data, &interface_ip, "FP Register File", Core_device, 116710234Syasuko.eckert@amd.com clockRate, core_params.opt_local, core_params.core_ty); 116810234Syasuko.eckert@amd.com FRF->output_data.area *= core_params.num_hthreads * 116910234Syasuko.eckert@amd.com core_params.num_fp_pipelines * cdb_overhead; 117010234Syasuko.eckert@amd.com area.set_area(area.get_area() + FRF->local_result.area * 117110234Syasuko.eckert@amd.com core_params.num_hthreads * core_params.num_fp_pipelines * 117210234Syasuko.eckert@amd.com cdb_overhead); 117310234Syasuko.eckert@amd.com int_regfile_height = IRF->local_result.cache_ht * 117410234Syasuko.eckert@amd.com core_params.num_hthreads * sqrt(cdb_overhead); 117510234Syasuko.eckert@amd.com fp_regfile_height = FRF->local_result.cache_ht * core_params.num_hthreads * 117610234Syasuko.eckert@amd.com sqrt(cdb_overhead); 117710234Syasuko.eckert@amd.com //since a EXU is associated with each pipeline, the cdb should not have 117810234Syasuko.eckert@amd.com //longer length. 117910234Syasuko.eckert@amd.com 118010234Syasuko.eckert@amd.com if (core_params.regWindowing) { 118110234Syasuko.eckert@amd.com //*********************************REG_WIN***************************** 118210234Syasuko.eckert@amd.com //ECC, and usually 2 regs are transfered together during window 118310234Syasuko.eckert@amd.com //shifting.Niagara Mega cell 118410234Syasuko.eckert@amd.com data = core_params.int_data_width; 118510234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 118610234Syasuko.eckert@amd.com 118710234Syasuko.eckert@amd.com interface_ip.cache_sz = core_params.register_window_size * 118810234Syasuko.eckert@amd.com IRF->l_ip.cache_sz * core_params.num_hthreads; 118910234Syasuko.eckert@amd.com interface_ip.line_sz = line; 119010234Syasuko.eckert@amd.com interface_ip.assoc = core_params.register_window_assoc; 119110234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.register_window_nbanks; 119210234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 119310234Syasuko.eckert@amd.com interface_ip.specific_tag = core_params.register_window_tag_width > 0; 119410234Syasuko.eckert@amd.com interface_ip.tag_w = core_params.register_window_tag_width; 119510234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 119610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 119710234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 119810234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 119910234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 120010234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.register_window_rw_ports; 120110234Syasuko.eckert@amd.com interface_ip.num_rd_ports = 0; 120210234Syasuko.eckert@amd.com interface_ip.num_wr_ports = 0; 120310234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 120410234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 120510234Syasuko.eckert@amd.com interface_ip.is_cache = false; 120610234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 120710234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 120810234Syasuko.eckert@amd.com interface_ip.throughput = 120910234Syasuko.eckert@amd.com core_params.register_window_throughput / clockRate; 121010234Syasuko.eckert@amd.com interface_ip.latency = 121110234Syasuko.eckert@amd.com core_params.register_window_latency / clockRate; 121210234Syasuko.eckert@amd.com RFWIN = new ArrayST(xml_data, &interface_ip, "RegWindow", Core_device, 121310234Syasuko.eckert@amd.com clockRate, core_params.opt_local, 121410234Syasuko.eckert@amd.com core_params.core_ty); 121510234Syasuko.eckert@amd.com RFWIN->output_data.area *= core_params.num_pipelines; 121610234Syasuko.eckert@amd.com area.set_area(area.get_area() + RFWIN->local_result.area * 121710234Syasuko.eckert@amd.com core_params.num_pipelines); 121810234Syasuko.eckert@amd.com } 121910234Syasuko.eckert@amd.com} 122010234Syasuko.eckert@amd.com 122110234Syasuko.eckert@amd.comEXECU::EXECU(XMLNode* _xml_data, 122210234Syasuko.eckert@amd.com InputParameter* interface_ip_, double lsq_height_, 122310234Syasuko.eckert@amd.com const CoreParameters & _core_params, 122410234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_) 122510234Syasuko.eckert@amd.com : McPATComponent(_xml_data), rfu(NULL), scheu(NULL), fp_u(NULL), 122610234Syasuko.eckert@amd.com exeu(NULL), mul(NULL), int_bypass(NULL), intTagBypass(NULL), 122710234Syasuko.eckert@amd.com int_mul_bypass(NULL), intTag_mul_Bypass(NULL), fp_bypass(NULL), 122810234Syasuko.eckert@amd.com fpTagBypass(NULL), interface_ip(*interface_ip_), 122910234Syasuko.eckert@amd.com lsq_height(lsq_height_), core_params(_core_params), 123010234Syasuko.eckert@amd.com core_stats(_core_stats), exist(exist_) { 123110234Syasuko.eckert@amd.com if (!exist) return; 123210234Syasuko.eckert@amd.com double fu_height = 0.0; 123310234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 123410234Syasuko.eckert@amd.com name = "Execution Unit"; 123510234Syasuko.eckert@amd.com rfu = new RegFU(xml_data, &interface_ip, core_params, core_stats); 123610234Syasuko.eckert@amd.com if (core_params.core_ty == OOO || 123710234Syasuko.eckert@amd.com (core_params.core_ty == Inorder && core_params.multithreaded)) { 123810234Syasuko.eckert@amd.com scheu = new SchedulerU(xml_data, &interface_ip, core_params, 123910234Syasuko.eckert@amd.com core_stats); 124010234Syasuko.eckert@amd.com area.set_area(area.get_area() + scheu->area.get_area() ); 124110234Syasuko.eckert@amd.com } 124210234Syasuko.eckert@amd.com exeu = new FunctionalUnit(xml_data, &interface_ip, core_params, 124310234Syasuko.eckert@amd.com core_stats, ALU); 124410234Syasuko.eckert@amd.com area.set_area(area.get_area() + exeu->area.get_area() + 124510234Syasuko.eckert@amd.com rfu->area.get_area()); 124610234Syasuko.eckert@amd.com fu_height = exeu->FU_height; 124710234Syasuko.eckert@amd.com if (core_params.num_fpus > 0) { 124810234Syasuko.eckert@amd.com fp_u = new FunctionalUnit(xml_data, &interface_ip, 124910234Syasuko.eckert@amd.com core_params, core_stats, FPU); 125010234Syasuko.eckert@amd.com area.set_area(area.get_area() + fp_u->area.get_area()); 125110234Syasuko.eckert@amd.com } 125210234Syasuko.eckert@amd.com if (core_params.num_muls > 0) { 125310234Syasuko.eckert@amd.com mul = new FunctionalUnit(xml_data, &interface_ip, 125410234Syasuko.eckert@amd.com core_params, core_stats, MUL); 125510234Syasuko.eckert@amd.com area.set_area(area.get_area() + mul->area.get_area()); 125610234Syasuko.eckert@amd.com fu_height += mul->FU_height; 125710234Syasuko.eckert@amd.com } 125810234Syasuko.eckert@amd.com /* 125910234Syasuko.eckert@amd.com * broadcast logic, including int-broadcast; int_tag-broadcast; 126010234Syasuko.eckert@amd.com * fp-broadcast; fp_tag-broadcast 126110234Syasuko.eckert@amd.com * integer by pass has two paths and fp has 3 paths. 126210234Syasuko.eckert@amd.com * on the same bus there are multiple tri-state drivers and muxes that go 126310234Syasuko.eckert@amd.com * to different components on the same bus 126410234Syasuko.eckert@amd.com */ 126510234Syasuko.eckert@amd.com interface_ip.wt = core_params.execu_broadcast_wt; 126610234Syasuko.eckert@amd.com interface_ip.wire_is_mat_type = core_params.execu_wire_mat_type; 126710234Syasuko.eckert@amd.com interface_ip.wire_os_mat_type = core_params.execu_wire_mat_type; 126810234Syasuko.eckert@amd.com interface_ip.throughput = core_params.broadcast_numerator / clockRate; 126910234Syasuko.eckert@amd.com interface_ip.latency = core_params.broadcast_numerator / clockRate; 127010234Syasuko.eckert@amd.com double scheu_Iw_height = 0.0; 127110234Syasuko.eckert@amd.com double scheu_ROB_height = 0.0; 127210234Syasuko.eckert@amd.com double scheu_fp_Iw_height = 0.0; 127310234Syasuko.eckert@amd.com if (scheu) { 127410234Syasuko.eckert@amd.com scheu_Iw_height = scheu->Iw_height; 127510234Syasuko.eckert@amd.com scheu_ROB_height = scheu->ROB_height; 127610234Syasuko.eckert@amd.com scheu_fp_Iw_height = scheu->fp_Iw_height; 127710234Syasuko.eckert@amd.com } 127810234Syasuko.eckert@amd.com 127910234Syasuko.eckert@amd.com // Common bypass logic parameters 128010234Syasuko.eckert@amd.com double base_w = core_params.execu_bypass_base_width; 128110234Syasuko.eckert@amd.com double base_h = core_params.execu_bypass_base_height; 128210234Syasuko.eckert@amd.com int level = core_params.execu_bypass_start_wiring_level; 128310234Syasuko.eckert@amd.com double route_over_perc = core_params.execu_bypass_route_over_perc; 128410234Syasuko.eckert@amd.com Wire_type wire_type = core_params.execu_bypass_wire_type; 128510234Syasuko.eckert@amd.com int data_w; 128610234Syasuko.eckert@amd.com double len; 128710234Syasuko.eckert@amd.com 128810234Syasuko.eckert@amd.com if (core_params.core_ty == Inorder) { 128910234Syasuko.eckert@amd.com data_w = int(ceil(data_path_width / 32.0)*32); 129010234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + lsq_height; 129110234Syasuko.eckert@amd.com int_bypass = new Interconnect(xml_data, "Int Bypass Data", Core_device, 129210234Syasuko.eckert@amd.com base_w, base_h, data_w, len, 129310234Syasuko.eckert@amd.com &interface_ip, level, clockRate, false, 129410234Syasuko.eckert@amd.com route_over_perc, core_params.opt_local, 129510234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 129610234Syasuko.eckert@amd.com 129710234Syasuko.eckert@amd.com data_w = core_params.perThreadState; 129810234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + lsq_height + 129910234Syasuko.eckert@amd.com scheu_Iw_height; 130010234Syasuko.eckert@amd.com intTagBypass = new Interconnect(xml_data, "Int Bypass Tag", 130110234Syasuko.eckert@amd.com Core_device, 130210234Syasuko.eckert@amd.com base_w, base_h, data_w, len, 130310234Syasuko.eckert@amd.com &interface_ip, level, clockRate, false, 130410234Syasuko.eckert@amd.com route_over_perc, core_params.opt_local, 130510234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 130610234Syasuko.eckert@amd.com 130710234Syasuko.eckert@amd.com if (core_params.num_muls > 0) { 130810234Syasuko.eckert@amd.com data_w = int(ceil(data_path_width / 32.0)*32*1.5); 130910234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + exeu->FU_height + mul->FU_height + 131010234Syasuko.eckert@amd.com lsq_height; 131110234Syasuko.eckert@amd.com int_mul_bypass = new Interconnect(xml_data, "Mul Bypass Data", 131210234Syasuko.eckert@amd.com Core_device, base_w, base_h, 131310234Syasuko.eckert@amd.com data_w, len, &interface_ip, 131410234Syasuko.eckert@amd.com level, clockRate, false, 131510234Syasuko.eckert@amd.com route_over_perc, 131610234Syasuko.eckert@amd.com core_params.opt_local, 131710234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 131810234Syasuko.eckert@amd.com 131910234Syasuko.eckert@amd.com data_w = core_params.perThreadState; 132010234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + exeu->FU_height + mul->FU_height + 132110234Syasuko.eckert@amd.com lsq_height + scheu_Iw_height; 132210234Syasuko.eckert@amd.com intTag_mul_Bypass = new Interconnect(xml_data, "Mul Bypass Tag", 132310234Syasuko.eckert@amd.com Core_device, base_w, base_h, 132410234Syasuko.eckert@amd.com data_w, len, &interface_ip, 132510234Syasuko.eckert@amd.com level, clockRate, false, 132610234Syasuko.eckert@amd.com route_over_perc, 132710234Syasuko.eckert@amd.com core_params.opt_local, 132810234Syasuko.eckert@amd.com core_params.core_ty, 132910234Syasuko.eckert@amd.com wire_type); 133010152Satgutier@umich.edu } 133110234Syasuko.eckert@amd.com 133210234Syasuko.eckert@amd.com if (core_params.num_fpus > 0) { 133310234Syasuko.eckert@amd.com data_w = int(ceil(data_path_width / 32.0)*32*1.5); 133410234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + fp_u->FU_height; 133510234Syasuko.eckert@amd.com fp_bypass = new Interconnect(xml_data, "FP Bypass Data", 133610234Syasuko.eckert@amd.com Core_device, 133710234Syasuko.eckert@amd.com base_w, base_h, data_w, len, 133810234Syasuko.eckert@amd.com &interface_ip, level, clockRate, 133910234Syasuko.eckert@amd.com false, route_over_perc, 134010234Syasuko.eckert@amd.com core_params.opt_local, 134110234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 134210234Syasuko.eckert@amd.com 134310234Syasuko.eckert@amd.com data_w = core_params.perThreadState; 134410234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + fp_u->FU_height + lsq_height + 134510234Syasuko.eckert@amd.com scheu_Iw_height; 134610234Syasuko.eckert@amd.com fpTagBypass = new Interconnect(xml_data, "FP Bypass Tag", 134710234Syasuko.eckert@amd.com Core_device, base_w, base_h, data_w, 134810234Syasuko.eckert@amd.com len, &interface_ip, level, 134910234Syasuko.eckert@amd.com clockRate, false, route_over_perc, 135010234Syasuko.eckert@amd.com core_params.opt_local, 135110234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 135210152Satgutier@umich.edu } 135310234Syasuko.eckert@amd.com } else {//OOO 135410234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 135510234Syasuko.eckert@amd.com /* For physical register based OOO, 135610234Syasuko.eckert@amd.com * data broadcast interconnects cover across functional units, lsq, 135710234Syasuko.eckert@amd.com * inst windows and register files, 135810234Syasuko.eckert@amd.com * while tag broadcast interconnects also cover across ROB 135910234Syasuko.eckert@amd.com */ 136010234Syasuko.eckert@amd.com data_w = int(ceil(core_params.int_data_width)); 136110234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + lsq_height; 136210234Syasuko.eckert@amd.com int_bypass = new Interconnect(xml_data, "Int Bypass Data", 136310234Syasuko.eckert@amd.com Core_device, base_w, base_h, data_w, 136410234Syasuko.eckert@amd.com len, &interface_ip, level, clockRate, 136510234Syasuko.eckert@amd.com false, route_over_perc, 136610234Syasuko.eckert@amd.com core_params.opt_local, 136710234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 136810234Syasuko.eckert@amd.com 136910234Syasuko.eckert@amd.com data_w = core_params.phy_ireg_width; 137010234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + lsq_height + 137110234Syasuko.eckert@amd.com scheu_Iw_height + scheu_ROB_height; 137210234Syasuko.eckert@amd.com intTagBypass = new Interconnect(xml_data, "Int Bypass Tag", 137310234Syasuko.eckert@amd.com Core_device, base_w, base_h, 137410234Syasuko.eckert@amd.com data_w, len, &interface_ip, level, 137510234Syasuko.eckert@amd.com clockRate, false, route_over_perc, 137610234Syasuko.eckert@amd.com core_params.opt_local, 137710234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 137810234Syasuko.eckert@amd.com 137910234Syasuko.eckert@amd.com if (core_params.num_muls > 0) { 138010234Syasuko.eckert@amd.com data_w = int(ceil(core_params.int_data_width)); 138110234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + 138210234Syasuko.eckert@amd.com mul->FU_height + lsq_height; 138310234Syasuko.eckert@amd.com int_mul_bypass = new Interconnect(xml_data, "Mul Bypass Data", 138410234Syasuko.eckert@amd.com Core_device, base_w, base_h, 138510234Syasuko.eckert@amd.com data_w, len, &interface_ip, 138610234Syasuko.eckert@amd.com level, clockRate, false, 138710234Syasuko.eckert@amd.com route_over_perc, 138810234Syasuko.eckert@amd.com core_params.opt_local, 138910234Syasuko.eckert@amd.com core_params.core_ty, 139010234Syasuko.eckert@amd.com wire_type); 139110234Syasuko.eckert@amd.com 139210234Syasuko.eckert@amd.com data_w = core_params.phy_ireg_width; 139310234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + 139410234Syasuko.eckert@amd.com mul->FU_height + lsq_height + scheu_Iw_height + 139510234Syasuko.eckert@amd.com scheu_ROB_height; 139610234Syasuko.eckert@amd.com intTag_mul_Bypass = new Interconnect(xml_data, 139710234Syasuko.eckert@amd.com "Mul Bypass Tag", 139810234Syasuko.eckert@amd.com Core_device, base_w, 139910234Syasuko.eckert@amd.com base_h, data_w, len, 140010234Syasuko.eckert@amd.com &interface_ip, level, 140110234Syasuko.eckert@amd.com clockRate, false, 140210234Syasuko.eckert@amd.com route_over_perc, 140310234Syasuko.eckert@amd.com core_params.opt_local, 140410234Syasuko.eckert@amd.com core_params.core_ty, 140510234Syasuko.eckert@amd.com wire_type); 140610152Satgutier@umich.edu } 140710234Syasuko.eckert@amd.com 140810234Syasuko.eckert@amd.com if (core_params.num_fpus > 0) { 140910234Syasuko.eckert@amd.com data_w = int(ceil(core_params.fp_data_width)); 141010234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + fp_u->FU_height; 141110234Syasuko.eckert@amd.com fp_bypass = new Interconnect(xml_data, "FP Bypass Data", 141210234Syasuko.eckert@amd.com Core_device, base_w, base_h, 141310234Syasuko.eckert@amd.com data_w, len, &interface_ip, level, 141410234Syasuko.eckert@amd.com clockRate, false, route_over_perc, 141510234Syasuko.eckert@amd.com core_params.opt_local, 141610234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 141710234Syasuko.eckert@amd.com 141810234Syasuko.eckert@amd.com data_w = core_params.phy_freg_width; 141910234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + fp_u->FU_height + lsq_height + 142010234Syasuko.eckert@amd.com scheu_fp_Iw_height + scheu_ROB_height; 142110234Syasuko.eckert@amd.com fpTagBypass = new Interconnect(xml_data, "FP Bypass Tag", 142210234Syasuko.eckert@amd.com Core_device, base_w, base_h, 142310234Syasuko.eckert@amd.com data_w, len, &interface_ip, 142410234Syasuko.eckert@amd.com level, clockRate, false, 142510234Syasuko.eckert@amd.com route_over_perc, 142610234Syasuko.eckert@amd.com core_params.opt_local, 142710234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 142810152Satgutier@umich.edu } 142910234Syasuko.eckert@amd.com } else { 143010234Syasuko.eckert@amd.com /* 143110234Syasuko.eckert@amd.com * In RS based processor both data and tag are broadcast together, 143210234Syasuko.eckert@amd.com * covering functional units, lsq, nst windows, register files, and ROBs 143310234Syasuko.eckert@amd.com */ 143410234Syasuko.eckert@amd.com data_w = int(ceil(core_params.int_data_width)); 143510234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + lsq_height + 143610234Syasuko.eckert@amd.com scheu_Iw_height + scheu_ROB_height; 143710234Syasuko.eckert@amd.com int_bypass = new Interconnect(xml_data, "Int Bypass Data", 143810234Syasuko.eckert@amd.com Core_device, base_w, base_h, data_w, 143910234Syasuko.eckert@amd.com len, &interface_ip, level, clockRate, 144010234Syasuko.eckert@amd.com false, route_over_perc, 144110234Syasuko.eckert@amd.com core_params.opt_local, 144210234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 144310234Syasuko.eckert@amd.com 144410234Syasuko.eckert@amd.com data_w = core_params.phy_ireg_width; 144510234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + lsq_height + 144610234Syasuko.eckert@amd.com scheu_Iw_height + scheu_ROB_height; 144710234Syasuko.eckert@amd.com intTagBypass = new Interconnect(xml_data, "Int Bypass Tag", 144810234Syasuko.eckert@amd.com Core_device, base_w, base_h, 144910234Syasuko.eckert@amd.com data_w, len, &interface_ip, level, 145010234Syasuko.eckert@amd.com clockRate, false, route_over_perc, 145110234Syasuko.eckert@amd.com core_params.opt_local, 145210234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 145310234Syasuko.eckert@amd.com if (core_params.num_muls > 0) { 145410234Syasuko.eckert@amd.com data_w = int(ceil(core_params.int_data_width)); 145510234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + 145610234Syasuko.eckert@amd.com mul->FU_height + lsq_height + scheu_Iw_height + 145710234Syasuko.eckert@amd.com scheu_ROB_height; 145810234Syasuko.eckert@amd.com int_mul_bypass = new Interconnect(xml_data, "Mul Bypass Data", 145910234Syasuko.eckert@amd.com Core_device, base_w, base_h, 146010234Syasuko.eckert@amd.com data_w, len, &interface_ip, 146110234Syasuko.eckert@amd.com level, clockRate, false, 146210234Syasuko.eckert@amd.com route_over_perc, 146310234Syasuko.eckert@amd.com core_params.opt_local, 146410234Syasuko.eckert@amd.com core_params.core_ty, 146510234Syasuko.eckert@amd.com wire_type); 146610234Syasuko.eckert@amd.com 146710234Syasuko.eckert@amd.com data_w = core_params.phy_ireg_width; 146810234Syasuko.eckert@amd.com len = rfu->int_regfile_height + exeu->FU_height + 146910234Syasuko.eckert@amd.com mul->FU_height + lsq_height + scheu_Iw_height + 147010234Syasuko.eckert@amd.com scheu_ROB_height; 147110234Syasuko.eckert@amd.com intTag_mul_Bypass = new Interconnect(xml_data, 147210234Syasuko.eckert@amd.com "Mul Bypass Tag", 147310234Syasuko.eckert@amd.com Core_device, base_w, 147410234Syasuko.eckert@amd.com base_h, data_w, len, 147510234Syasuko.eckert@amd.com &interface_ip, level, 147610234Syasuko.eckert@amd.com clockRate, false, 147710234Syasuko.eckert@amd.com route_over_perc, 147810234Syasuko.eckert@amd.com core_params.opt_local, 147910234Syasuko.eckert@amd.com core_params.core_ty, 148010234Syasuko.eckert@amd.com wire_type); 148110234Syasuko.eckert@amd.com } 148210234Syasuko.eckert@amd.com 148310234Syasuko.eckert@amd.com if (core_params.num_fpus > 0) { 148410234Syasuko.eckert@amd.com data_w = int(ceil(core_params.fp_data_width)); 148510234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + fp_u->FU_height + lsq_height + 148610234Syasuko.eckert@amd.com scheu_fp_Iw_height + scheu_ROB_height; 148710234Syasuko.eckert@amd.com fp_bypass = new Interconnect(xml_data, "FP Bypass Data", 148810234Syasuko.eckert@amd.com Core_device, base_w, base_h, 148910234Syasuko.eckert@amd.com data_w, len, &interface_ip, level, 149010234Syasuko.eckert@amd.com clockRate, false, route_over_perc, 149110234Syasuko.eckert@amd.com core_params.opt_local, 149210234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 149310234Syasuko.eckert@amd.com 149410234Syasuko.eckert@amd.com data_w = core_params.phy_freg_width; 149510234Syasuko.eckert@amd.com len = rfu->fp_regfile_height + fp_u->FU_height + lsq_height + 149610234Syasuko.eckert@amd.com scheu_fp_Iw_height + scheu_ROB_height; 149710234Syasuko.eckert@amd.com fpTagBypass = new Interconnect(xml_data, "FP Bypass Tag", 149810234Syasuko.eckert@amd.com Core_device, base_w, base_h, 149910234Syasuko.eckert@amd.com data_w, len, &interface_ip, 150010234Syasuko.eckert@amd.com level, clockRate, false, 150110234Syasuko.eckert@amd.com route_over_perc, 150210234Syasuko.eckert@amd.com core_params.opt_local, 150310234Syasuko.eckert@amd.com core_params.core_ty, wire_type); 150410234Syasuko.eckert@amd.com } 150510152Satgutier@umich.edu } 150610152Satgutier@umich.edu } 150710234Syasuko.eckert@amd.com if (int_bypass) { 150810234Syasuko.eckert@amd.com children.push_back(int_bypass); 150910234Syasuko.eckert@amd.com } 151010234Syasuko.eckert@amd.com if (intTagBypass) { 151110234Syasuko.eckert@amd.com children.push_back(intTagBypass); 151210234Syasuko.eckert@amd.com } 151310234Syasuko.eckert@amd.com if (int_mul_bypass) { 151410234Syasuko.eckert@amd.com children.push_back(int_mul_bypass); 151510234Syasuko.eckert@amd.com } 151610234Syasuko.eckert@amd.com if (intTag_mul_Bypass) { 151710234Syasuko.eckert@amd.com children.push_back(intTag_mul_Bypass); 151810234Syasuko.eckert@amd.com } 151910234Syasuko.eckert@amd.com if (fp_bypass) { 152010234Syasuko.eckert@amd.com children.push_back(fp_bypass); 152110234Syasuko.eckert@amd.com } 152210234Syasuko.eckert@amd.com if (fpTagBypass) { 152310234Syasuko.eckert@amd.com children.push_back(fpTagBypass); 152410234Syasuko.eckert@amd.com } 152510234Syasuko.eckert@amd.com 152610234Syasuko.eckert@amd.com area.set_area(area.get_area() + int_bypass->area.get_area() + 152710234Syasuko.eckert@amd.com intTagBypass->area.get_area()); 152810234Syasuko.eckert@amd.com if (core_params.num_muls > 0) { 152910234Syasuko.eckert@amd.com area.set_area(area.get_area() + int_mul_bypass->area.get_area() + 153010234Syasuko.eckert@amd.com intTag_mul_Bypass->area.get_area()); 153110234Syasuko.eckert@amd.com } 153210234Syasuko.eckert@amd.com if (core_params.num_fpus > 0) { 153310234Syasuko.eckert@amd.com area.set_area(area.get_area() + fp_bypass->area.get_area() + 153410234Syasuko.eckert@amd.com fpTagBypass->area.get_area()); 153510234Syasuko.eckert@amd.com } 153610234Syasuko.eckert@amd.com} 153710234Syasuko.eckert@amd.com 153810234Syasuko.eckert@amd.comRENAMINGU::RENAMINGU(XMLNode* _xml_data, InputParameter* interface_ip_, 153910234Syasuko.eckert@amd.com const CoreParameters & _core_params, 154010234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_) 154110234Syasuko.eckert@amd.com : McPATComponent(_xml_data), iFRAT(NULL), fFRAT(NULL), iRRAT(NULL), 154210234Syasuko.eckert@amd.com fRRAT(NULL), ifreeL(NULL), ffreeL(NULL), idcl(NULL), fdcl(NULL), 154310234Syasuko.eckert@amd.com RAHT(NULL), interface_ip(*interface_ip_), 154410234Syasuko.eckert@amd.com core_params(_core_params), core_stats(_core_stats), exist(exist_) { 154510234Syasuko.eckert@amd.com if (!exist) return; 154610234Syasuko.eckert@amd.com int tag; 154710234Syasuko.eckert@amd.com int data; 154810234Syasuko.eckert@amd.com int out_w; 154910234Syasuko.eckert@amd.com int size; 155010234Syasuko.eckert@amd.com 155110234Syasuko.eckert@amd.com // Assumption: 155210234Syasuko.eckert@amd.com // We make an implicit design assumption based on the specific structure 155310234Syasuko.eckert@amd.com // that is being modeled. 155410234Syasuko.eckert@amd.com // 1. RAM-based RATs are direct mapped. However, if the associated 155510234Syasuko.eckert@amd.com // scheduler is a reservation station style, the RATs are fully 155610234Syasuko.eckert@amd.com // associative. 155710234Syasuko.eckert@amd.com // 2. Non-CAM based RATs and free lists do not have tags. 155810234Syasuko.eckert@amd.com // 3. Free lists are direct mapped. 155910234Syasuko.eckert@amd.com 156010234Syasuko.eckert@amd.com const int RAM_BASED_RAT_ASSOC = 1; 156110234Syasuko.eckert@amd.com const int RS_RAT_ASSOC = 0; 156210234Syasuko.eckert@amd.com const int NON_CAM_BASED_TAG_WIDTH = 0; 156310234Syasuko.eckert@amd.com const int FREELIST_ASSOC = 1; 156410234Syasuko.eckert@amd.com 156510234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 156610234Syasuko.eckert@amd.com name = "Rename Unit"; 156710234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 156810234Syasuko.eckert@amd.com //integer pipeline 156910234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 157010234Syasuko.eckert@amd.com if (core_params.rm_ty == RAMbased) { 157110234Syasuko.eckert@amd.com //FRAT with global checkpointing (GCs) please see paper tech 157210234Syasuko.eckert@amd.com //report for detailed explaintions 157310234Syasuko.eckert@amd.com 157410234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_ireg_width * 157510234Syasuko.eckert@amd.com (1 + core_params.globalCheckpoint) / 157610234Syasuko.eckert@amd.com BITS_PER_BYTE)); 157710234Syasuko.eckert@amd.com out_w = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE)); 157810234Syasuko.eckert@amd.com 157910234Syasuko.eckert@amd.com size = data * core_params.archi_Regs_IRF_size; 158010234Syasuko.eckert@amd.com 158110234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 158210234Syasuko.eckert@amd.com interface_ip.line_sz = data; 158310234Syasuko.eckert@amd.com interface_ip.assoc = RAM_BASED_RAT_ASSOC; 158410234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 158510234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 158610234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 158710234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 158810234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 158910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 159010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 159110234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 159210234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 159310234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 159410234Syasuko.eckert@amd.com interface_ip.num_rd_ports = 159510234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.decodeW; 159610234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.decodeW; 159710234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 159810234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 159910234Syasuko.eckert@amd.com interface_ip.is_cache = false; 160010234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 160110234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 160210234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 160310234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 160410234Syasuko.eckert@amd.com iFRAT = new ArrayST(xml_data, &interface_ip, "Int Front RAT", 160510234Syasuko.eckert@amd.com Core_device, clockRate, 160610234Syasuko.eckert@amd.com core_params.opt_local, 160710234Syasuko.eckert@amd.com core_params.core_ty); 160810234Syasuko.eckert@amd.com iFRAT->output_data.area *= core_params.num_hthreads; 160910234Syasuko.eckert@amd.com area.set_area(area.get_area() + iFRAT->area.get_area()); 161010234Syasuko.eckert@amd.com 161110234Syasuko.eckert@amd.com //FRAT floating point 161210234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_freg_width * 161310234Syasuko.eckert@amd.com (1 + core_params.globalCheckpoint) / 161410234Syasuko.eckert@amd.com BITS_PER_BYTE)); 161510234Syasuko.eckert@amd.com out_w = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE)); 161610234Syasuko.eckert@amd.com size = data * core_params.archi_Regs_FRF_size; 161710234Syasuko.eckert@amd.com 161810234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 161910234Syasuko.eckert@amd.com interface_ip.line_sz = data; 162010234Syasuko.eckert@amd.com interface_ip.assoc = RAM_BASED_RAT_ASSOC; 162110234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 162210234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 162310234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 162410234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 162510234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 162610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 162710234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 162810234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 162910234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 163010234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 163110234Syasuko.eckert@amd.com interface_ip.num_rd_ports = 163210234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.fp_decodeW; 163310234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.fp_decodeW; 163410234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 163510234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 163610234Syasuko.eckert@amd.com interface_ip.is_cache = false; 163710234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 163810234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 163910234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 164010234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 164110234Syasuko.eckert@amd.com fFRAT = new ArrayST(xml_data, &interface_ip, "FP Front RAT", 164210234Syasuko.eckert@amd.com Core_device, clockRate, 164310234Syasuko.eckert@amd.com core_params.opt_local, 164410234Syasuko.eckert@amd.com core_params.core_ty); 164510234Syasuko.eckert@amd.com fFRAT->output_data.area *= core_params.num_hthreads; 164610234Syasuko.eckert@amd.com area.set_area(area.get_area() + fFRAT->area.get_area()); 164710234Syasuko.eckert@amd.com 164810234Syasuko.eckert@amd.com } else if ((core_params.rm_ty == CAMbased)) { 164910234Syasuko.eckert@amd.com //IRAT 165010234Syasuko.eckert@amd.com tag = core_params.arch_ireg_width; 165110234Syasuko.eckert@amd.com //the address of CAM needed to be sent out 165210234Syasuko.eckert@amd.com data = int(ceil((core_params.arch_ireg_width + 1 * 165310234Syasuko.eckert@amd.com core_params.globalCheckpoint) / 165410234Syasuko.eckert@amd.com BITS_PER_BYTE)); 165510234Syasuko.eckert@amd.com out_w = int(ceil(core_params.arch_ireg_width / BITS_PER_BYTE)); 165610234Syasuko.eckert@amd.com size = data * core_params.phy_Regs_IRF_size; 165710234Syasuko.eckert@amd.com 165810234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 165910234Syasuko.eckert@amd.com interface_ip.line_sz = data; 166010234Syasuko.eckert@amd.com interface_ip.assoc = CAM_ASSOC; 166110234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 166210234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 166310234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 166410234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 166510234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 166610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 166710234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 166810234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 166910234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 167010234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 167110234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.decodeW; 167210234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.decodeW; 167310234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 167410234Syasuko.eckert@amd.com interface_ip.num_search_ports = 167510234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.decodeW; 167610234Syasuko.eckert@amd.com interface_ip.is_cache = true; 167710234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 167810234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 167910234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 168010234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 168110234Syasuko.eckert@amd.com iFRAT = new ArrayST(xml_data, &interface_ip, "Int Front RAT", 168210234Syasuko.eckert@amd.com Core_device, clockRate, 168310234Syasuko.eckert@amd.com core_params.opt_local, 168410234Syasuko.eckert@amd.com core_params.core_ty); 168510234Syasuko.eckert@amd.com iFRAT->output_data.area *= core_params.num_hthreads; 168610234Syasuko.eckert@amd.com area.set_area(area.get_area() + iFRAT->area.get_area()); 168710234Syasuko.eckert@amd.com 168810234Syasuko.eckert@amd.com //FRAT for FP 168910234Syasuko.eckert@amd.com tag = core_params.arch_freg_width; 169010234Syasuko.eckert@amd.com //the address of CAM needed to be sent out 169110234Syasuko.eckert@amd.com data = int(ceil((core_params.arch_freg_width + 1 * 169210234Syasuko.eckert@amd.com core_params.globalCheckpoint) / 169310234Syasuko.eckert@amd.com BITS_PER_BYTE)); 169410234Syasuko.eckert@amd.com out_w = int(ceil(core_params.arch_freg_width / BITS_PER_BYTE)); 169510234Syasuko.eckert@amd.com size = data * core_params.phy_Regs_FRF_size; 169610234Syasuko.eckert@amd.com 169710234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 169810234Syasuko.eckert@amd.com interface_ip.line_sz = data; 169910234Syasuko.eckert@amd.com interface_ip.assoc = CAM_ASSOC; 170010234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 170110234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 170210234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 170310234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 170410234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 170510234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 170610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 170710234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 170810234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 170910234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 171010234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.fp_decodeW; 171110234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.fp_decodeW; 171210234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 171310234Syasuko.eckert@amd.com interface_ip.num_search_ports = 171410234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.fp_decodeW; 171510234Syasuko.eckert@amd.com interface_ip.is_cache = true; 171610234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 171710234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 171810234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 171910234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 172010234Syasuko.eckert@amd.com fFRAT = new ArrayST(xml_data, &interface_ip, "FP Front RAT", 172110234Syasuko.eckert@amd.com Core_device, clockRate, 172210234Syasuko.eckert@amd.com core_params.opt_local, 172310234Syasuko.eckert@amd.com core_params.core_ty); 172410234Syasuko.eckert@amd.com fFRAT->output_data.area *= core_params.num_hthreads; 172510234Syasuko.eckert@amd.com area.set_area(area.get_area() + fFRAT->area.get_area()); 172610234Syasuko.eckert@amd.com } 172710234Syasuko.eckert@amd.com 172810234Syasuko.eckert@amd.com //RRAT is always RAM based, does not have GCs, and is used only for 172910234Syasuko.eckert@amd.com //record latest non-speculative mapping 173010234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE)); 173110234Syasuko.eckert@amd.com size = data * core_params.archi_Regs_IRF_size * 173210234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS; 173310234Syasuko.eckert@amd.com 173410234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 173510234Syasuko.eckert@amd.com interface_ip.line_sz = data; 173610234Syasuko.eckert@amd.com interface_ip.assoc = RAM_BASED_RAT_ASSOC; 173710234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.retire_rat_nbanks; 173810234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 173910234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 174010234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 174110234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 174210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 174310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 174410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 174510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 174610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.retire_rat_rw_ports; 174710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.commitW; 174810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.commitW; 174910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 175010234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 175110234Syasuko.eckert@amd.com interface_ip.is_cache = false; 175210234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 175310234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 175410234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 175510234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 175610234Syasuko.eckert@amd.com iRRAT = new ArrayST(xml_data, &interface_ip, "Int Retire RAT", 175710234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 175810234Syasuko.eckert@amd.com core_params.core_ty); 175910234Syasuko.eckert@amd.com iRRAT->output_data.area *= core_params.num_hthreads; 176010234Syasuko.eckert@amd.com area.set_area(area.get_area() + iRRAT->area.get_area()); 176110234Syasuko.eckert@amd.com 176210234Syasuko.eckert@amd.com //RRAT for FP 176310234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE)); 176410234Syasuko.eckert@amd.com size = data * core_params.archi_Regs_FRF_size * 176510234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS; 176610234Syasuko.eckert@amd.com 176710234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 176810234Syasuko.eckert@amd.com interface_ip.line_sz = data; 176910234Syasuko.eckert@amd.com interface_ip.assoc = RAM_BASED_RAT_ASSOC; 177010234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.retire_rat_nbanks; 177110234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 177210234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 177310234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 177410234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 177510234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 177610234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 177710234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 177810234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 177910234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.retire_rat_rw_ports; 178010234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.fp_decodeW; 178110234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.fp_decodeW; 178210234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 178310234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 178410234Syasuko.eckert@amd.com interface_ip.is_cache = false; 178510234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 178610234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 178710234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 178810234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 178910234Syasuko.eckert@amd.com fRRAT = new ArrayST(xml_data, &interface_ip, "FP Retire RAT", 179010234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 179110234Syasuko.eckert@amd.com core_params.core_ty); 179210234Syasuko.eckert@amd.com fRRAT->output_data.area *= core_params.num_hthreads; 179310234Syasuko.eckert@amd.com area.set_area(area.get_area() + fRRAT->area.get_area()); 179410234Syasuko.eckert@amd.com 179510234Syasuko.eckert@amd.com //Freelist of renaming unit always RAM based 179610234Syasuko.eckert@amd.com //Recycle happens at two places: 1)when DCL check there are WAW, the Phyregisters/ROB directly recycles into freelist 179710234Syasuko.eckert@amd.com // 2)When instruction commits the Phyregisters/ROB needed to be recycled. 179810234Syasuko.eckert@amd.com //therefore num_wr port = decode-1(-1 means at least one phy reg will be used for the current renaming group) + commit width 179910234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE)); 180010234Syasuko.eckert@amd.com size = data * core_params.num_ifreelist_entries; 180110234Syasuko.eckert@amd.com 180210234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 180310234Syasuko.eckert@amd.com interface_ip.line_sz = data; 180410234Syasuko.eckert@amd.com interface_ip.assoc = FREELIST_ASSOC; 180510234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.freelist_nbanks; 180610234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 180710234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 180810234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 180910234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 181010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 181110234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 181210234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 181310234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 181410234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.freelist_rw_ports; 181510234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.decodeW; 181610234Syasuko.eckert@amd.com interface_ip.num_wr_ports = 181710234Syasuko.eckert@amd.com core_params.decodeW - 1 + core_params.commitW; 181810234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 181910234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 182010234Syasuko.eckert@amd.com interface_ip.is_cache = false; 182110234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 182210234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 182310234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 182410234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 182510234Syasuko.eckert@amd.com ifreeL = new ArrayST(xml_data, &interface_ip, "Integer Free List", 182610234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 182710234Syasuko.eckert@amd.com core_params.core_ty); 182810234Syasuko.eckert@amd.com ifreeL->output_data.area *= core_params.num_hthreads; 182910234Syasuko.eckert@amd.com area.set_area(area.get_area() + ifreeL->area.get_area()); 183010234Syasuko.eckert@amd.com 183110234Syasuko.eckert@amd.com //freelist for FP 183210234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE)); 183310234Syasuko.eckert@amd.com size = data * core_params.num_ffreelist_entries; 183410234Syasuko.eckert@amd.com 183510234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 183610234Syasuko.eckert@amd.com interface_ip.line_sz = data; 183710234Syasuko.eckert@amd.com interface_ip.assoc = FREELIST_ASSOC; 183810234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.freelist_nbanks; 183910234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 184010234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 184110234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 184210234Syasuko.eckert@amd.com interface_ip.access_mode = Sequential; 184310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 184410234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 184510234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 184610234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 184710234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.freelist_rw_ports; 184810234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.fp_decodeW; 184910234Syasuko.eckert@amd.com interface_ip.num_wr_ports = 185010234Syasuko.eckert@amd.com core_params.fp_decodeW - 1 + core_params.commitW; 185110234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 185210234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 185310234Syasuko.eckert@amd.com interface_ip.is_cache = false; 185410234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 185510234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 185610234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 185710234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 185810234Syasuko.eckert@amd.com ffreeL = new ArrayST(xml_data, &interface_ip, "FP Free List", 185910234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 186010234Syasuko.eckert@amd.com core_params.core_ty); 186110234Syasuko.eckert@amd.com ffreeL->output_data.area *= core_params.num_hthreads; 186210234Syasuko.eckert@amd.com area.set_area(area.get_area() + ffreeL->area.get_area()); 186310234Syasuko.eckert@amd.com 186410234Syasuko.eckert@amd.com } else if (core_params.scheu_ty == ReservationStation) { 186510234Syasuko.eckert@amd.com if (core_params.rm_ty == RAMbased) { 186610234Syasuko.eckert@amd.com tag = core_params.phy_ireg_width; 186710234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_ireg_width * 186810234Syasuko.eckert@amd.com (1 + core_params.globalCheckpoint) / 186910234Syasuko.eckert@amd.com BITS_PER_BYTE)); 187010234Syasuko.eckert@amd.com out_w = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE)); 187110234Syasuko.eckert@amd.com size = data * core_params.archi_Regs_IRF_size; 187210234Syasuko.eckert@amd.com 187310234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 187410234Syasuko.eckert@amd.com interface_ip.line_sz = data; 187510234Syasuko.eckert@amd.com interface_ip.assoc = RS_RAT_ASSOC; 187610234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 187710234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 187810234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 187910234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 188010234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 188110234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 188210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 188310234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 188410234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 188510234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 188610234Syasuko.eckert@amd.com interface_ip.num_rd_ports = 188710234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.decodeW; 188810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.decodeW; 188910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 189010234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.commitW; 189110234Syasuko.eckert@amd.com interface_ip.is_cache = true; 189210234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 189310234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 189410234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 189510234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 189610234Syasuko.eckert@amd.com iFRAT = new ArrayST(xml_data, &interface_ip, "Int Front RAT", 189710234Syasuko.eckert@amd.com Core_device, clockRate, 189810234Syasuko.eckert@amd.com core_params.opt_local, 189910234Syasuko.eckert@amd.com core_params.core_ty); 190010234Syasuko.eckert@amd.com iFRAT->local_result.adjust_area(); 190110234Syasuko.eckert@amd.com iFRAT->output_data.area *= core_params.num_hthreads; 190210234Syasuko.eckert@amd.com area.set_area(area.get_area() + iFRAT->area.get_area()); 190310234Syasuko.eckert@amd.com 190410234Syasuko.eckert@amd.com //FP 190510234Syasuko.eckert@amd.com tag = core_params.phy_freg_width; 190610234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_freg_width * 190710234Syasuko.eckert@amd.com (1 + core_params.globalCheckpoint) / 190810234Syasuko.eckert@amd.com BITS_PER_BYTE)); 190910234Syasuko.eckert@amd.com out_w = int(ceil(core_params.phy_freg_width / BITS_PER_BYTE)); 191010234Syasuko.eckert@amd.com size = data * core_params.archi_Regs_FRF_size; 191110234Syasuko.eckert@amd.com 191210234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 191310234Syasuko.eckert@amd.com interface_ip.line_sz = data; 191410234Syasuko.eckert@amd.com interface_ip.assoc = RS_RAT_ASSOC; 191510234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 191610234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 191710234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 191810234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 191910234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 192010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 192110234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 192210234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 192310234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 192410234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 192510234Syasuko.eckert@amd.com interface_ip.num_rd_ports = 192610234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.fp_decodeW; 192710234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.fp_decodeW; 192810234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 192910234Syasuko.eckert@amd.com interface_ip.num_search_ports = core_params.fp_issueW; 193010234Syasuko.eckert@amd.com interface_ip.is_cache = true; 193110234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 193210234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 193310234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 193410234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 193510234Syasuko.eckert@amd.com fFRAT = new ArrayST(xml_data, &interface_ip, "FP Front RAT", 193610234Syasuko.eckert@amd.com Core_device, clockRate, 193710234Syasuko.eckert@amd.com core_params.opt_local, 193810234Syasuko.eckert@amd.com core_params.core_ty); 193910234Syasuko.eckert@amd.com fFRAT->local_result.adjust_area(); 194010234Syasuko.eckert@amd.com fFRAT->output_data.area *= core_params.num_hthreads; 194110234Syasuko.eckert@amd.com area.set_area(area.get_area() + fFRAT->area.get_area()); 194210234Syasuko.eckert@amd.com 194310234Syasuko.eckert@amd.com } else if ((core_params.rm_ty == CAMbased)) { 194410234Syasuko.eckert@amd.com //FRAT 194510234Syasuko.eckert@amd.com //the address of CAM needed to be sent out 194610234Syasuko.eckert@amd.com tag = core_params.arch_ireg_width; 194710234Syasuko.eckert@amd.com data = int(ceil (core_params.arch_ireg_width + 194810234Syasuko.eckert@amd.com 1 * core_params.globalCheckpoint / 194910234Syasuko.eckert@amd.com BITS_PER_BYTE)); 195010234Syasuko.eckert@amd.com out_w = int(ceil (core_params.arch_ireg_width / 195110234Syasuko.eckert@amd.com BITS_PER_BYTE)); 195210234Syasuko.eckert@amd.com size = data * core_params.phy_Regs_IRF_size; 195310234Syasuko.eckert@amd.com 195410234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 195510234Syasuko.eckert@amd.com interface_ip.line_sz = data; 195610234Syasuko.eckert@amd.com interface_ip.assoc = CAM_ASSOC; 195710234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 195810234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 195910234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 196010234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 196110234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 196210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 196310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 196410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 196510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 196610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 196710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.decodeW; 196810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.decodeW; 196910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 197010234Syasuko.eckert@amd.com interface_ip.num_search_ports = 197110234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.decodeW; 197210234Syasuko.eckert@amd.com interface_ip.is_cache = true; 197310234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 197410234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 197510234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 197610234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 197710234Syasuko.eckert@amd.com iFRAT = new ArrayST(xml_data, &interface_ip, "Int Front RAT", 197810234Syasuko.eckert@amd.com Core_device, clockRate, 197910234Syasuko.eckert@amd.com core_params.opt_local, 198010234Syasuko.eckert@amd.com core_params.core_ty); 198110234Syasuko.eckert@amd.com iFRAT->output_data.area *= core_params.num_hthreads; 198210234Syasuko.eckert@amd.com area.set_area(area.get_area() + iFRAT->area.get_area()); 198310234Syasuko.eckert@amd.com 198410234Syasuko.eckert@amd.com //FRAT 198510234Syasuko.eckert@amd.com tag = core_params.arch_freg_width; 198610234Syasuko.eckert@amd.com //the address of CAM needed to be sent out 198710234Syasuko.eckert@amd.com data = int(ceil(core_params.arch_freg_width + 198810234Syasuko.eckert@amd.com 1 * core_params.globalCheckpoint / 198910234Syasuko.eckert@amd.com BITS_PER_BYTE)); 199010234Syasuko.eckert@amd.com out_w = int(ceil(core_params.arch_freg_width / BITS_PER_BYTE)); 199110234Syasuko.eckert@amd.com size = data * core_params.phy_Regs_FRF_size; 199210234Syasuko.eckert@amd.com 199310234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 199410234Syasuko.eckert@amd.com interface_ip.line_sz = data; 199510234Syasuko.eckert@amd.com interface_ip.assoc = CAM_ASSOC; 199610234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.front_rat_nbanks; 199710234Syasuko.eckert@amd.com interface_ip.out_w = out_w * BITS_PER_BYTE; 199810234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 199910234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 200010234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 200110234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 200210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 200310234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 200410234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 200510234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.front_rat_rw_ports; 200610234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.decodeW; 200710234Syasuko.eckert@amd.com interface_ip.num_wr_ports = core_params.fp_decodeW; 200810234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 200910234Syasuko.eckert@amd.com interface_ip.num_search_ports = 201010234Syasuko.eckert@amd.com NUM_SOURCE_OPERANDS * core_params.fp_decodeW; 201110234Syasuko.eckert@amd.com interface_ip.is_cache = true; 201210234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 201310234Syasuko.eckert@amd.com interface_ip.pure_ram = false; 201410234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 201510234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 201610234Syasuko.eckert@amd.com fFRAT = new ArrayST(xml_data, &interface_ip, "FP Front RAT", 201710234Syasuko.eckert@amd.com Core_device, clockRate, 201810234Syasuko.eckert@amd.com core_params.opt_local, 201910234Syasuko.eckert@amd.com core_params.core_ty); 202010234Syasuko.eckert@amd.com fFRAT->output_data.area *= core_params.num_hthreads; 202110234Syasuko.eckert@amd.com area.set_area(area.get_area() + fFRAT->area.get_area()); 202210234Syasuko.eckert@amd.com 202310234Syasuko.eckert@amd.com } 202410234Syasuko.eckert@amd.com //No RRAT for RS based OOO 202510234Syasuko.eckert@amd.com //Freelist of renaming unit of RS based OOO is unifed for both int and fp renaming unit since the ROB is unified 202610234Syasuko.eckert@amd.com data = int(ceil(core_params.phy_ireg_width / BITS_PER_BYTE)); 202710234Syasuko.eckert@amd.com size = data * core_params.num_ifreelist_entries; 202810234Syasuko.eckert@amd.com 202910234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 203010234Syasuko.eckert@amd.com interface_ip.line_sz = data; 203110234Syasuko.eckert@amd.com interface_ip.assoc = FREELIST_ASSOC; 203210234Syasuko.eckert@amd.com interface_ip.nbanks = core_params.freelist_nbanks; 203310234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 203410234Syasuko.eckert@amd.com interface_ip.specific_tag = NON_CAM_BASED_TAG_WIDTH > 0; 203510234Syasuko.eckert@amd.com interface_ip.tag_w = NON_CAM_BASED_TAG_WIDTH; 203610234Syasuko.eckert@amd.com interface_ip.access_mode = Fast; 203710234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 203810234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 203910234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 204010234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 204110234Syasuko.eckert@amd.com interface_ip.num_rw_ports = core_params.freelist_rw_ports; 204210234Syasuko.eckert@amd.com interface_ip.num_rd_ports = core_params.decodeW; 204310234Syasuko.eckert@amd.com interface_ip.num_wr_ports = 204410234Syasuko.eckert@amd.com core_params.decodeW - 1 + core_params.commitW; 204510234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = 0; 204610234Syasuko.eckert@amd.com interface_ip.num_search_ports = 0; 204710234Syasuko.eckert@amd.com interface_ip.is_cache = false; 204810234Syasuko.eckert@amd.com interface_ip.pure_cam = false; 204910234Syasuko.eckert@amd.com interface_ip.pure_ram = true; 205010234Syasuko.eckert@amd.com interface_ip.throughput = 1.0 / clockRate; 205110234Syasuko.eckert@amd.com interface_ip.latency = 1.0 / clockRate; 205210234Syasuko.eckert@amd.com ifreeL = new ArrayST(xml_data, &interface_ip, "Unified Free List", 205310234Syasuko.eckert@amd.com Core_device, clockRate, core_params.opt_local, 205410234Syasuko.eckert@amd.com core_params.core_ty); 205510234Syasuko.eckert@amd.com ifreeL->output_data.area *= core_params.num_hthreads; 205610234Syasuko.eckert@amd.com area.set_area(area.get_area() + ifreeL->area.get_area()); 205710152Satgutier@umich.edu } 205810152Satgutier@umich.edu 205910234Syasuko.eckert@amd.com } 206010234Syasuko.eckert@amd.com idcl = 206110234Syasuko.eckert@amd.com new dep_resource_conflict_check(xml_data, 206210234Syasuko.eckert@amd.com "Instruction Dependency Check?", 206310234Syasuko.eckert@amd.com &interface_ip, core_params, 206410234Syasuko.eckert@amd.com core_params.phy_ireg_width, 206510234Syasuko.eckert@amd.com clockRate); 206610234Syasuko.eckert@amd.com fdcl = 206710234Syasuko.eckert@amd.com new dep_resource_conflict_check(xml_data, 206810234Syasuko.eckert@amd.com "FP Dependency Check?", &interface_ip, 206910234Syasuko.eckert@amd.com core_params, 207010234Syasuko.eckert@amd.com core_params.phy_freg_width, clockRate); 207110234Syasuko.eckert@amd.com} 207210234Syasuko.eckert@amd.com 207310234Syasuko.eckert@amd.comCore::Core(XMLNode* _xml_data, int _ithCore, InputParameter* interface_ip_) 207410234Syasuko.eckert@amd.com : McPATComponent(_xml_data), ifu(NULL), lsu(NULL), mmu(NULL), 207510234Syasuko.eckert@amd.com exu(NULL), rnu(NULL), corepipe (NULL), undiffCore(NULL), l2cache (NULL), 207610234Syasuko.eckert@amd.com ithCore(_ithCore), interface_ip(*interface_ip_) { 207710234Syasuko.eckert@amd.com 207810234Syasuko.eckert@amd.com ostringstream os; 207910234Syasuko.eckert@amd.com os << ithCore; 208010234Syasuko.eckert@amd.com name = "Core " + os.str(); 208110234Syasuko.eckert@amd.com 208210234Syasuko.eckert@amd.com int i = 0; 208310234Syasuko.eckert@amd.com XMLNode* childXML; 208410234Syasuko.eckert@amd.com for (i = 0; i < xml_data->nChildNode("component"); i++) { 208510234Syasuko.eckert@amd.com childXML = xml_data->getChildNodePtr("component", &i); 208610234Syasuko.eckert@amd.com XMLCSTR type = childXML->getAttribute("type"); 208710234Syasuko.eckert@amd.com if (!type) 208810234Syasuko.eckert@amd.com warnMissingComponentType(childXML->getAttribute("id")); 208910234Syasuko.eckert@amd.com 209010234Syasuko.eckert@amd.com STRCMP(type, "CacheUnit") { 209110234Syasuko.eckert@amd.com XMLCSTR comp_name = childXML->getAttribute("id"); 209210234Syasuko.eckert@amd.com if (!comp_name) 209310234Syasuko.eckert@amd.com continue; 209410234Syasuko.eckert@amd.com 209510234Syasuko.eckert@amd.com STRCMP(comp_name, "system.L20") { 209610234Syasuko.eckert@amd.com l2cache = new CacheUnit(childXML, &interface_ip); 209710234Syasuko.eckert@amd.com children.push_back(l2cache); 209810234Syasuko.eckert@amd.com } 209910152Satgutier@umich.edu } 210010234Syasuko.eckert@amd.com } 210110234Syasuko.eckert@amd.com 210210234Syasuko.eckert@amd.com set_core_param(); 210310234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 210410234Syasuko.eckert@amd.com 210510234Syasuko.eckert@amd.com ifu = new InstFetchU(xml_data, &interface_ip, core_params, 210610234Syasuko.eckert@amd.com core_stats); 210710234Syasuko.eckert@amd.com children.push_back(ifu); 210810234Syasuko.eckert@amd.com lsu = new LoadStoreU(xml_data, &interface_ip, core_params, 210910234Syasuko.eckert@amd.com core_stats); 211010234Syasuko.eckert@amd.com children.push_back(lsu); 211110234Syasuko.eckert@amd.com mmu = new MemManU(xml_data, &interface_ip, core_params, 211210234Syasuko.eckert@amd.com core_stats); 211310234Syasuko.eckert@amd.com children.push_back(mmu); 211410234Syasuko.eckert@amd.com exu = new EXECU(xml_data, &interface_ip, lsu->lsq_height, 211510234Syasuko.eckert@amd.com core_params, core_stats); 211610234Syasuko.eckert@amd.com children.push_back(exu); 211710234Syasuko.eckert@amd.com undiffCore = new UndiffCore(xml_data, &interface_ip, core_params); 211810234Syasuko.eckert@amd.com children.push_back(undiffCore); 211910234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 212010234Syasuko.eckert@amd.com rnu = new RENAMINGU(xml_data, &interface_ip, core_params, 212110234Syasuko.eckert@amd.com core_stats); 212210234Syasuko.eckert@amd.com children.push_back(rnu); 212310234Syasuko.eckert@amd.com } 212410234Syasuko.eckert@amd.com corepipe = new Pipeline(xml_data, &interface_ip, core_params); 212510234Syasuko.eckert@amd.com children.push_back(corepipe); 212610234Syasuko.eckert@amd.com 212710234Syasuko.eckert@amd.com double pipeline_area_per_unit; 212810234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 212910234Syasuko.eckert@amd.com pipeline_area_per_unit = (corepipe->area.get_area() * 213010234Syasuko.eckert@amd.com core_params.num_pipelines) / 5.0; 213110234Syasuko.eckert@amd.com if (rnu->exist) { 213210234Syasuko.eckert@amd.com rnu->area.set_area(rnu->area.get_area() + pipeline_area_per_unit); 213310152Satgutier@umich.edu } 213410234Syasuko.eckert@amd.com } else { 213510234Syasuko.eckert@amd.com pipeline_area_per_unit = (corepipe->area.get_area() * 213610234Syasuko.eckert@amd.com core_params.num_pipelines) / 4.0; 213710234Syasuko.eckert@amd.com } 213810234Syasuko.eckert@amd.com 213910234Syasuko.eckert@amd.com // Move all of this to computeArea 214010234Syasuko.eckert@amd.com //area.set_area(area.get_area()+ corepipe->area.get_area()); 214110234Syasuko.eckert@amd.com if (ifu->exist) { 214210234Syasuko.eckert@amd.com ifu->area.set_area(ifu->area.get_area() + pipeline_area_per_unit); 214310234Syasuko.eckert@amd.com area.set_area(area.get_area() + ifu->area.get_area()); 214410234Syasuko.eckert@amd.com } 214510234Syasuko.eckert@amd.com if (lsu->exist) { 214610234Syasuko.eckert@amd.com lsu->area.set_area(lsu->area.get_area() + pipeline_area_per_unit); 214710234Syasuko.eckert@amd.com area.set_area(area.get_area() + lsu->area.get_area()); 214810234Syasuko.eckert@amd.com } 214910234Syasuko.eckert@amd.com if (exu->exist) { 215010234Syasuko.eckert@amd.com exu->area.set_area(exu->area.get_area() + pipeline_area_per_unit); 215110234Syasuko.eckert@amd.com area.set_area(area.get_area() + exu->area.get_area()); 215210234Syasuko.eckert@amd.com } 215310234Syasuko.eckert@amd.com if (mmu->exist) { 215410234Syasuko.eckert@amd.com mmu->area.set_area(mmu->area.get_area() + pipeline_area_per_unit); 215510234Syasuko.eckert@amd.com area.set_area(area.get_area() + mmu->area.get_area()); 215610234Syasuko.eckert@amd.com } 215710234Syasuko.eckert@amd.com 215810234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 215910234Syasuko.eckert@amd.com if (rnu->exist) { 216010234Syasuko.eckert@amd.com 216110234Syasuko.eckert@amd.com area.set_area(area.get_area() + rnu->area.get_area()); 216210234Syasuko.eckert@amd.com } 216310234Syasuko.eckert@amd.com } 216410234Syasuko.eckert@amd.com 216510234Syasuko.eckert@amd.com if (undiffCore->exist) { 216610234Syasuko.eckert@amd.com area.set_area(area.get_area() + undiffCore->area.get_area()); 216710234Syasuko.eckert@amd.com } 216810234Syasuko.eckert@amd.com 216910234Syasuko.eckert@amd.com if (l2cache) { 217010234Syasuko.eckert@amd.com area.set_area(area.get_area() + l2cache->area.get_area()); 217110234Syasuko.eckert@amd.com } 217210152Satgutier@umich.edu} 217310152Satgutier@umich.edu 217410152Satgutier@umich.edu 217510234Syasuko.eckert@amd.comvoid BranchPredictor::computeEnergy() { 217610234Syasuko.eckert@amd.com if (!exist) return; 217710234Syasuko.eckert@amd.com 217810234Syasuko.eckert@amd.com // ASSUMPTION: All instructions access the branch predictors at Fetch and 217910234Syasuko.eckert@amd.com // only branch instrucions update the predictors regardless 218010234Syasuko.eckert@amd.com // of the correctness of the prediction. 218110234Syasuko.eckert@amd.com double tdp_read_accesses = 218210234Syasuko.eckert@amd.com core_params.predictionW * core_stats.BR_duty_cycle; 218310234Syasuko.eckert@amd.com globalBPT->tdp_stats.reset(); 218410234Syasuko.eckert@amd.com globalBPT->tdp_stats.readAc.access = tdp_read_accesses; 218510234Syasuko.eckert@amd.com globalBPT->tdp_stats.writeAc.access = 0; 218610234Syasuko.eckert@amd.com globalBPT->rtp_stats.reset(); 218710234Syasuko.eckert@amd.com globalBPT->rtp_stats.readAc.access = core_stats.total_instructions; 218810234Syasuko.eckert@amd.com globalBPT->rtp_stats.writeAc.access = core_stats.branch_instructions; 218910234Syasuko.eckert@amd.com globalBPT->power_t.reset(); 219010234Syasuko.eckert@amd.com globalBPT->power_t.readOp.dynamic += 219110234Syasuko.eckert@amd.com globalBPT->local_result.power.readOp.dynamic * 219210234Syasuko.eckert@amd.com globalBPT->tdp_stats.readAc.access + 219310234Syasuko.eckert@amd.com globalBPT->local_result.power.writeOp.dynamic * 219410234Syasuko.eckert@amd.com globalBPT->tdp_stats.writeAc.access; 219510234Syasuko.eckert@amd.com globalBPT->power_t = globalBPT->power_t + 219610234Syasuko.eckert@amd.com globalBPT->local_result.power * pppm_lkg; 219710234Syasuko.eckert@amd.com globalBPT->rt_power.reset(); 219810234Syasuko.eckert@amd.com globalBPT->rt_power.readOp.dynamic += 219910234Syasuko.eckert@amd.com globalBPT->local_result.power.readOp.dynamic * 220010234Syasuko.eckert@amd.com globalBPT->rtp_stats.readAc.access + 220110234Syasuko.eckert@amd.com globalBPT->local_result.power.writeOp.dynamic * 220210234Syasuko.eckert@amd.com globalBPT->rtp_stats.writeAc.access; 220310234Syasuko.eckert@amd.com 220410234Syasuko.eckert@amd.com L1_localBPT->tdp_stats.reset(); 220510234Syasuko.eckert@amd.com L1_localBPT->tdp_stats.readAc.access = tdp_read_accesses; 220610234Syasuko.eckert@amd.com L1_localBPT->tdp_stats.writeAc.access = 0; 220710234Syasuko.eckert@amd.com L1_localBPT->rtp_stats.reset(); 220810234Syasuko.eckert@amd.com L1_localBPT->rtp_stats.readAc.access = core_stats.total_instructions; 220910234Syasuko.eckert@amd.com L1_localBPT->rtp_stats.writeAc.access = core_stats.branch_instructions; 221010234Syasuko.eckert@amd.com L1_localBPT->power_t.reset(); 221110234Syasuko.eckert@amd.com L1_localBPT->power_t.readOp.dynamic += 221210234Syasuko.eckert@amd.com L1_localBPT->local_result.power.readOp.dynamic * 221310234Syasuko.eckert@amd.com L1_localBPT->tdp_stats.readAc.access + 221410234Syasuko.eckert@amd.com L1_localBPT->local_result.power.writeOp.dynamic * 221510234Syasuko.eckert@amd.com L1_localBPT->tdp_stats.writeAc.access; 221610234Syasuko.eckert@amd.com L1_localBPT->power_t = L1_localBPT->power_t + 221710234Syasuko.eckert@amd.com L1_localBPT->local_result.power * pppm_lkg; 221810234Syasuko.eckert@amd.com L1_localBPT->rt_power.reset(); 221910234Syasuko.eckert@amd.com L1_localBPT->rt_power.readOp.dynamic += 222010234Syasuko.eckert@amd.com L1_localBPT->local_result.power.readOp.dynamic * 222110234Syasuko.eckert@amd.com L1_localBPT->rtp_stats.readAc.access + 222210234Syasuko.eckert@amd.com L1_localBPT->local_result.power.writeOp.dynamic * 222310234Syasuko.eckert@amd.com L1_localBPT->rtp_stats.writeAc.access; 222410234Syasuko.eckert@amd.com 222510234Syasuko.eckert@amd.com L2_localBPT->tdp_stats.reset(); 222610234Syasuko.eckert@amd.com L2_localBPT->tdp_stats.readAc.access = tdp_read_accesses; 222710234Syasuko.eckert@amd.com L2_localBPT->tdp_stats.writeAc.access = 0; 222810234Syasuko.eckert@amd.com L2_localBPT->rtp_stats.reset(); 222910234Syasuko.eckert@amd.com L2_localBPT->rtp_stats.readAc.access = core_stats.branch_instructions; 223010234Syasuko.eckert@amd.com L2_localBPT->rtp_stats.writeAc.access = core_stats.branch_instructions; 223110234Syasuko.eckert@amd.com L2_localBPT->power_t.reset(); 223210234Syasuko.eckert@amd.com L2_localBPT->power_t.readOp.dynamic += 223310234Syasuko.eckert@amd.com L2_localBPT->local_result.power.readOp.dynamic * 223410234Syasuko.eckert@amd.com L2_localBPT->tdp_stats.readAc.access + 223510234Syasuko.eckert@amd.com L2_localBPT->local_result.power.writeOp.dynamic * 223610234Syasuko.eckert@amd.com L2_localBPT->tdp_stats.writeAc.access; 223710234Syasuko.eckert@amd.com L2_localBPT->power_t = L2_localBPT->power_t + 223810234Syasuko.eckert@amd.com L2_localBPT->local_result.power * pppm_lkg; 223910234Syasuko.eckert@amd.com L2_localBPT->rt_power.reset(); 224010234Syasuko.eckert@amd.com L2_localBPT->rt_power.readOp.dynamic += 224110234Syasuko.eckert@amd.com L2_localBPT->local_result.power.readOp.dynamic * 224210234Syasuko.eckert@amd.com L2_localBPT->rtp_stats.readAc.access + 224310234Syasuko.eckert@amd.com L2_localBPT->local_result.power.writeOp.dynamic * 224410234Syasuko.eckert@amd.com L2_localBPT->rtp_stats.writeAc.access; 224510234Syasuko.eckert@amd.com 224610234Syasuko.eckert@amd.com chooser->tdp_stats.reset(); 224710234Syasuko.eckert@amd.com chooser->tdp_stats.readAc.access = tdp_read_accesses; 224810234Syasuko.eckert@amd.com chooser->tdp_stats.writeAc.access = 0; 224910234Syasuko.eckert@amd.com chooser->rtp_stats.reset(); 225010234Syasuko.eckert@amd.com chooser->rtp_stats.readAc.access = core_stats.total_instructions; 225110234Syasuko.eckert@amd.com chooser->rtp_stats.writeAc.access = core_stats.branch_instructions; 225210234Syasuko.eckert@amd.com chooser->power_t.reset(); 225310234Syasuko.eckert@amd.com chooser->power_t.readOp.dynamic += 225410234Syasuko.eckert@amd.com chooser->local_result.power.readOp.dynamic * 225510234Syasuko.eckert@amd.com chooser->tdp_stats.readAc.access + 225610234Syasuko.eckert@amd.com chooser->local_result.power.writeOp.dynamic * 225710234Syasuko.eckert@amd.com chooser->tdp_stats.writeAc.access; 225810234Syasuko.eckert@amd.com chooser->power_t = 225910234Syasuko.eckert@amd.com chooser->power_t + chooser->local_result.power * pppm_lkg; 226010234Syasuko.eckert@amd.com chooser->rt_power.reset(); 226110234Syasuko.eckert@amd.com chooser->rt_power.readOp.dynamic += 226210234Syasuko.eckert@amd.com chooser->local_result.power.readOp.dynamic * 226310234Syasuko.eckert@amd.com chooser->rtp_stats.readAc.access + 226410234Syasuko.eckert@amd.com chooser->local_result.power.writeOp.dynamic * 226510234Syasuko.eckert@amd.com chooser->rtp_stats.writeAc.access; 226610234Syasuko.eckert@amd.com 226710234Syasuko.eckert@amd.com RAS->tdp_stats.reset(); 226810234Syasuko.eckert@amd.com RAS->tdp_stats.readAc.access = tdp_read_accesses; 226910234Syasuko.eckert@amd.com RAS->tdp_stats.writeAc.access = 0; 227010234Syasuko.eckert@amd.com RAS->rtp_stats.reset(); 227110234Syasuko.eckert@amd.com RAS->rtp_stats.readAc.access = core_stats.function_calls; 227210234Syasuko.eckert@amd.com RAS->rtp_stats.writeAc.access = core_stats.function_calls; 227310234Syasuko.eckert@amd.com RAS->power_t.reset(); 227410234Syasuko.eckert@amd.com RAS->power_t.readOp.dynamic += 227510234Syasuko.eckert@amd.com RAS->local_result.power.readOp.dynamic * RAS->tdp_stats.readAc.access + 227610234Syasuko.eckert@amd.com RAS->local_result.power.writeOp.dynamic * 227710234Syasuko.eckert@amd.com RAS->tdp_stats.writeAc.access; 227810234Syasuko.eckert@amd.com RAS->power_t = RAS->power_t + RAS->local_result.power * 227910234Syasuko.eckert@amd.com core_params.pppm_lkg_multhread; 228010234Syasuko.eckert@amd.com RAS->rt_power.reset(); 228110234Syasuko.eckert@amd.com RAS->rt_power.readOp.dynamic += RAS->local_result.power.readOp.dynamic * 228210234Syasuko.eckert@amd.com RAS->rtp_stats.readAc.access + 228310234Syasuko.eckert@amd.com RAS->local_result.power.writeOp.dynamic * 228410234Syasuko.eckert@amd.com RAS->rtp_stats.writeAc.access; 228510234Syasuko.eckert@amd.com 228610234Syasuko.eckert@amd.com output_data.reset(); 228710234Syasuko.eckert@amd.com if (globalBPT) { 228810234Syasuko.eckert@amd.com globalBPT->output_data.peak_dynamic_power = 228910234Syasuko.eckert@amd.com globalBPT->power_t.readOp.dynamic * clockRate; 229010234Syasuko.eckert@amd.com globalBPT->output_data.runtime_dynamic_energy = 229110234Syasuko.eckert@amd.com globalBPT->rt_power.readOp.dynamic; 229210234Syasuko.eckert@amd.com output_data += globalBPT->output_data; 229310234Syasuko.eckert@amd.com } 229410234Syasuko.eckert@amd.com if (L1_localBPT) { 229510234Syasuko.eckert@amd.com L1_localBPT->output_data.peak_dynamic_power = 229610234Syasuko.eckert@amd.com L1_localBPT->power_t.readOp.dynamic * clockRate; 229710234Syasuko.eckert@amd.com L1_localBPT->output_data.runtime_dynamic_energy = 229810234Syasuko.eckert@amd.com L1_localBPT->rt_power.readOp.dynamic; 229910234Syasuko.eckert@amd.com output_data += L1_localBPT->output_data; 230010234Syasuko.eckert@amd.com } 230110234Syasuko.eckert@amd.com if (L2_localBPT) { 230210234Syasuko.eckert@amd.com L2_localBPT->output_data.peak_dynamic_power = 230310234Syasuko.eckert@amd.com L2_localBPT->power_t.readOp.dynamic * clockRate; 230410234Syasuko.eckert@amd.com L2_localBPT->output_data.runtime_dynamic_energy = 230510234Syasuko.eckert@amd.com L2_localBPT->rt_power.readOp.dynamic; 230610234Syasuko.eckert@amd.com output_data += L2_localBPT->output_data; 230710234Syasuko.eckert@amd.com } 230810234Syasuko.eckert@amd.com if (chooser) { 230910234Syasuko.eckert@amd.com chooser->output_data.peak_dynamic_power = 231010234Syasuko.eckert@amd.com chooser->power_t.readOp.dynamic * clockRate; 231110234Syasuko.eckert@amd.com chooser->output_data.runtime_dynamic_energy = 231210234Syasuko.eckert@amd.com chooser->rt_power.readOp.dynamic; 231310234Syasuko.eckert@amd.com output_data += chooser->output_data; 231410234Syasuko.eckert@amd.com } 231510234Syasuko.eckert@amd.com if (RAS) { 231610234Syasuko.eckert@amd.com RAS->output_data.peak_dynamic_power = 231710234Syasuko.eckert@amd.com RAS->power_t.readOp.dynamic * clockRate; 231810234Syasuko.eckert@amd.com RAS->output_data.subthreshold_leakage_power = 231910234Syasuko.eckert@amd.com RAS->power_t.readOp.leakage * core_params.num_hthreads; 232010234Syasuko.eckert@amd.com RAS->output_data.gate_leakage_power = 232110234Syasuko.eckert@amd.com RAS->power_t.readOp.gate_leakage * core_params.num_hthreads; 232210234Syasuko.eckert@amd.com RAS->output_data.runtime_dynamic_energy = RAS->rt_power.readOp.dynamic; 232310234Syasuko.eckert@amd.com output_data += RAS->output_data; 232410234Syasuko.eckert@amd.com } 232510234Syasuko.eckert@amd.com} 232610234Syasuko.eckert@amd.com 232710234Syasuko.eckert@amd.comvoid BranchPredictor::displayData(uint32_t indent, int plevel) { 232810234Syasuko.eckert@amd.com if (!exist) return; 232910234Syasuko.eckert@amd.com 233010234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 233110234Syasuko.eckert@amd.com 233210234Syasuko.eckert@amd.com globalBPT->displayData(indent + 4, plevel); 233310234Syasuko.eckert@amd.com L1_localBPT->displayData(indent + 4, plevel); 233410234Syasuko.eckert@amd.com L2_localBPT->displayData(indent + 4, plevel); 233510234Syasuko.eckert@amd.com chooser->displayData(indent + 4, plevel); 233610234Syasuko.eckert@amd.com RAS->displayData(indent + 4, plevel); 233710234Syasuko.eckert@amd.com} 233810234Syasuko.eckert@amd.com 233910234Syasuko.eckert@amd.comvoid InstFetchU::computeEnergy() { 234010234Syasuko.eckert@amd.com if (!exist) return; 234110234Syasuko.eckert@amd.com 234210234Syasuko.eckert@amd.com if (BPT) { 234310234Syasuko.eckert@amd.com BPT->computeEnergy(); 234410234Syasuko.eckert@amd.com } 234510234Syasuko.eckert@amd.com 234610234Syasuko.eckert@amd.com IB->tdp_stats.reset(); 234710234Syasuko.eckert@amd.com IB->tdp_stats.readAc.access = core_params.peak_issueW; 234810234Syasuko.eckert@amd.com IB->tdp_stats.writeAc.access = core_params.peak_issueW; 234910234Syasuko.eckert@amd.com IB->rtp_stats.reset(); 235010234Syasuko.eckert@amd.com IB->rtp_stats.readAc.access = core_stats.total_instructions; 235110234Syasuko.eckert@amd.com IB->rtp_stats.writeAc.access = core_stats.total_instructions; 235210234Syasuko.eckert@amd.com IB->power_t.reset(); 235310234Syasuko.eckert@amd.com IB->power_t.readOp.dynamic += IB->local_result.power.readOp.dynamic * 235410234Syasuko.eckert@amd.com IB->tdp_stats.readAc.access + 235510234Syasuko.eckert@amd.com IB->local_result.power.writeOp.dynamic * IB->tdp_stats.writeAc.access; 235610234Syasuko.eckert@amd.com IB->power_t = IB->power_t + IB->local_result.power * pppm_lkg; 235710234Syasuko.eckert@amd.com IB->rt_power.reset(); 235810234Syasuko.eckert@amd.com IB->rt_power.readOp.dynamic += IB->local_result.power.readOp.dynamic * 235910234Syasuko.eckert@amd.com IB->rtp_stats.readAc.access + 236010234Syasuko.eckert@amd.com IB->local_result.power.writeOp.dynamic * IB->rtp_stats.writeAc.access; 236110234Syasuko.eckert@amd.com 236210234Syasuko.eckert@amd.com if (core_params.predictionW > 0) { 236310234Syasuko.eckert@amd.com BTB->tdp_stats.reset(); 236410234Syasuko.eckert@amd.com BTB->tdp_stats.readAc.access = core_params.predictionW; 236510234Syasuko.eckert@amd.com BTB->tdp_stats.writeAc.access = 0; 236610234Syasuko.eckert@amd.com BTB->rtp_stats.reset(); 236710234Syasuko.eckert@amd.com BTB->rtp_stats.readAc.access = inst_fetch_stats.btb_read_accesses; 236810234Syasuko.eckert@amd.com BTB->rtp_stats.writeAc.access = inst_fetch_stats.btb_write_accesses; 236910234Syasuko.eckert@amd.com BTB->power_t.reset(); 237010234Syasuko.eckert@amd.com BTB->power_t.readOp.dynamic += BTB->local_result.power.readOp.dynamic * 237110234Syasuko.eckert@amd.com BTB->tdp_stats.readAc.access + 237210234Syasuko.eckert@amd.com BTB->local_result.power.writeOp.dynamic * 237310234Syasuko.eckert@amd.com BTB->tdp_stats.writeAc.access; 237410234Syasuko.eckert@amd.com BTB->rt_power.reset(); 237510234Syasuko.eckert@amd.com BTB->rt_power.readOp.dynamic += 237610234Syasuko.eckert@amd.com BTB->local_result.power.readOp.dynamic * 237710234Syasuko.eckert@amd.com BTB->rtp_stats.readAc.access + 237810234Syasuko.eckert@amd.com BTB->local_result.power.writeOp.dynamic * 237910234Syasuko.eckert@amd.com BTB->rtp_stats.writeAc.access; 238010234Syasuko.eckert@amd.com } 238110234Syasuko.eckert@amd.com 238210234Syasuko.eckert@amd.com ID_inst->tdp_stats.reset(); 238310234Syasuko.eckert@amd.com ID_inst->tdp_stats.readAc.access = core_params.decodeW; 238410234Syasuko.eckert@amd.com ID_inst->power_t.reset(); 238510234Syasuko.eckert@amd.com ID_inst->power_t = ID_misc->power; 238610234Syasuko.eckert@amd.com ID_inst->power_t.readOp.dynamic = ID_inst->power.readOp.dynamic * 238710234Syasuko.eckert@amd.com ID_inst->tdp_stats.readAc.access; 238810234Syasuko.eckert@amd.com ID_inst->rtp_stats.reset(); 238910234Syasuko.eckert@amd.com ID_inst->rtp_stats.readAc.access = core_stats.total_instructions; 239010234Syasuko.eckert@amd.com ID_inst->rt_power.reset(); 239110234Syasuko.eckert@amd.com ID_inst->rt_power.readOp.dynamic = ID_inst->power.readOp.dynamic * 239210234Syasuko.eckert@amd.com ID_inst->rtp_stats.readAc.access; 239310234Syasuko.eckert@amd.com 239410234Syasuko.eckert@amd.com ID_operand->tdp_stats.reset(); 239510234Syasuko.eckert@amd.com ID_operand->tdp_stats.readAc.access = core_params.decodeW; 239610234Syasuko.eckert@amd.com ID_operand->power_t.reset(); 239710234Syasuko.eckert@amd.com ID_operand->power_t = ID_misc->power; 239810234Syasuko.eckert@amd.com ID_operand->power_t.readOp.dynamic = ID_operand->power.readOp.dynamic * 239910234Syasuko.eckert@amd.com ID_operand->tdp_stats.readAc.access; 240010234Syasuko.eckert@amd.com ID_operand->rtp_stats.reset(); 240110234Syasuko.eckert@amd.com ID_operand->rtp_stats.readAc.access = core_stats.total_instructions; 240210234Syasuko.eckert@amd.com ID_operand->rt_power.reset(); 240310234Syasuko.eckert@amd.com ID_operand->rt_power.readOp.dynamic = ID_operand->power.readOp.dynamic * 240410234Syasuko.eckert@amd.com ID_operand->rtp_stats.readAc.access; 240510234Syasuko.eckert@amd.com 240610234Syasuko.eckert@amd.com ID_misc->tdp_stats.reset(); 240710234Syasuko.eckert@amd.com ID_misc->tdp_stats.readAc.access = core_params.decodeW; 240810234Syasuko.eckert@amd.com ID_misc->power_t.reset(); 240910234Syasuko.eckert@amd.com ID_misc->power_t = ID_misc->power; 241010234Syasuko.eckert@amd.com ID_misc->power_t.readOp.dynamic = ID_misc->power.readOp.dynamic * 241110234Syasuko.eckert@amd.com ID_misc->tdp_stats.readAc.access; 241210234Syasuko.eckert@amd.com ID_misc->rtp_stats.reset(); 241310234Syasuko.eckert@amd.com ID_misc->rtp_stats.readAc.access = core_stats.total_instructions; 241410234Syasuko.eckert@amd.com ID_misc->rt_power.reset(); 241510234Syasuko.eckert@amd.com ID_misc->rt_power.readOp.dynamic = ID_misc->power.readOp.dynamic * 241610234Syasuko.eckert@amd.com ID_misc->rtp_stats.readAc.access; 241710234Syasuko.eckert@amd.com 241810234Syasuko.eckert@amd.com power.reset(); 241910234Syasuko.eckert@amd.com rt_power.reset(); 242010234Syasuko.eckert@amd.com McPATComponent::computeEnergy(); 242110234Syasuko.eckert@amd.com 242210234Syasuko.eckert@amd.com output_data.reset(); 242310234Syasuko.eckert@amd.com if (icache) { 242410234Syasuko.eckert@amd.com output_data += icache->output_data; 242510234Syasuko.eckert@amd.com } 242610234Syasuko.eckert@amd.com if (IB) { 242710234Syasuko.eckert@amd.com IB->output_data.peak_dynamic_power = 242810234Syasuko.eckert@amd.com IB->power_t.readOp.dynamic * clockRate; 242910234Syasuko.eckert@amd.com IB->output_data.runtime_dynamic_energy = IB->rt_power.readOp.dynamic; 243010234Syasuko.eckert@amd.com output_data += IB->output_data; 243110234Syasuko.eckert@amd.com } 243210234Syasuko.eckert@amd.com if (BTB) { 243310234Syasuko.eckert@amd.com BTB->output_data.peak_dynamic_power = 243410234Syasuko.eckert@amd.com BTB->power_t.readOp.dynamic * clockRate; 243510234Syasuko.eckert@amd.com BTB->output_data.runtime_dynamic_energy = BTB->rt_power.readOp.dynamic; 243610234Syasuko.eckert@amd.com output_data += BTB->output_data; 243710234Syasuko.eckert@amd.com } 243810234Syasuko.eckert@amd.com if (BPT) { 243910234Syasuko.eckert@amd.com output_data += BPT->output_data; 244010234Syasuko.eckert@amd.com } 244110234Syasuko.eckert@amd.com if (ID_inst) { 244210234Syasuko.eckert@amd.com ID_inst->output_data.peak_dynamic_power = 244310234Syasuko.eckert@amd.com ID_inst->power_t.readOp.dynamic * clockRate; 244410234Syasuko.eckert@amd.com ID_inst->output_data.runtime_dynamic_energy = 244510234Syasuko.eckert@amd.com ID_inst->rt_power.readOp.dynamic; 244610234Syasuko.eckert@amd.com output_data += ID_inst->output_data; 244710234Syasuko.eckert@amd.com } 244810234Syasuko.eckert@amd.com if (ID_operand) { 244910234Syasuko.eckert@amd.com ID_operand->output_data.peak_dynamic_power = 245010234Syasuko.eckert@amd.com ID_operand->power_t.readOp.dynamic * clockRate; 245110234Syasuko.eckert@amd.com ID_operand->output_data.runtime_dynamic_energy = 245210234Syasuko.eckert@amd.com ID_operand->rt_power.readOp.dynamic; 245310234Syasuko.eckert@amd.com output_data += ID_operand->output_data; 245410234Syasuko.eckert@amd.com } 245510234Syasuko.eckert@amd.com if (ID_misc) { 245610234Syasuko.eckert@amd.com ID_misc->output_data.peak_dynamic_power = 245710234Syasuko.eckert@amd.com ID_misc->power_t.readOp.dynamic * clockRate; 245810234Syasuko.eckert@amd.com ID_misc->output_data.runtime_dynamic_energy = 245910234Syasuko.eckert@amd.com ID_misc->rt_power.readOp.dynamic; 246010234Syasuko.eckert@amd.com output_data += ID_misc->output_data; 246110234Syasuko.eckert@amd.com } 246210234Syasuko.eckert@amd.com} 246310234Syasuko.eckert@amd.com 246410234Syasuko.eckert@amd.comvoid InstFetchU::displayData(uint32_t indent, int plevel) { 246510234Syasuko.eckert@amd.com if (!exist) return; 246610234Syasuko.eckert@amd.com 246710234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 246810234Syasuko.eckert@amd.com 246910234Syasuko.eckert@amd.com if (core_params.predictionW > 0) { 247010234Syasuko.eckert@amd.com BTB->displayData(indent + 4, plevel); 247110234Syasuko.eckert@amd.com if (BPT->exist) { 247210234Syasuko.eckert@amd.com BPT->displayData(indent + 4, plevel); 247310152Satgutier@umich.edu } 247410234Syasuko.eckert@amd.com } 247510234Syasuko.eckert@amd.com IB->displayData(indent + 4, plevel); 247610234Syasuko.eckert@amd.com ID_inst->displayData(indent + 4, plevel); 247710234Syasuko.eckert@amd.com ID_operand->displayData(indent + 4, plevel); 247810234Syasuko.eckert@amd.com ID_misc->displayData(indent + 4, plevel); 247910234Syasuko.eckert@amd.com} 248010234Syasuko.eckert@amd.com 248110234Syasuko.eckert@amd.comvoid RENAMINGU::computeEnergy() { 248210234Syasuko.eckert@amd.com if (!exist) return; 248310234Syasuko.eckert@amd.com 248410234Syasuko.eckert@amd.com idcl->tdp_stats.reset(); 248510234Syasuko.eckert@amd.com idcl->rtp_stats.reset(); 248610234Syasuko.eckert@amd.com idcl->power_t.reset(); 248710234Syasuko.eckert@amd.com idcl->rt_power.reset(); 248810234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 248910234Syasuko.eckert@amd.com idcl->tdp_stats.readAc.access = core_params.decodeW; 249010234Syasuko.eckert@amd.com idcl->rtp_stats.readAc.access = 3 * core_params.decodeW * 249110234Syasuko.eckert@amd.com core_params.decodeW * core_stats.rename_reads; 249210234Syasuko.eckert@amd.com } else if (core_params.issueW > 1) { 249310234Syasuko.eckert@amd.com idcl->tdp_stats.readAc.access = core_params.decodeW; 249410234Syasuko.eckert@amd.com idcl->rtp_stats.readAc.access = 2 * core_stats.int_instructions; 249510234Syasuko.eckert@amd.com } 249610234Syasuko.eckert@amd.com idcl->power_t.readOp.dynamic = idcl->tdp_stats.readAc.access * 249710234Syasuko.eckert@amd.com idcl->power.readOp.dynamic; 249810234Syasuko.eckert@amd.com idcl->power_t.readOp.leakage = idcl->power.readOp.leakage * 249910234Syasuko.eckert@amd.com core_params.num_hthreads; 250010234Syasuko.eckert@amd.com idcl->power_t.readOp.gate_leakage = idcl->power.readOp.gate_leakage * 250110234Syasuko.eckert@amd.com core_params.num_hthreads; 250210234Syasuko.eckert@amd.com idcl->rt_power.readOp.dynamic = idcl->rtp_stats.readAc.access * 250310234Syasuko.eckert@amd.com idcl->power.readOp.dynamic; 250410234Syasuko.eckert@amd.com 250510234Syasuko.eckert@amd.com fdcl->tdp_stats.reset(); 250610234Syasuko.eckert@amd.com fdcl->rtp_stats.reset(); 250710234Syasuko.eckert@amd.com fdcl->power_t.reset(); 250810234Syasuko.eckert@amd.com fdcl->rt_power.reset(); 250910234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 251010234Syasuko.eckert@amd.com fdcl->tdp_stats.readAc.access = core_params.decodeW; 251110234Syasuko.eckert@amd.com fdcl->rtp_stats.readAc.access = 3 * core_params.fp_issueW * 251210234Syasuko.eckert@amd.com core_params.fp_issueW * core_stats.fp_rename_writes; 251310234Syasuko.eckert@amd.com } else if (core_params.issueW > 1) { 251410234Syasuko.eckert@amd.com fdcl->tdp_stats.readAc.access = core_params.decodeW; 251510234Syasuko.eckert@amd.com fdcl->rtp_stats.readAc.access = core_stats.fp_instructions; 251610234Syasuko.eckert@amd.com } 251710234Syasuko.eckert@amd.com fdcl->power_t.readOp.dynamic = fdcl->tdp_stats.readAc.access * 251810234Syasuko.eckert@amd.com fdcl->power.readOp.dynamic; 251910234Syasuko.eckert@amd.com fdcl->power_t.readOp.leakage = fdcl->power.readOp.leakage * 252010234Syasuko.eckert@amd.com core_params.num_hthreads; 252110234Syasuko.eckert@amd.com fdcl->power_t.readOp.gate_leakage = fdcl->power.readOp.gate_leakage * 252210234Syasuko.eckert@amd.com core_params.num_hthreads; 252310234Syasuko.eckert@amd.com fdcl->rt_power.readOp.dynamic = fdcl->rtp_stats.readAc.access * 252410234Syasuko.eckert@amd.com fdcl->power.readOp.dynamic; 252510234Syasuko.eckert@amd.com 252610234Syasuko.eckert@amd.com if (iRRAT) { 252710234Syasuko.eckert@amd.com iRRAT->tdp_stats.reset(); 252810234Syasuko.eckert@amd.com iRRAT->tdp_stats.readAc.access = iRRAT->l_ip.num_rd_ports; 252910234Syasuko.eckert@amd.com iRRAT->tdp_stats.writeAc.access = iRRAT->l_ip.num_wr_ports; 253010234Syasuko.eckert@amd.com iRRAT->rtp_stats.reset(); 253110234Syasuko.eckert@amd.com iRRAT->rtp_stats.readAc.access = core_stats.rename_writes; 253210234Syasuko.eckert@amd.com iRRAT->rtp_stats.writeAc.access = core_stats.rename_writes; 253310234Syasuko.eckert@amd.com iRRAT->power_t.reset(); 253410234Syasuko.eckert@amd.com iRRAT->power_t.readOp.dynamic += 253510234Syasuko.eckert@amd.com iRRAT->tdp_stats.readAc.access * iRRAT->power.readOp.dynamic + 253610234Syasuko.eckert@amd.com iRRAT->tdp_stats.writeAc.access * iRRAT->power.writeOp.dynamic; 253710234Syasuko.eckert@amd.com iRRAT->rt_power.reset(); 253810234Syasuko.eckert@amd.com iRRAT->rt_power.readOp.dynamic += 253910234Syasuko.eckert@amd.com iRRAT->rtp_stats.readAc.access * iRRAT->power.readOp.dynamic + 254010234Syasuko.eckert@amd.com iRRAT->rtp_stats.writeAc.access * iRRAT->power.writeOp.dynamic; 254110234Syasuko.eckert@amd.com iRRAT->power_t.readOp.leakage = 254210234Syasuko.eckert@amd.com iRRAT->power.readOp.leakage * core_params.num_hthreads; 254310234Syasuko.eckert@amd.com iRRAT->power_t.readOp.gate_leakage = 254410234Syasuko.eckert@amd.com iRRAT->power.readOp.gate_leakage * core_params.num_hthreads; 254510234Syasuko.eckert@amd.com } 254610234Syasuko.eckert@amd.com 254710234Syasuko.eckert@amd.com if (ifreeL) { 254810234Syasuko.eckert@amd.com ifreeL->tdp_stats.reset(); 254910234Syasuko.eckert@amd.com ifreeL->tdp_stats.readAc.access = core_params.decodeW; 255010234Syasuko.eckert@amd.com ifreeL->tdp_stats.writeAc.access = core_params.decodeW; 255110234Syasuko.eckert@amd.com ifreeL->rtp_stats.reset(); 255210234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 255310234Syasuko.eckert@amd.com ifreeL->rtp_stats.readAc.access = core_stats.rename_reads; 255410234Syasuko.eckert@amd.com ifreeL->rtp_stats.writeAc.access = 2 * core_stats.rename_writes; 255510234Syasuko.eckert@amd.com } else if (core_params.scheu_ty == ReservationStation) { 255610234Syasuko.eckert@amd.com ifreeL->rtp_stats.readAc.access = 255710234Syasuko.eckert@amd.com core_stats.rename_reads + core_stats.fp_rename_reads; 255810234Syasuko.eckert@amd.com ifreeL->rtp_stats.writeAc.access = 255910234Syasuko.eckert@amd.com 2 * (core_stats.rename_writes + core_stats.fp_rename_writes); 256010152Satgutier@umich.edu } 256110234Syasuko.eckert@amd.com ifreeL->power_t.reset(); 256210234Syasuko.eckert@amd.com ifreeL->power_t.readOp.dynamic += 256310234Syasuko.eckert@amd.com ifreeL->tdp_stats.readAc.access * ifreeL->power.readOp.dynamic + 256410234Syasuko.eckert@amd.com ifreeL->tdp_stats.writeAc.access * ifreeL->power.writeOp.dynamic; 256510234Syasuko.eckert@amd.com ifreeL->rt_power.reset(); 256610234Syasuko.eckert@amd.com ifreeL->rt_power.readOp.dynamic += 256710234Syasuko.eckert@amd.com ifreeL->rtp_stats.readAc.access * ifreeL->power.readOp.dynamic + 256810234Syasuko.eckert@amd.com ifreeL->rtp_stats.writeAc.access * ifreeL->power.writeOp.dynamic; 256910234Syasuko.eckert@amd.com ifreeL->power_t.readOp.leakage = 257010234Syasuko.eckert@amd.com ifreeL->power.readOp.leakage * core_params.num_hthreads; 257110234Syasuko.eckert@amd.com ifreeL->power_t.readOp.gate_leakage = 257210234Syasuko.eckert@amd.com ifreeL->power.readOp.gate_leakage * core_params.num_hthreads; 257310234Syasuko.eckert@amd.com } 257410234Syasuko.eckert@amd.com 257510234Syasuko.eckert@amd.com if (fRRAT) { 257610234Syasuko.eckert@amd.com fRRAT->tdp_stats.reset(); 257710234Syasuko.eckert@amd.com fRRAT->tdp_stats.readAc.access = fRRAT->l_ip.num_rd_ports; 257810234Syasuko.eckert@amd.com fRRAT->tdp_stats.writeAc.access = fRRAT->l_ip.num_wr_ports; 257910234Syasuko.eckert@amd.com fRRAT->rtp_stats.reset(); 258010234Syasuko.eckert@amd.com fRRAT->rtp_stats.readAc.access = core_stats.fp_rename_writes; 258110234Syasuko.eckert@amd.com fRRAT->rtp_stats.writeAc.access = core_stats.fp_rename_writes; 258210234Syasuko.eckert@amd.com fRRAT->power_t.reset(); 258310234Syasuko.eckert@amd.com fRRAT->power_t.readOp.dynamic += 258410234Syasuko.eckert@amd.com fRRAT->tdp_stats.readAc.access * fRRAT->power.readOp.dynamic + 258510234Syasuko.eckert@amd.com fRRAT->tdp_stats.writeAc.access * fRRAT->power.writeOp.dynamic; 258610234Syasuko.eckert@amd.com fRRAT->rt_power.reset(); 258710234Syasuko.eckert@amd.com fRRAT->rt_power.readOp.dynamic += 258810234Syasuko.eckert@amd.com fRRAT->rtp_stats.readAc.access * fRRAT->power.readOp.dynamic + 258910234Syasuko.eckert@amd.com fRRAT->rtp_stats.writeAc.access * fRRAT->power.writeOp.dynamic; 259010234Syasuko.eckert@amd.com fRRAT->power_t.readOp.leakage = 259110234Syasuko.eckert@amd.com fRRAT->power.readOp.leakage * core_params.num_hthreads; 259210234Syasuko.eckert@amd.com fRRAT->power_t.readOp.gate_leakage = 259310234Syasuko.eckert@amd.com fRRAT->power.readOp.gate_leakage * core_params.num_hthreads; 259410234Syasuko.eckert@amd.com } 259510234Syasuko.eckert@amd.com 259610234Syasuko.eckert@amd.com if (ffreeL) { 259710234Syasuko.eckert@amd.com ffreeL->tdp_stats.reset(); 259810234Syasuko.eckert@amd.com ffreeL->tdp_stats.readAc.access = core_params.decodeW; 259910234Syasuko.eckert@amd.com ffreeL->tdp_stats.writeAc.access = core_params.decodeW; 260010234Syasuko.eckert@amd.com ffreeL->rtp_stats.reset(); 260110234Syasuko.eckert@amd.com ffreeL->rtp_stats.readAc.access = core_stats.fp_rename_reads; 260210234Syasuko.eckert@amd.com ffreeL->rtp_stats.writeAc.access = 2 * core_stats.fp_rename_writes; 260310234Syasuko.eckert@amd.com ffreeL->power_t.reset(); 260410234Syasuko.eckert@amd.com ffreeL->power_t.readOp.dynamic += 260510234Syasuko.eckert@amd.com ffreeL->tdp_stats.readAc.access * ffreeL->power.readOp.dynamic + 260610234Syasuko.eckert@amd.com ffreeL->tdp_stats.writeAc.access * ffreeL->power.writeOp.dynamic; 260710234Syasuko.eckert@amd.com ffreeL->rt_power.reset(); 260810234Syasuko.eckert@amd.com ffreeL->rt_power.readOp.dynamic += 260910234Syasuko.eckert@amd.com ffreeL->rtp_stats.readAc.access * ffreeL->power.readOp.dynamic + 261010234Syasuko.eckert@amd.com ffreeL->rtp_stats.writeAc.access * ffreeL->power.writeOp.dynamic; 261110234Syasuko.eckert@amd.com ffreeL->power_t.readOp.leakage = 261210234Syasuko.eckert@amd.com ffreeL->power.readOp.leakage * core_params.num_hthreads; 261310234Syasuko.eckert@amd.com ffreeL->power_t.readOp.gate_leakage = 261410234Syasuko.eckert@amd.com ffreeL->power.readOp.gate_leakage * core_params.num_hthreads; 261510234Syasuko.eckert@amd.com } 261610234Syasuko.eckert@amd.com 261710234Syasuko.eckert@amd.com if (iFRAT) { 261810234Syasuko.eckert@amd.com tdp_stats.reset(); 261910234Syasuko.eckert@amd.com if (core_params.rm_ty == RAMbased) { 262010234Syasuko.eckert@amd.com iFRAT->tdp_stats.readAc.access = iFRAT->l_ip.num_rd_ports; 262110234Syasuko.eckert@amd.com iFRAT->tdp_stats.writeAc.access = iFRAT->l_ip.num_wr_ports; 262210234Syasuko.eckert@amd.com iFRAT->tdp_stats.searchAc.access = iFRAT->l_ip.num_search_ports; 262310234Syasuko.eckert@amd.com } else if ((core_params.rm_ty == CAMbased)) { 262410234Syasuko.eckert@amd.com iFRAT->tdp_stats.readAc.access = iFRAT->l_ip.num_search_ports; 262510234Syasuko.eckert@amd.com iFRAT->tdp_stats.writeAc.access = iFRAT->l_ip.num_wr_ports; 262610234Syasuko.eckert@amd.com } 262710234Syasuko.eckert@amd.com rtp_stats.reset(); 262810234Syasuko.eckert@amd.com iFRAT->rtp_stats.readAc.access = core_stats.rename_reads; 262910234Syasuko.eckert@amd.com iFRAT->rtp_stats.writeAc.access = core_stats.rename_writes; 263010234Syasuko.eckert@amd.com if (core_params.scheu_ty == ReservationStation && 263110234Syasuko.eckert@amd.com core_params.rm_ty == RAMbased) { 263210234Syasuko.eckert@amd.com iFRAT->rtp_stats.searchAc.access = 263310234Syasuko.eckert@amd.com core_stats.committed_int_instructions; 263410234Syasuko.eckert@amd.com } 263510234Syasuko.eckert@amd.com iFRAT->power_t.reset(); 263610234Syasuko.eckert@amd.com iFRAT->power_t.readOp.dynamic += iFRAT->tdp_stats.readAc.access 263710234Syasuko.eckert@amd.com * (iFRAT->local_result.power.readOp.dynamic 263810234Syasuko.eckert@amd.com + idcl->power.readOp.dynamic) 263910234Syasuko.eckert@amd.com + iFRAT->tdp_stats.writeAc.access 264010234Syasuko.eckert@amd.com * iFRAT->local_result.power.writeOp.dynamic 264110234Syasuko.eckert@amd.com + iFRAT->tdp_stats.searchAc.access 264210234Syasuko.eckert@amd.com * iFRAT->local_result.power.searchOp.dynamic; 264310234Syasuko.eckert@amd.com iFRAT->power_t.readOp.leakage = 264410234Syasuko.eckert@amd.com iFRAT->power.readOp.leakage * core_params.num_hthreads; 264510234Syasuko.eckert@amd.com iFRAT->power_t.readOp.gate_leakage = 264610234Syasuko.eckert@amd.com iFRAT->power.readOp.gate_leakage * core_params.num_hthreads; 264710234Syasuko.eckert@amd.com iFRAT->rt_power.reset(); 264810234Syasuko.eckert@amd.com iFRAT->rt_power.readOp.dynamic += iFRAT->rtp_stats.readAc.access 264910234Syasuko.eckert@amd.com * (iFRAT->local_result.power.readOp.dynamic 265010234Syasuko.eckert@amd.com + idcl->power.readOp.dynamic) 265110234Syasuko.eckert@amd.com + iFRAT->rtp_stats.writeAc.access 265210234Syasuko.eckert@amd.com * iFRAT->local_result.power.writeOp.dynamic 265310234Syasuko.eckert@amd.com + iFRAT->rtp_stats.searchAc.access 265410234Syasuko.eckert@amd.com * iFRAT->local_result.power.searchOp.dynamic; 265510234Syasuko.eckert@amd.com } 265610234Syasuko.eckert@amd.com 265710234Syasuko.eckert@amd.com if (fFRAT) { 265810234Syasuko.eckert@amd.com tdp_stats.reset(); 265910234Syasuko.eckert@amd.com fFRAT->tdp_stats.writeAc.access = fFRAT->l_ip.num_wr_ports; 266010234Syasuko.eckert@amd.com if ((core_params.rm_ty == CAMbased)) { 266110234Syasuko.eckert@amd.com fFRAT->tdp_stats.readAc.access = fFRAT->l_ip.num_search_ports; 266210234Syasuko.eckert@amd.com } else if (core_params.rm_ty == RAMbased) { 266310234Syasuko.eckert@amd.com fFRAT->tdp_stats.readAc.access = fFRAT->l_ip.num_rd_ports; 266410234Syasuko.eckert@amd.com if (core_params.scheu_ty == ReservationStation) { 266510234Syasuko.eckert@amd.com fFRAT->tdp_stats.searchAc.access = fFRAT->l_ip.num_search_ports; 266610234Syasuko.eckert@amd.com } 266710234Syasuko.eckert@amd.com } 266810234Syasuko.eckert@amd.com rtp_stats.reset(); 266910234Syasuko.eckert@amd.com fFRAT->rtp_stats.readAc.access = core_stats.fp_rename_reads; 267010234Syasuko.eckert@amd.com fFRAT->rtp_stats.writeAc.access = core_stats.fp_rename_writes; 267110234Syasuko.eckert@amd.com if (core_params.scheu_ty == ReservationStation && 267210234Syasuko.eckert@amd.com core_params.rm_ty == RAMbased) { 267310234Syasuko.eckert@amd.com fFRAT->rtp_stats.searchAc.access = 267410234Syasuko.eckert@amd.com core_stats.committed_fp_instructions; 267510234Syasuko.eckert@amd.com } 267610234Syasuko.eckert@amd.com fFRAT->power_t.reset(); 267710234Syasuko.eckert@amd.com fFRAT->power_t.readOp.dynamic += fFRAT->tdp_stats.readAc.access 267810234Syasuko.eckert@amd.com * (fFRAT->local_result.power.readOp.dynamic 267910234Syasuko.eckert@amd.com + fdcl->power.readOp.dynamic) 268010234Syasuko.eckert@amd.com + fFRAT->tdp_stats.writeAc.access 268110234Syasuko.eckert@amd.com * fFRAT->local_result.power.writeOp.dynamic 268210234Syasuko.eckert@amd.com + fFRAT->tdp_stats.searchAc.access 268310234Syasuko.eckert@amd.com * fFRAT->local_result.power.searchOp.dynamic; 268410234Syasuko.eckert@amd.com fFRAT->power_t.readOp.leakage = 268510234Syasuko.eckert@amd.com fFRAT->power.readOp.leakage * core_params.num_hthreads; 268610234Syasuko.eckert@amd.com fFRAT->power_t.readOp.gate_leakage = 268710234Syasuko.eckert@amd.com fFRAT->power.readOp.gate_leakage * core_params.num_hthreads; 268810234Syasuko.eckert@amd.com fFRAT->rt_power.reset(); 268910234Syasuko.eckert@amd.com fFRAT->rt_power.readOp.dynamic += fFRAT->rtp_stats.readAc.access 269010234Syasuko.eckert@amd.com * (fFRAT->local_result.power.readOp.dynamic 269110234Syasuko.eckert@amd.com + fdcl->power.readOp.dynamic) 269210234Syasuko.eckert@amd.com + fFRAT->rtp_stats.writeAc.access 269310234Syasuko.eckert@amd.com * fFRAT->local_result.power.writeOp.dynamic 269410234Syasuko.eckert@amd.com + fFRAT->rtp_stats.searchAc.access 269510234Syasuko.eckert@amd.com * fFRAT->local_result.power.searchOp.dynamic; 269610234Syasuko.eckert@amd.com } 269710234Syasuko.eckert@amd.com 269810234Syasuko.eckert@amd.com output_data.reset(); 269910234Syasuko.eckert@amd.com if (iFRAT) { 270010234Syasuko.eckert@amd.com iFRAT->output_data.peak_dynamic_power = 270110234Syasuko.eckert@amd.com iFRAT->power_t.readOp.dynamic * clockRate; 270210234Syasuko.eckert@amd.com iFRAT->output_data.subthreshold_leakage_power = 270310234Syasuko.eckert@amd.com iFRAT->power_t.readOp.leakage; 270410234Syasuko.eckert@amd.com iFRAT->output_data.gate_leakage_power = 270510234Syasuko.eckert@amd.com iFRAT->power_t.readOp.gate_leakage; 270610234Syasuko.eckert@amd.com iFRAT->output_data.runtime_dynamic_energy = 270710234Syasuko.eckert@amd.com iFRAT->rt_power.readOp.dynamic; 270810234Syasuko.eckert@amd.com output_data += iFRAT->output_data; 270910234Syasuko.eckert@amd.com } 271010234Syasuko.eckert@amd.com if (fFRAT) { 271110234Syasuko.eckert@amd.com fFRAT->output_data.peak_dynamic_power = 271210234Syasuko.eckert@amd.com fFRAT->power_t.readOp.dynamic * clockRate; 271310234Syasuko.eckert@amd.com fFRAT->output_data.subthreshold_leakage_power = 271410234Syasuko.eckert@amd.com fFRAT->power_t.readOp.leakage; 271510234Syasuko.eckert@amd.com fFRAT->output_data.gate_leakage_power = 271610234Syasuko.eckert@amd.com fFRAT->power_t.readOp.gate_leakage; 271710234Syasuko.eckert@amd.com fFRAT->output_data.runtime_dynamic_energy = 271810234Syasuko.eckert@amd.com fFRAT->rt_power.readOp.dynamic; 271910234Syasuko.eckert@amd.com output_data += fFRAT->output_data; 272010234Syasuko.eckert@amd.com } 272110234Syasuko.eckert@amd.com if (iRRAT) { 272210234Syasuko.eckert@amd.com iRRAT->output_data.peak_dynamic_power = 272310234Syasuko.eckert@amd.com iRRAT->power_t.readOp.dynamic * clockRate; 272410234Syasuko.eckert@amd.com iRRAT->output_data.subthreshold_leakage_power = 272510234Syasuko.eckert@amd.com iRRAT->power_t.readOp.leakage; 272610234Syasuko.eckert@amd.com iRRAT->output_data.gate_leakage_power = 272710234Syasuko.eckert@amd.com iRRAT->power_t.readOp.gate_leakage; 272810234Syasuko.eckert@amd.com iRRAT->output_data.runtime_dynamic_energy = 272910234Syasuko.eckert@amd.com iRRAT->rt_power.readOp.dynamic; 273010234Syasuko.eckert@amd.com output_data += iRRAT->output_data; 273110234Syasuko.eckert@amd.com } 273210234Syasuko.eckert@amd.com if (fRRAT) { 273310234Syasuko.eckert@amd.com fRRAT->output_data.peak_dynamic_power = 273410234Syasuko.eckert@amd.com fRRAT->power_t.readOp.dynamic * clockRate; 273510234Syasuko.eckert@amd.com fRRAT->output_data.subthreshold_leakage_power = 273610234Syasuko.eckert@amd.com fRRAT->power_t.readOp.leakage; 273710234Syasuko.eckert@amd.com fRRAT->output_data.gate_leakage_power = 273810234Syasuko.eckert@amd.com fRRAT->power_t.readOp.gate_leakage; 273910234Syasuko.eckert@amd.com fRRAT->output_data.runtime_dynamic_energy = 274010234Syasuko.eckert@amd.com fRRAT->rt_power.readOp.dynamic; 274110234Syasuko.eckert@amd.com output_data += fRRAT->output_data; 274210234Syasuko.eckert@amd.com } 274310234Syasuko.eckert@amd.com if (ifreeL) { 274410234Syasuko.eckert@amd.com ifreeL->output_data.peak_dynamic_power = 274510234Syasuko.eckert@amd.com ifreeL->power_t.readOp.dynamic * clockRate; 274610234Syasuko.eckert@amd.com ifreeL->output_data.subthreshold_leakage_power = 274710234Syasuko.eckert@amd.com ifreeL->power_t.readOp.leakage; 274810234Syasuko.eckert@amd.com ifreeL->output_data.gate_leakage_power = 274910234Syasuko.eckert@amd.com ifreeL->power_t.readOp.gate_leakage; 275010234Syasuko.eckert@amd.com ifreeL->output_data.runtime_dynamic_energy = 275110234Syasuko.eckert@amd.com ifreeL->rt_power.readOp.dynamic; 275210234Syasuko.eckert@amd.com output_data += ifreeL->output_data; 275310234Syasuko.eckert@amd.com } 275410234Syasuko.eckert@amd.com if (ffreeL) { 275510234Syasuko.eckert@amd.com ffreeL->output_data.peak_dynamic_power = 275610234Syasuko.eckert@amd.com ffreeL->power_t.readOp.dynamic * clockRate; 275710234Syasuko.eckert@amd.com ffreeL->output_data.subthreshold_leakage_power = 275810234Syasuko.eckert@amd.com ffreeL->power_t.readOp.leakage; 275910234Syasuko.eckert@amd.com ffreeL->output_data.gate_leakage_power = 276010234Syasuko.eckert@amd.com ffreeL->power_t.readOp.gate_leakage; 276110234Syasuko.eckert@amd.com ffreeL->output_data.runtime_dynamic_energy = 276210234Syasuko.eckert@amd.com ffreeL->rt_power.readOp.dynamic; 276310234Syasuko.eckert@amd.com output_data += ffreeL->output_data; 276410234Syasuko.eckert@amd.com } 276510234Syasuko.eckert@amd.com if (idcl) { 276610234Syasuko.eckert@amd.com idcl->output_data.peak_dynamic_power = 276710234Syasuko.eckert@amd.com idcl->power_t.readOp.dynamic * clockRate; 276810234Syasuko.eckert@amd.com idcl->output_data.subthreshold_leakage_power = 276910234Syasuko.eckert@amd.com idcl->power_t.readOp.leakage; 277010234Syasuko.eckert@amd.com idcl->output_data.gate_leakage_power = 277110234Syasuko.eckert@amd.com idcl->power_t.readOp.gate_leakage; 277210234Syasuko.eckert@amd.com idcl->output_data.runtime_dynamic_energy = 277310234Syasuko.eckert@amd.com idcl->rt_power.readOp.dynamic; 277410234Syasuko.eckert@amd.com output_data += idcl->output_data; 277510234Syasuko.eckert@amd.com } 277610234Syasuko.eckert@amd.com if (fdcl) { 277710234Syasuko.eckert@amd.com fdcl->output_data.peak_dynamic_power = 277810234Syasuko.eckert@amd.com fdcl->power_t.readOp.dynamic * clockRate; 277910234Syasuko.eckert@amd.com fdcl->output_data.subthreshold_leakage_power = 278010234Syasuko.eckert@amd.com fdcl->power_t.readOp.leakage; 278110234Syasuko.eckert@amd.com fdcl->output_data.gate_leakage_power = 278210234Syasuko.eckert@amd.com fdcl->power_t.readOp.gate_leakage; 278310234Syasuko.eckert@amd.com fdcl->output_data.runtime_dynamic_energy = 278410234Syasuko.eckert@amd.com fdcl->rt_power.readOp.dynamic; 278510234Syasuko.eckert@amd.com output_data += fdcl->output_data; 278610234Syasuko.eckert@amd.com } 278710234Syasuko.eckert@amd.com if (RAHT) { 278810234Syasuko.eckert@amd.com output_data += RAHT->output_data; 278910234Syasuko.eckert@amd.com } 279010152Satgutier@umich.edu} 279110152Satgutier@umich.edu 279210234Syasuko.eckert@amd.comvoid RENAMINGU::displayData(uint32_t indent, int plevel) { 279310234Syasuko.eckert@amd.com if (!exist) return; 279410234Syasuko.eckert@amd.com 279510234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 279610234Syasuko.eckert@amd.com 279710234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 279810234Syasuko.eckert@amd.com iFRAT->displayData(indent + 4, plevel); 279910234Syasuko.eckert@amd.com fFRAT->displayData(indent + 4, plevel); 280010234Syasuko.eckert@amd.com ifreeL->displayData(indent + 4, plevel); 280110234Syasuko.eckert@amd.com 280210234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 280310234Syasuko.eckert@amd.com iRRAT->displayData(indent + 4, plevel); 280410234Syasuko.eckert@amd.com fRRAT->displayData(indent + 4, plevel); 280510234Syasuko.eckert@amd.com ffreeL->displayData(indent + 4, plevel); 280610152Satgutier@umich.edu } 280710234Syasuko.eckert@amd.com } 280810234Syasuko.eckert@amd.com idcl->displayData(indent + 4, plevel); 280910234Syasuko.eckert@amd.com fdcl->displayData(indent + 4, plevel); 281010234Syasuko.eckert@amd.com} 281110234Syasuko.eckert@amd.com 281210234Syasuko.eckert@amd.comvoid SchedulerU::computeEnergy() { 281310234Syasuko.eckert@amd.com if (!exist) return; 281410234Syasuko.eckert@amd.com 281510234Syasuko.eckert@amd.com double ROB_duty_cycle; 281610234Syasuko.eckert@amd.com ROB_duty_cycle = 1; 281710234Syasuko.eckert@amd.com 281810234Syasuko.eckert@amd.com if (int_instruction_selection) { 281910234Syasuko.eckert@amd.com int_instruction_selection->computeEnergy(); 282010234Syasuko.eckert@amd.com } 282110234Syasuko.eckert@amd.com 282210234Syasuko.eckert@amd.com if (fp_instruction_selection) { 282310234Syasuko.eckert@amd.com fp_instruction_selection->computeEnergy(); 282410234Syasuko.eckert@amd.com } 282510234Syasuko.eckert@amd.com 282610234Syasuko.eckert@amd.com if (int_inst_window) { 282710234Syasuko.eckert@amd.com int_inst_window->tdp_stats.reset(); 282810234Syasuko.eckert@amd.com int_inst_window->rtp_stats.reset(); 282910234Syasuko.eckert@amd.com int_inst_window->power_t.reset(); 283010234Syasuko.eckert@amd.com int_inst_window->rt_power.reset(); 283110234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 283210234Syasuko.eckert@amd.com int_inst_window->tdp_stats.readAc.access = 283310234Syasuko.eckert@amd.com core_params.issueW * core_params.num_pipelines; 283410234Syasuko.eckert@amd.com int_inst_window->tdp_stats.writeAc.access = 283510234Syasuko.eckert@amd.com core_params.issueW * core_params.num_pipelines; 283610234Syasuko.eckert@amd.com int_inst_window->tdp_stats.searchAc.access = 283710234Syasuko.eckert@amd.com core_params.issueW * core_params.num_pipelines; 283810234Syasuko.eckert@amd.com 283910234Syasuko.eckert@amd.com int_inst_window->power_t.readOp.dynamic += 284010234Syasuko.eckert@amd.com int_inst_window->local_result.power.readOp.dynamic * 284110234Syasuko.eckert@amd.com int_inst_window->tdp_stats.readAc.access + 284210234Syasuko.eckert@amd.com int_inst_window->local_result.power.searchOp.dynamic * 284310234Syasuko.eckert@amd.com int_inst_window->tdp_stats.searchAc.access + 284410234Syasuko.eckert@amd.com int_inst_window->local_result.power.writeOp.dynamic * 284510234Syasuko.eckert@amd.com int_inst_window->tdp_stats.writeAc.access; 284610234Syasuko.eckert@amd.com 284710234Syasuko.eckert@amd.com int_inst_window->rtp_stats.readAc.access = 284810234Syasuko.eckert@amd.com core_stats.inst_window_reads; 284910234Syasuko.eckert@amd.com int_inst_window->rtp_stats.writeAc.access = 285010234Syasuko.eckert@amd.com core_stats.inst_window_writes; 285110234Syasuko.eckert@amd.com int_inst_window->rtp_stats.searchAc.access = 285210234Syasuko.eckert@amd.com core_stats.inst_window_wakeup_accesses; 285310234Syasuko.eckert@amd.com 285410234Syasuko.eckert@amd.com int_inst_window->rt_power.readOp.dynamic += 285510234Syasuko.eckert@amd.com int_inst_window->local_result.power.readOp.dynamic * 285610234Syasuko.eckert@amd.com int_inst_window->rtp_stats.readAc.access + 285710234Syasuko.eckert@amd.com int_inst_window->local_result.power.searchOp.dynamic * 285810234Syasuko.eckert@amd.com int_inst_window->rtp_stats.searchAc.access + 285910234Syasuko.eckert@amd.com int_inst_window->local_result.power.writeOp.dynamic * 286010234Syasuko.eckert@amd.com int_inst_window->rtp_stats.writeAc.access; 286110234Syasuko.eckert@amd.com } else if (core_params.multithreaded) { 286210234Syasuko.eckert@amd.com int_inst_window->tdp_stats.readAc.access = 286310234Syasuko.eckert@amd.com core_params.issueW * core_params.num_pipelines; 286410234Syasuko.eckert@amd.com int_inst_window->tdp_stats.writeAc.access = 286510234Syasuko.eckert@amd.com core_params.issueW * core_params.num_pipelines; 286610234Syasuko.eckert@amd.com int_inst_window->tdp_stats.searchAc.access = 286710234Syasuko.eckert@amd.com core_params.issueW * core_params.num_pipelines; 286810234Syasuko.eckert@amd.com 286910234Syasuko.eckert@amd.com int_inst_window->power_t.readOp.dynamic += 287010234Syasuko.eckert@amd.com int_inst_window->local_result.power.readOp.dynamic * 287110234Syasuko.eckert@amd.com int_inst_window->tdp_stats.readAc.access + 287210234Syasuko.eckert@amd.com int_inst_window->local_result.power.searchOp.dynamic * 287310234Syasuko.eckert@amd.com int_inst_window->tdp_stats.searchAc.access + 287410234Syasuko.eckert@amd.com int_inst_window->local_result.power.writeOp.dynamic * 287510234Syasuko.eckert@amd.com int_inst_window->tdp_stats.writeAc.access; 287610234Syasuko.eckert@amd.com 287710234Syasuko.eckert@amd.com int_inst_window->rtp_stats.readAc.access = 287810234Syasuko.eckert@amd.com core_stats.int_instructions + core_stats.fp_instructions; 287910234Syasuko.eckert@amd.com int_inst_window->rtp_stats.writeAc.access = 288010234Syasuko.eckert@amd.com core_stats.int_instructions + core_stats.fp_instructions; 288110234Syasuko.eckert@amd.com int_inst_window->rtp_stats.searchAc.access = 288210234Syasuko.eckert@amd.com 2 * (core_stats.int_instructions + core_stats.fp_instructions); 288310234Syasuko.eckert@amd.com 288410234Syasuko.eckert@amd.com int_inst_window->rt_power.readOp.dynamic += 288510234Syasuko.eckert@amd.com int_inst_window->local_result.power.readOp.dynamic * 288610234Syasuko.eckert@amd.com int_inst_window->rtp_stats.readAc.access + 288710234Syasuko.eckert@amd.com int_inst_window->local_result.power.searchOp.dynamic * 288810234Syasuko.eckert@amd.com int_inst_window->rtp_stats.searchAc.access + 288910234Syasuko.eckert@amd.com int_inst_window->local_result.power.writeOp.dynamic * 289010234Syasuko.eckert@amd.com int_inst_window->rtp_stats.writeAc.access; 289110152Satgutier@umich.edu } 289210234Syasuko.eckert@amd.com } 289310234Syasuko.eckert@amd.com 289410234Syasuko.eckert@amd.com if (fp_inst_window) { 289510234Syasuko.eckert@amd.com fp_inst_window->tdp_stats.reset(); 289610234Syasuko.eckert@amd.com fp_inst_window->tdp_stats.readAc.access = 289710234Syasuko.eckert@amd.com fp_inst_window->l_ip.num_rd_ports * core_params.num_fp_pipelines; 289810234Syasuko.eckert@amd.com fp_inst_window->tdp_stats.writeAc.access = 289910234Syasuko.eckert@amd.com fp_inst_window->l_ip.num_wr_ports * core_params.num_fp_pipelines; 290010234Syasuko.eckert@amd.com fp_inst_window->tdp_stats.searchAc.access = 290110234Syasuko.eckert@amd.com fp_inst_window->l_ip.num_search_ports * 290210234Syasuko.eckert@amd.com core_params.num_fp_pipelines; 290310234Syasuko.eckert@amd.com 290410234Syasuko.eckert@amd.com fp_inst_window->rtp_stats.reset(); 290510234Syasuko.eckert@amd.com fp_inst_window->rtp_stats.readAc.access = 290610234Syasuko.eckert@amd.com core_stats.fp_inst_window_reads; 290710234Syasuko.eckert@amd.com fp_inst_window->rtp_stats.writeAc.access = 290810234Syasuko.eckert@amd.com core_stats.fp_inst_window_writes; 290910234Syasuko.eckert@amd.com fp_inst_window->rtp_stats.searchAc.access = 291010234Syasuko.eckert@amd.com core_stats.fp_inst_window_wakeup_accesses; 291110234Syasuko.eckert@amd.com 291210234Syasuko.eckert@amd.com fp_inst_window->power_t.reset(); 291310234Syasuko.eckert@amd.com fp_inst_window->power_t.readOp.dynamic += 291410234Syasuko.eckert@amd.com fp_inst_window->power.readOp.dynamic * 291510234Syasuko.eckert@amd.com fp_inst_window->tdp_stats.readAc.access + 291610234Syasuko.eckert@amd.com fp_inst_window->power.searchOp.dynamic * 291710234Syasuko.eckert@amd.com fp_inst_window->tdp_stats.searchAc.access + 291810234Syasuko.eckert@amd.com fp_inst_window->power.writeOp.dynamic * 291910234Syasuko.eckert@amd.com fp_inst_window->tdp_stats.writeAc.access; 292010234Syasuko.eckert@amd.com 292110234Syasuko.eckert@amd.com fp_inst_window->rt_power.reset(); 292210234Syasuko.eckert@amd.com fp_inst_window->rt_power.readOp.dynamic += 292310234Syasuko.eckert@amd.com fp_inst_window->power.readOp.dynamic * 292410234Syasuko.eckert@amd.com fp_inst_window->rtp_stats.readAc.access + 292510234Syasuko.eckert@amd.com fp_inst_window->power.searchOp.dynamic * 292610234Syasuko.eckert@amd.com fp_inst_window->rtp_stats.searchAc.access + 292710234Syasuko.eckert@amd.com fp_inst_window->power.writeOp.dynamic * 292810234Syasuko.eckert@amd.com fp_inst_window->rtp_stats.writeAc.access; 292910234Syasuko.eckert@amd.com } 293010234Syasuko.eckert@amd.com 293110234Syasuko.eckert@amd.com if (ROB) { 293210234Syasuko.eckert@amd.com ROB->tdp_stats.reset(); 293310234Syasuko.eckert@amd.com ROB->tdp_stats.readAc.access = core_params.commitW * 293410234Syasuko.eckert@amd.com core_params.num_pipelines * ROB_duty_cycle; 293510234Syasuko.eckert@amd.com ROB->tdp_stats.writeAc.access = core_params.issueW * 293610234Syasuko.eckert@amd.com core_params.num_pipelines * ROB_duty_cycle; 293710234Syasuko.eckert@amd.com ROB->rtp_stats.reset(); 293810234Syasuko.eckert@amd.com ROB->rtp_stats.readAc.access = core_stats.ROB_reads; 293910234Syasuko.eckert@amd.com ROB->rtp_stats.writeAc.access = core_stats.ROB_writes; 294010234Syasuko.eckert@amd.com ROB->power_t.reset(); 294110234Syasuko.eckert@amd.com ROB->power_t.readOp.dynamic += 294210234Syasuko.eckert@amd.com ROB->local_result.power.readOp.dynamic * 294310234Syasuko.eckert@amd.com ROB->tdp_stats.readAc.access + 294410234Syasuko.eckert@amd.com ROB->local_result.power.writeOp.dynamic * 294510234Syasuko.eckert@amd.com ROB->tdp_stats.writeAc.access; 294610234Syasuko.eckert@amd.com ROB->rt_power.reset(); 294710234Syasuko.eckert@amd.com ROB->rt_power.readOp.dynamic += 294810234Syasuko.eckert@amd.com ROB->local_result.power.readOp.dynamic * 294910234Syasuko.eckert@amd.com ROB->rtp_stats.readAc.access + 295010234Syasuko.eckert@amd.com ROB->local_result.power.writeOp.dynamic * 295110234Syasuko.eckert@amd.com ROB->rtp_stats.writeAc.access; 295210234Syasuko.eckert@amd.com } 295310234Syasuko.eckert@amd.com 295410234Syasuko.eckert@amd.com output_data.reset(); 295510234Syasuko.eckert@amd.com if (int_inst_window) { 295610234Syasuko.eckert@amd.com int_inst_window->output_data.subthreshold_leakage_power = 295710234Syasuko.eckert@amd.com int_inst_window->power_t.readOp.leakage; 295810234Syasuko.eckert@amd.com int_inst_window->output_data.gate_leakage_power = 295910234Syasuko.eckert@amd.com int_inst_window->power_t.readOp.gate_leakage; 296010234Syasuko.eckert@amd.com int_inst_window->output_data.peak_dynamic_power = 296110234Syasuko.eckert@amd.com int_inst_window->power_t.readOp.dynamic * clockRate; 296210234Syasuko.eckert@amd.com int_inst_window->output_data.runtime_dynamic_energy = 296310234Syasuko.eckert@amd.com int_inst_window->rt_power.readOp.dynamic; 296410234Syasuko.eckert@amd.com output_data += int_inst_window->output_data; 296510234Syasuko.eckert@amd.com } 296610234Syasuko.eckert@amd.com if (fp_inst_window) { 296710234Syasuko.eckert@amd.com fp_inst_window->output_data.subthreshold_leakage_power = 296810234Syasuko.eckert@amd.com fp_inst_window->power_t.readOp.leakage; 296910234Syasuko.eckert@amd.com fp_inst_window->output_data.gate_leakage_power = 297010234Syasuko.eckert@amd.com fp_inst_window->power_t.readOp.gate_leakage; 297110234Syasuko.eckert@amd.com fp_inst_window->output_data.peak_dynamic_power = 297210234Syasuko.eckert@amd.com fp_inst_window->power_t.readOp.dynamic * clockRate; 297310234Syasuko.eckert@amd.com fp_inst_window->output_data.runtime_dynamic_energy = 297410234Syasuko.eckert@amd.com fp_inst_window->rt_power.readOp.dynamic; 297510234Syasuko.eckert@amd.com output_data += fp_inst_window->output_data; 297610234Syasuko.eckert@amd.com } 297710234Syasuko.eckert@amd.com if (ROB) { 297810234Syasuko.eckert@amd.com ROB->output_data.peak_dynamic_power = 297910234Syasuko.eckert@amd.com ROB->power_t.readOp.dynamic * clockRate; 298010234Syasuko.eckert@amd.com ROB->output_data.runtime_dynamic_energy = 298110234Syasuko.eckert@amd.com ROB->rt_power.readOp.dynamic; 298210234Syasuko.eckert@amd.com output_data += ROB->output_data; 298310234Syasuko.eckert@amd.com } 298410234Syasuko.eckert@amd.com 298510234Syasuko.eckert@amd.com // Integer and FP instruction selection logic is not included in the 298610234Syasuko.eckert@amd.com // roll-up due to the uninitialized area 298710234Syasuko.eckert@amd.com /* 298810234Syasuko.eckert@amd.com if (int_instruction_selection) { 298910234Syasuko.eckert@amd.com output_data += int_instruction_selection->output_data; 299010234Syasuko.eckert@amd.com } 299110234Syasuko.eckert@amd.com if (fp_instruction_selection) { 299210234Syasuko.eckert@amd.com output_data += fp_instruction_selection->output_data; 299310234Syasuko.eckert@amd.com } 299410234Syasuko.eckert@amd.com */ 299510234Syasuko.eckert@amd.com} 299610234Syasuko.eckert@amd.com 299710234Syasuko.eckert@amd.comvoid SchedulerU::displayData(uint32_t indent, int plevel) { 299810234Syasuko.eckert@amd.com if (!exist) return; 299910234Syasuko.eckert@amd.com 300010234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 300110234Syasuko.eckert@amd.com 300210234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 300310234Syasuko.eckert@amd.com int_inst_window->displayData(indent + 4, plevel); 300410234Syasuko.eckert@amd.com fp_inst_window->displayData(indent + 4, plevel); 300510234Syasuko.eckert@amd.com if (core_params.ROB_size > 0) { 300610234Syasuko.eckert@amd.com ROB->displayData(indent + 4, plevel); 300710152Satgutier@umich.edu } 300810234Syasuko.eckert@amd.com } else if (core_params.multithreaded) { 300910234Syasuko.eckert@amd.com int_inst_window->displayData(indent + 4, plevel); 301010234Syasuko.eckert@amd.com } 301110234Syasuko.eckert@amd.com 301210234Syasuko.eckert@amd.com // Integer and FP instruction selection logic is not included in the 301310234Syasuko.eckert@amd.com // roll-up due to the uninitialized area 301410234Syasuko.eckert@amd.com /* 301510234Syasuko.eckert@amd.com if (int_instruction_selection) { 301610234Syasuko.eckert@amd.com int_instruction_selection->displayData(indent + 4, plevel); 301710234Syasuko.eckert@amd.com } 301810234Syasuko.eckert@amd.com if (fp_instruction_selection) { 301910234Syasuko.eckert@amd.com fp_instruction_selection->displayData(indent + 4, plevel); 302010234Syasuko.eckert@amd.com } 302110234Syasuko.eckert@amd.com */ 302210234Syasuko.eckert@amd.com} 302310234Syasuko.eckert@amd.com 302410234Syasuko.eckert@amd.comvoid LoadStoreU::computeEnergy() { 302510234Syasuko.eckert@amd.com if (!exist) return; 302610234Syasuko.eckert@amd.com 302710234Syasuko.eckert@amd.com LSQ->tdp_stats.reset(); 302810234Syasuko.eckert@amd.com LSQ->tdp_stats.readAc.access = LSQ->l_ip.num_search_ports * 302910234Syasuko.eckert@amd.com core_stats.LSU_duty_cycle; 303010234Syasuko.eckert@amd.com LSQ->tdp_stats.writeAc.access = LSQ->l_ip.num_search_ports * 303110234Syasuko.eckert@amd.com core_stats.LSU_duty_cycle; 303210234Syasuko.eckert@amd.com LSQ->rtp_stats.reset(); 303310234Syasuko.eckert@amd.com // Flush overhead conidered 303410234Syasuko.eckert@amd.com LSQ->rtp_stats.readAc.access = (core_stats.load_instructions + 303510234Syasuko.eckert@amd.com core_stats.store_instructions) * 2; 303610234Syasuko.eckert@amd.com LSQ->rtp_stats.writeAc.access = (core_stats.load_instructions + 303710234Syasuko.eckert@amd.com core_stats.store_instructions) * 2; 303810234Syasuko.eckert@amd.com LSQ->power_t.reset(); 303910234Syasuko.eckert@amd.com //every memory access invloves at least two operations on LSQ 304010234Syasuko.eckert@amd.com LSQ->power_t.readOp.dynamic += LSQ->tdp_stats.readAc.access * 304110234Syasuko.eckert@amd.com (LSQ->local_result.power.searchOp.dynamic + 304210234Syasuko.eckert@amd.com LSQ->local_result.power.readOp.dynamic) + 304310234Syasuko.eckert@amd.com LSQ->tdp_stats.writeAc.access * LSQ->local_result.power.writeOp.dynamic; 304410234Syasuko.eckert@amd.com LSQ->rt_power.reset(); 304510234Syasuko.eckert@amd.com //every memory access invloves at least two operations on LSQ 304610234Syasuko.eckert@amd.com LSQ->rt_power.readOp.dynamic += LSQ->rtp_stats.readAc.access * 304710234Syasuko.eckert@amd.com (LSQ->local_result.power.searchOp.dynamic + 304810234Syasuko.eckert@amd.com LSQ->local_result.power.readOp.dynamic) + 304910234Syasuko.eckert@amd.com LSQ->rtp_stats.writeAc.access * LSQ->local_result.power.writeOp.dynamic; 305010234Syasuko.eckert@amd.com 305110234Syasuko.eckert@amd.com if (LoadQ) { 305210234Syasuko.eckert@amd.com LoadQ->tdp_stats.reset(); 305310234Syasuko.eckert@amd.com LoadQ->tdp_stats.readAc.access = LoadQ->l_ip.num_search_ports * 305410234Syasuko.eckert@amd.com core_stats.LSU_duty_cycle; 305510234Syasuko.eckert@amd.com LoadQ->tdp_stats.writeAc.access = LoadQ->l_ip.num_search_ports * 305610234Syasuko.eckert@amd.com core_stats.LSU_duty_cycle; 305710234Syasuko.eckert@amd.com LoadQ->rtp_stats.reset(); 305810234Syasuko.eckert@amd.com LoadQ->rtp_stats.readAc.access = core_stats.load_instructions + 305910234Syasuko.eckert@amd.com core_stats.store_instructions; 306010234Syasuko.eckert@amd.com LoadQ->rtp_stats.writeAc.access = core_stats.load_instructions + 306110234Syasuko.eckert@amd.com core_stats.store_instructions; 306210234Syasuko.eckert@amd.com LoadQ->power_t.reset(); 306310234Syasuko.eckert@amd.com //every memory access invloves at least two operations on LoadQ 306410234Syasuko.eckert@amd.com LoadQ->power_t.readOp.dynamic += 306510234Syasuko.eckert@amd.com LoadQ->tdp_stats.readAc.access * 306610234Syasuko.eckert@amd.com (LoadQ->local_result.power.searchOp.dynamic + 306710234Syasuko.eckert@amd.com LoadQ->local_result.power.readOp.dynamic) + 306810234Syasuko.eckert@amd.com LoadQ->tdp_stats.writeAc.access * 306910234Syasuko.eckert@amd.com LoadQ->local_result.power.writeOp.dynamic; 307010234Syasuko.eckert@amd.com LoadQ->rt_power.reset(); 307110234Syasuko.eckert@amd.com //every memory access invloves at least two operations on LoadQ 307210234Syasuko.eckert@amd.com LoadQ->rt_power.readOp.dynamic += LoadQ->rtp_stats.readAc.access * 307310234Syasuko.eckert@amd.com (LoadQ->local_result.power.searchOp.dynamic + 307410234Syasuko.eckert@amd.com LoadQ->local_result.power.readOp.dynamic) + 307510234Syasuko.eckert@amd.com LoadQ->rtp_stats.writeAc.access * 307610234Syasuko.eckert@amd.com LoadQ->local_result.power.writeOp.dynamic; 307710234Syasuko.eckert@amd.com } 307810234Syasuko.eckert@amd.com 307910234Syasuko.eckert@amd.com McPATComponent::computeEnergy(); 308010234Syasuko.eckert@amd.com 308110234Syasuko.eckert@amd.com output_data.reset(); 308210234Syasuko.eckert@amd.com if (dcache) { 308310234Syasuko.eckert@amd.com output_data += dcache->output_data; 308410234Syasuko.eckert@amd.com } 308510234Syasuko.eckert@amd.com if (LSQ) { 308610234Syasuko.eckert@amd.com LSQ->output_data.peak_dynamic_power = 308710234Syasuko.eckert@amd.com LSQ->power_t.readOp.dynamic * clockRate; 308810234Syasuko.eckert@amd.com LSQ->output_data.runtime_dynamic_energy = LSQ->rt_power.readOp.dynamic; 308910234Syasuko.eckert@amd.com output_data += LSQ->output_data; 309010234Syasuko.eckert@amd.com } 309110234Syasuko.eckert@amd.com if (LoadQ) { 309210234Syasuko.eckert@amd.com LoadQ->output_data.peak_dynamic_power = 309310234Syasuko.eckert@amd.com LoadQ->power_t.readOp.dynamic * clockRate; 309410234Syasuko.eckert@amd.com LoadQ->output_data.runtime_dynamic_energy = 309510234Syasuko.eckert@amd.com LoadQ->rt_power.readOp.dynamic; 309610234Syasuko.eckert@amd.com output_data += LoadQ->output_data; 309710234Syasuko.eckert@amd.com } 309810234Syasuko.eckert@amd.com} 309910234Syasuko.eckert@amd.com 310010234Syasuko.eckert@amd.comvoid LoadStoreU::displayData(uint32_t indent, int plevel) { 310110234Syasuko.eckert@amd.com if (!exist) return; 310210234Syasuko.eckert@amd.com 310310234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 310410234Syasuko.eckert@amd.com 310510234Syasuko.eckert@amd.com if (LoadQ) { 310610234Syasuko.eckert@amd.com LoadQ->displayData(indent + 4, plevel); 310710234Syasuko.eckert@amd.com } 310810234Syasuko.eckert@amd.com LSQ->displayData(indent + 4, plevel); 310910234Syasuko.eckert@amd.com 311010234Syasuko.eckert@amd.com} 311110234Syasuko.eckert@amd.com 311210234Syasuko.eckert@amd.comvoid MemManU::computeEnergy() { 311310234Syasuko.eckert@amd.com if (!exist) return; 311410234Syasuko.eckert@amd.com 311510234Syasuko.eckert@amd.com itlb->tdp_stats.reset(); 311610234Syasuko.eckert@amd.com itlb->tdp_stats.readAc.access = itlb->l_ip.num_search_ports; 311710234Syasuko.eckert@amd.com itlb->tdp_stats.readAc.miss = 0; 311810234Syasuko.eckert@amd.com itlb->tdp_stats.readAc.hit = itlb->tdp_stats.readAc.access - 311910234Syasuko.eckert@amd.com itlb->tdp_stats.readAc.miss; 312010234Syasuko.eckert@amd.com itlb->rtp_stats.reset(); 312110234Syasuko.eckert@amd.com itlb->rtp_stats.readAc.access = mem_man_stats.itlb_total_accesses; 312210234Syasuko.eckert@amd.com itlb->rtp_stats.writeAc.access = mem_man_stats.itlb_total_misses; 312310234Syasuko.eckert@amd.com 312410234Syasuko.eckert@amd.com itlb->power_t.reset(); 312510234Syasuko.eckert@amd.com //FA spent most power in tag, so use total access not hits 312610234Syasuko.eckert@amd.com itlb->power_t.readOp.dynamic += itlb->tdp_stats.readAc.access * 312710234Syasuko.eckert@amd.com itlb->local_result.power.searchOp.dynamic + 312810234Syasuko.eckert@amd.com itlb->tdp_stats.readAc.miss * 312910234Syasuko.eckert@amd.com itlb->local_result.power.writeOp.dynamic; 313010234Syasuko.eckert@amd.com itlb->rt_power.reset(); 313110234Syasuko.eckert@amd.com //FA spent most power in tag, so use total access not hits 313210234Syasuko.eckert@amd.com itlb->rt_power.readOp.dynamic += itlb->rtp_stats.readAc.access * 313310234Syasuko.eckert@amd.com itlb->local_result.power.searchOp.dynamic + 313410234Syasuko.eckert@amd.com itlb->rtp_stats.writeAc.access * 313510234Syasuko.eckert@amd.com itlb->local_result.power.writeOp.dynamic; 313610234Syasuko.eckert@amd.com 313710234Syasuko.eckert@amd.com dtlb->tdp_stats.reset(); 313810234Syasuko.eckert@amd.com dtlb->tdp_stats.readAc.access = dtlb->l_ip.num_search_ports * 313910234Syasuko.eckert@amd.com core_stats.LSU_duty_cycle; 314010234Syasuko.eckert@amd.com dtlb->tdp_stats.readAc.miss = 0; 314110234Syasuko.eckert@amd.com dtlb->tdp_stats.readAc.hit = dtlb->tdp_stats.readAc.access - 314210234Syasuko.eckert@amd.com dtlb->tdp_stats.readAc.miss; 314310234Syasuko.eckert@amd.com dtlb->rtp_stats.reset(); 314410234Syasuko.eckert@amd.com dtlb->rtp_stats.readAc.access = mem_man_stats.dtlb_read_accesses + 314510234Syasuko.eckert@amd.com mem_man_stats.dtlb_write_misses; 314610234Syasuko.eckert@amd.com dtlb->rtp_stats.writeAc.access = mem_man_stats.dtlb_write_accesses + 314710234Syasuko.eckert@amd.com mem_man_stats.dtlb_read_misses; 314810234Syasuko.eckert@amd.com 314910234Syasuko.eckert@amd.com dtlb->power_t.reset(); 315010234Syasuko.eckert@amd.com //FA spent most power in tag, so use total access not hits 315110234Syasuko.eckert@amd.com dtlb->power_t.readOp.dynamic += dtlb->tdp_stats.readAc.access * 315210234Syasuko.eckert@amd.com dtlb->local_result.power.searchOp.dynamic + 315310234Syasuko.eckert@amd.com dtlb->tdp_stats.readAc.miss * 315410234Syasuko.eckert@amd.com dtlb->local_result.power.writeOp.dynamic; 315510234Syasuko.eckert@amd.com dtlb->rt_power.reset(); 315610234Syasuko.eckert@amd.com //FA spent most power in tag, so use total access not hits 315710234Syasuko.eckert@amd.com dtlb->rt_power.readOp.dynamic += dtlb->rtp_stats.readAc.access * 315810234Syasuko.eckert@amd.com dtlb->local_result.power.searchOp.dynamic + 315910234Syasuko.eckert@amd.com dtlb->rtp_stats.writeAc.access * 316010234Syasuko.eckert@amd.com dtlb->local_result.power.writeOp.dynamic; 316110234Syasuko.eckert@amd.com 316210234Syasuko.eckert@amd.com output_data.reset(); 316310234Syasuko.eckert@amd.com if (itlb) { 316410234Syasuko.eckert@amd.com itlb->output_data.peak_dynamic_power = itlb->power_t.readOp.dynamic * 316510234Syasuko.eckert@amd.com clockRate; 316610234Syasuko.eckert@amd.com itlb->output_data.runtime_dynamic_energy = 316710234Syasuko.eckert@amd.com itlb->rt_power.readOp.dynamic; 316810234Syasuko.eckert@amd.com output_data += itlb->output_data; 316910234Syasuko.eckert@amd.com } 317010234Syasuko.eckert@amd.com if (dtlb) { 317110234Syasuko.eckert@amd.com dtlb->output_data.peak_dynamic_power = 317210234Syasuko.eckert@amd.com dtlb->power_t.readOp.dynamic * clockRate; 317310234Syasuko.eckert@amd.com dtlb->output_data.runtime_dynamic_energy = 317410234Syasuko.eckert@amd.com dtlb->rt_power.readOp.dynamic; 317510234Syasuko.eckert@amd.com output_data += dtlb->output_data; 317610234Syasuko.eckert@amd.com } 317710234Syasuko.eckert@amd.com} 317810234Syasuko.eckert@amd.com 317910234Syasuko.eckert@amd.comvoid MemManU::displayData(uint32_t indent, int plevel) { 318010234Syasuko.eckert@amd.com if (!exist) return; 318110234Syasuko.eckert@amd.com 318210234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 318310234Syasuko.eckert@amd.com 318410234Syasuko.eckert@amd.com itlb->displayData(indent + 4, plevel); 318510234Syasuko.eckert@amd.com dtlb->displayData(indent + 4, plevel); 318610234Syasuko.eckert@amd.com} 318710234Syasuko.eckert@amd.com 318810234Syasuko.eckert@amd.comvoid RegFU::computeEnergy() { 318910234Syasuko.eckert@amd.com /* 319010234Syasuko.eckert@amd.com * Architecture RF and physical RF cannot be present at the same time. 319110234Syasuko.eckert@amd.com * Therefore, the RF stats can only refer to either ARF or PRF; 319210234Syasuko.eckert@amd.com * And the same stats can be used for both. 319310234Syasuko.eckert@amd.com */ 319410234Syasuko.eckert@amd.com if (!exist) return; 319510234Syasuko.eckert@amd.com 319610234Syasuko.eckert@amd.com IRF->tdp_stats.reset(); 319710234Syasuko.eckert@amd.com IRF->tdp_stats.readAc.access = 319810234Syasuko.eckert@amd.com core_params.issueW * NUM_INT_INST_SOURCE_OPERANDS * 319910234Syasuko.eckert@amd.com (core_stats.ALU_duty_cycle * 1.1 + 320010234Syasuko.eckert@amd.com (core_params.num_muls > 0 ? core_stats.MUL_duty_cycle : 0)) * 320110234Syasuko.eckert@amd.com core_params.num_pipelines; 320210234Syasuko.eckert@amd.com IRF->tdp_stats.writeAc.access = 320310234Syasuko.eckert@amd.com core_params.issueW * 320410234Syasuko.eckert@amd.com (core_stats.ALU_duty_cycle * 1.1 + 320510234Syasuko.eckert@amd.com (core_params.num_muls > 0 ? core_stats.MUL_duty_cycle : 0)) * 320610234Syasuko.eckert@amd.com core_params.num_pipelines; 320710234Syasuko.eckert@amd.com IRF->rtp_stats.reset(); 320810234Syasuko.eckert@amd.com IRF->rtp_stats.readAc.access = core_stats.int_regfile_reads; 320910234Syasuko.eckert@amd.com IRF->rtp_stats.writeAc.access = core_stats.int_regfile_writes; 321010234Syasuko.eckert@amd.com if (core_params.regWindowing) { 321110234Syasuko.eckert@amd.com IRF->rtp_stats.readAc.access += core_stats.function_calls * 321210234Syasuko.eckert@amd.com RFWIN_ACCESS_MULTIPLIER; 321310234Syasuko.eckert@amd.com IRF->rtp_stats.writeAc.access += core_stats.function_calls * 321410234Syasuko.eckert@amd.com RFWIN_ACCESS_MULTIPLIER; 321510234Syasuko.eckert@amd.com } 321610234Syasuko.eckert@amd.com IRF->power_t.reset(); 321710234Syasuko.eckert@amd.com IRF->power_t.readOp.dynamic += IRF->tdp_stats.readAc.access * 321810234Syasuko.eckert@amd.com IRF->local_result.power.readOp.dynamic + 321910234Syasuko.eckert@amd.com IRF->tdp_stats.writeAc.access * 322010234Syasuko.eckert@amd.com IRF->local_result.power.writeOp.dynamic; 322110234Syasuko.eckert@amd.com IRF->rt_power.reset(); 322210234Syasuko.eckert@amd.com IRF->rt_power.readOp.dynamic += 322310234Syasuko.eckert@amd.com IRF->rtp_stats.readAc.access * IRF->local_result.power.readOp.dynamic + 322410234Syasuko.eckert@amd.com IRF->rtp_stats.writeAc.access * IRF->local_result.power.writeOp.dynamic; 322510234Syasuko.eckert@amd.com 322610234Syasuko.eckert@amd.com FRF->tdp_stats.reset(); 322710234Syasuko.eckert@amd.com FRF->tdp_stats.readAc.access = 322810234Syasuko.eckert@amd.com FRF->l_ip.num_rd_ports * core_stats.FPU_duty_cycle * 1.05 * 322910234Syasuko.eckert@amd.com core_params.num_fp_pipelines; 323010234Syasuko.eckert@amd.com FRF->tdp_stats.writeAc.access = 323110234Syasuko.eckert@amd.com FRF->l_ip.num_wr_ports * core_stats.FPU_duty_cycle * 1.05 * 323210234Syasuko.eckert@amd.com core_params.num_fp_pipelines; 323310234Syasuko.eckert@amd.com FRF->rtp_stats.reset(); 323410234Syasuko.eckert@amd.com FRF->rtp_stats.readAc.access = core_stats.float_regfile_reads; 323510234Syasuko.eckert@amd.com FRF->rtp_stats.writeAc.access = core_stats.float_regfile_writes; 323610234Syasuko.eckert@amd.com if (core_params.regWindowing) { 323710234Syasuko.eckert@amd.com FRF->rtp_stats.readAc.access += core_stats.function_calls * 323810234Syasuko.eckert@amd.com RFWIN_ACCESS_MULTIPLIER; 323910234Syasuko.eckert@amd.com FRF->rtp_stats.writeAc.access += core_stats.function_calls * 324010234Syasuko.eckert@amd.com RFWIN_ACCESS_MULTIPLIER; 324110234Syasuko.eckert@amd.com } 324210234Syasuko.eckert@amd.com FRF->power_t.reset(); 324310234Syasuko.eckert@amd.com FRF->power_t.readOp.dynamic += 324410234Syasuko.eckert@amd.com FRF->tdp_stats.readAc.access * FRF->local_result.power.readOp.dynamic + 324510234Syasuko.eckert@amd.com FRF->tdp_stats.writeAc.access * FRF->local_result.power.writeOp.dynamic; 324610234Syasuko.eckert@amd.com FRF->rt_power.reset(); 324710234Syasuko.eckert@amd.com FRF->rt_power.readOp.dynamic += 324810234Syasuko.eckert@amd.com FRF->rtp_stats.readAc.access * FRF->local_result.power.readOp.dynamic + 324910234Syasuko.eckert@amd.com FRF->rtp_stats.writeAc.access * FRF->local_result.power.writeOp.dynamic; 325010234Syasuko.eckert@amd.com 325110234Syasuko.eckert@amd.com if (core_params.regWindowing) { 325210234Syasuko.eckert@amd.com RFWIN->tdp_stats.reset(); 325310234Syasuko.eckert@amd.com RFWIN->tdp_stats.readAc.access = 0; 325410234Syasuko.eckert@amd.com RFWIN->tdp_stats.writeAc.access = 0; 325510234Syasuko.eckert@amd.com RFWIN->rtp_stats.reset(); 325610234Syasuko.eckert@amd.com RFWIN->rtp_stats.readAc.access = 325710234Syasuko.eckert@amd.com core_stats.function_calls * RFWIN_ACCESS_MULTIPLIER; 325810234Syasuko.eckert@amd.com RFWIN->rtp_stats.writeAc.access = 325910234Syasuko.eckert@amd.com core_stats.function_calls * RFWIN_ACCESS_MULTIPLIER; 326010234Syasuko.eckert@amd.com RFWIN->power_t.reset(); 326110234Syasuko.eckert@amd.com RFWIN->power_t.readOp.dynamic += 326210234Syasuko.eckert@amd.com RFWIN->tdp_stats.readAc.access * 326310234Syasuko.eckert@amd.com RFWIN->local_result.power.readOp.dynamic + 326410234Syasuko.eckert@amd.com RFWIN->tdp_stats.writeAc.access * 326510234Syasuko.eckert@amd.com RFWIN->local_result.power.writeOp.dynamic; 326610234Syasuko.eckert@amd.com RFWIN->rt_power.reset(); 326710234Syasuko.eckert@amd.com RFWIN->rt_power.readOp.dynamic += 326810234Syasuko.eckert@amd.com RFWIN->rtp_stats.readAc.access * 326910234Syasuko.eckert@amd.com RFWIN->local_result.power.readOp.dynamic + 327010234Syasuko.eckert@amd.com RFWIN->rtp_stats.writeAc.access * 327110234Syasuko.eckert@amd.com RFWIN->local_result.power.writeOp.dynamic; 327210234Syasuko.eckert@amd.com } 327310234Syasuko.eckert@amd.com 327410234Syasuko.eckert@amd.com output_data.reset(); 327510234Syasuko.eckert@amd.com if (IRF) { 327610234Syasuko.eckert@amd.com IRF->output_data.peak_dynamic_power = 327710234Syasuko.eckert@amd.com IRF->power_t.readOp.dynamic * clockRate; 327810234Syasuko.eckert@amd.com IRF->output_data.subthreshold_leakage_power *= 327910234Syasuko.eckert@amd.com core_params.num_hthreads; 328010234Syasuko.eckert@amd.com IRF->output_data.gate_leakage_power *= core_params.num_hthreads; 328110234Syasuko.eckert@amd.com IRF->output_data.runtime_dynamic_energy = IRF->rt_power.readOp.dynamic; 328210234Syasuko.eckert@amd.com output_data += IRF->output_data; 328310234Syasuko.eckert@amd.com } 328410234Syasuko.eckert@amd.com if (FRF) { 328510234Syasuko.eckert@amd.com FRF->output_data.peak_dynamic_power = 328610234Syasuko.eckert@amd.com FRF->power_t.readOp.dynamic * clockRate; 328710234Syasuko.eckert@amd.com FRF->output_data.subthreshold_leakage_power *= 328810234Syasuko.eckert@amd.com core_params.num_hthreads; 328910234Syasuko.eckert@amd.com FRF->output_data.gate_leakage_power *= core_params.num_hthreads; 329010234Syasuko.eckert@amd.com FRF->output_data.runtime_dynamic_energy = FRF->rt_power.readOp.dynamic; 329110234Syasuko.eckert@amd.com output_data += FRF->output_data; 329210234Syasuko.eckert@amd.com } 329310234Syasuko.eckert@amd.com if (RFWIN) { 329410234Syasuko.eckert@amd.com RFWIN->output_data.peak_dynamic_power = 329510234Syasuko.eckert@amd.com RFWIN->power_t.readOp.dynamic * clockRate; 329610234Syasuko.eckert@amd.com RFWIN->output_data.runtime_dynamic_energy = 329710234Syasuko.eckert@amd.com RFWIN->rt_power.readOp.dynamic; 329810234Syasuko.eckert@amd.com output_data += RFWIN->output_data; 329910234Syasuko.eckert@amd.com } 330010234Syasuko.eckert@amd.com} 330110234Syasuko.eckert@amd.com 330210234Syasuko.eckert@amd.comvoid RegFU::displayData(uint32_t indent, int plevel) { 330310234Syasuko.eckert@amd.com if (!exist) return; 330410234Syasuko.eckert@amd.com 330510234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 330610234Syasuko.eckert@amd.com 330710234Syasuko.eckert@amd.com IRF->displayData(indent + 4, plevel); 330810234Syasuko.eckert@amd.com FRF->displayData(indent + 4, plevel); 330910234Syasuko.eckert@amd.com if (core_params.regWindowing) { 331010234Syasuko.eckert@amd.com RFWIN->displayData(indent + 4, plevel); 331110234Syasuko.eckert@amd.com } 331210234Syasuko.eckert@amd.com} 331310234Syasuko.eckert@amd.com 331410234Syasuko.eckert@amd.comvoid EXECU::computeEnergy() { 331510234Syasuko.eckert@amd.com if (!exist) return; 331610234Syasuko.eckert@amd.com 331710234Syasuko.eckert@amd.com int_bypass->set_params_stats(core_params.execu_int_bypass_ports, 331810234Syasuko.eckert@amd.com core_stats.ALU_cdb_duty_cycle, 331910234Syasuko.eckert@amd.com core_stats.cdb_alu_accesses); 332010234Syasuko.eckert@amd.com 332110234Syasuko.eckert@amd.com intTagBypass->set_params_stats(core_params.execu_int_bypass_ports, 332210234Syasuko.eckert@amd.com core_stats.ALU_cdb_duty_cycle, 332310234Syasuko.eckert@amd.com core_stats.cdb_alu_accesses); 332410234Syasuko.eckert@amd.com 332510234Syasuko.eckert@amd.com if (core_params.num_muls > 0) { 332610234Syasuko.eckert@amd.com int_mul_bypass->set_params_stats(core_params.execu_mul_bypass_ports, 332710234Syasuko.eckert@amd.com core_stats.MUL_cdb_duty_cycle, 332810234Syasuko.eckert@amd.com core_stats.cdb_mul_accesses); 332910234Syasuko.eckert@amd.com 333010234Syasuko.eckert@amd.com intTag_mul_Bypass->set_params_stats(core_params.execu_mul_bypass_ports, 333110234Syasuko.eckert@amd.com core_stats.MUL_cdb_duty_cycle, 333210234Syasuko.eckert@amd.com core_stats.cdb_mul_accesses); 333310234Syasuko.eckert@amd.com } 333410234Syasuko.eckert@amd.com 333510234Syasuko.eckert@amd.com if (core_params.num_fpus > 0) { 333610234Syasuko.eckert@amd.com fp_bypass->set_params_stats(core_params.execu_fp_bypass_ports, 333710234Syasuko.eckert@amd.com core_stats.FPU_cdb_duty_cycle, 333810234Syasuko.eckert@amd.com core_stats.cdb_fpu_accesses); 333910234Syasuko.eckert@amd.com 334010234Syasuko.eckert@amd.com fpTagBypass->set_params_stats(core_params.execu_fp_bypass_ports, 334110234Syasuko.eckert@amd.com core_stats.FPU_cdb_duty_cycle, 334210234Syasuko.eckert@amd.com core_stats.cdb_fpu_accesses); 334310234Syasuko.eckert@amd.com } 334410234Syasuko.eckert@amd.com 334510234Syasuko.eckert@amd.com McPATComponent::computeEnergy(); 334610234Syasuko.eckert@amd.com 334710234Syasuko.eckert@amd.com if (rfu) { 334810234Syasuko.eckert@amd.com rfu->computeEnergy(); 334910234Syasuko.eckert@amd.com output_data += rfu->output_data; 335010234Syasuko.eckert@amd.com } 335110234Syasuko.eckert@amd.com if (scheu) { 335210234Syasuko.eckert@amd.com scheu->computeEnergy(); 335310234Syasuko.eckert@amd.com output_data += scheu->output_data; 335410234Syasuko.eckert@amd.com } 335510234Syasuko.eckert@amd.com if (fp_u) { 335610234Syasuko.eckert@amd.com fp_u->computeEnergy(); 335710234Syasuko.eckert@amd.com output_data += fp_u->output_data; 335810234Syasuko.eckert@amd.com } 335910234Syasuko.eckert@amd.com if (exeu) { 336010234Syasuko.eckert@amd.com exeu->computeEnergy(); 336110234Syasuko.eckert@amd.com output_data += exeu->output_data; 336210234Syasuko.eckert@amd.com } 336310234Syasuko.eckert@amd.com if (mul) { 336410234Syasuko.eckert@amd.com mul->computeEnergy(); 336510234Syasuko.eckert@amd.com output_data += mul->output_data; 336610234Syasuko.eckert@amd.com } 336710234Syasuko.eckert@amd.com} 336810234Syasuko.eckert@amd.com 336910234Syasuko.eckert@amd.comvoid EXECU::displayData(uint32_t indent, int plevel) { 337010234Syasuko.eckert@amd.com if (!exist) return; 337110234Syasuko.eckert@amd.com 337210234Syasuko.eckert@amd.com McPATComponent::displayData(indent, plevel); 337310234Syasuko.eckert@amd.com 337410234Syasuko.eckert@amd.com rfu->displayData(indent + 4, plevel); 337510234Syasuko.eckert@amd.com if (scheu) { 337610234Syasuko.eckert@amd.com scheu->displayData(indent + 4, plevel); 337710234Syasuko.eckert@amd.com } 337810234Syasuko.eckert@amd.com exeu->displayData(indent + 4, plevel); 337910234Syasuko.eckert@amd.com if (core_params.num_fpus > 0) { 338010234Syasuko.eckert@amd.com fp_u->displayData(indent + 4, plevel); 338110234Syasuko.eckert@amd.com } 338210234Syasuko.eckert@amd.com if (core_params.num_muls > 0) { 338310234Syasuko.eckert@amd.com mul->displayData(indent + 4, plevel); 338410234Syasuko.eckert@amd.com } 338510234Syasuko.eckert@amd.com} 338610234Syasuko.eckert@amd.com 338710234Syasuko.eckert@amd.comvoid Core::computeEnergy() { 338810234Syasuko.eckert@amd.com ifu->computeEnergy(); 338910234Syasuko.eckert@amd.com lsu->computeEnergy(); 339010234Syasuko.eckert@amd.com mmu->computeEnergy(); 339110234Syasuko.eckert@amd.com exu->computeEnergy(); 339210234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 339310234Syasuko.eckert@amd.com rnu->computeEnergy(); 339410234Syasuko.eckert@amd.com } 339510234Syasuko.eckert@amd.com 339610234Syasuko.eckert@amd.com output_data.reset(); 339710234Syasuko.eckert@amd.com if (ifu) { 339810234Syasuko.eckert@amd.com output_data += ifu->output_data; 339910234Syasuko.eckert@amd.com } 340010234Syasuko.eckert@amd.com if (lsu) { 340110234Syasuko.eckert@amd.com output_data += lsu->output_data; 340210234Syasuko.eckert@amd.com } 340310234Syasuko.eckert@amd.com if (mmu) { 340410234Syasuko.eckert@amd.com output_data += mmu->output_data; 340510234Syasuko.eckert@amd.com } 340610234Syasuko.eckert@amd.com if (exu) { 340710234Syasuko.eckert@amd.com output_data += exu->output_data; 340810234Syasuko.eckert@amd.com } 340910234Syasuko.eckert@amd.com if (rnu) { 341010234Syasuko.eckert@amd.com output_data += rnu->output_data; 341110234Syasuko.eckert@amd.com } 341210234Syasuko.eckert@amd.com if (corepipe) { 341310234Syasuko.eckert@amd.com output_data += corepipe->output_data; 341410234Syasuko.eckert@amd.com } 341510234Syasuko.eckert@amd.com if (undiffCore) { 341610234Syasuko.eckert@amd.com output_data += undiffCore->output_data; 341710234Syasuko.eckert@amd.com } 341810234Syasuko.eckert@amd.com if (l2cache) { 341910234Syasuko.eckert@amd.com output_data += l2cache->output_data; 342010234Syasuko.eckert@amd.com } 342110234Syasuko.eckert@amd.com} 342210234Syasuko.eckert@amd.com 342310234Syasuko.eckert@amd.comInstFetchU ::~InstFetchU() { 342410234Syasuko.eckert@amd.com 342510234Syasuko.eckert@amd.com if (!exist) return; 342610234Syasuko.eckert@amd.com if (IB) { 342710234Syasuko.eckert@amd.com delete IB; 342810234Syasuko.eckert@amd.com IB = NULL; 342910234Syasuko.eckert@amd.com } 343010234Syasuko.eckert@amd.com if (ID_inst) { 343110234Syasuko.eckert@amd.com delete ID_inst; 343210234Syasuko.eckert@amd.com ID_inst = NULL; 343310234Syasuko.eckert@amd.com } 343410234Syasuko.eckert@amd.com if (ID_operand) { 343510234Syasuko.eckert@amd.com delete ID_operand; 343610234Syasuko.eckert@amd.com ID_operand = NULL; 343710234Syasuko.eckert@amd.com } 343810234Syasuko.eckert@amd.com if (ID_misc) { 343910234Syasuko.eckert@amd.com delete ID_misc; 344010234Syasuko.eckert@amd.com ID_misc = NULL; 344110234Syasuko.eckert@amd.com } 344210234Syasuko.eckert@amd.com if (core_params.predictionW > 0) { 344310234Syasuko.eckert@amd.com if (BTB) { 344410234Syasuko.eckert@amd.com delete BTB; 344510234Syasuko.eckert@amd.com BTB = NULL; 344610152Satgutier@umich.edu } 344710234Syasuko.eckert@amd.com if (BPT) { 344810234Syasuko.eckert@amd.com delete BPT; 344910234Syasuko.eckert@amd.com BPT = NULL; 345010234Syasuko.eckert@amd.com } 345110234Syasuko.eckert@amd.com } 345210234Syasuko.eckert@amd.com if (icache) { 345310234Syasuko.eckert@amd.com delete icache; 345410234Syasuko.eckert@amd.com } 345510152Satgutier@umich.edu} 345610152Satgutier@umich.edu 345710234Syasuko.eckert@amd.comBranchPredictor ::~BranchPredictor() { 345810234Syasuko.eckert@amd.com 345910234Syasuko.eckert@amd.com if (!exist) return; 346010234Syasuko.eckert@amd.com if (globalBPT) { 346110234Syasuko.eckert@amd.com delete globalBPT; 346210234Syasuko.eckert@amd.com globalBPT = NULL; 346310234Syasuko.eckert@amd.com } 346410234Syasuko.eckert@amd.com if (localBPT) { 346510234Syasuko.eckert@amd.com delete localBPT; 346610234Syasuko.eckert@amd.com localBPT = NULL; 346710234Syasuko.eckert@amd.com } 346810234Syasuko.eckert@amd.com if (L1_localBPT) { 346910234Syasuko.eckert@amd.com delete L1_localBPT; 347010234Syasuko.eckert@amd.com L1_localBPT = NULL; 347110234Syasuko.eckert@amd.com } 347210234Syasuko.eckert@amd.com if (L2_localBPT) { 347310234Syasuko.eckert@amd.com delete L2_localBPT; 347410234Syasuko.eckert@amd.com L2_localBPT = NULL; 347510234Syasuko.eckert@amd.com } 347610234Syasuko.eckert@amd.com if (chooser) { 347710234Syasuko.eckert@amd.com delete chooser; 347810234Syasuko.eckert@amd.com chooser = NULL; 347910234Syasuko.eckert@amd.com } 348010234Syasuko.eckert@amd.com if (RAS) { 348110234Syasuko.eckert@amd.com delete RAS; 348210234Syasuko.eckert@amd.com RAS = NULL; 348310234Syasuko.eckert@amd.com } 348410234Syasuko.eckert@amd.com} 348510234Syasuko.eckert@amd.com 348610234Syasuko.eckert@amd.comRENAMINGU ::~RENAMINGU() { 348710234Syasuko.eckert@amd.com 348810234Syasuko.eckert@amd.com if (!exist) return; 348910234Syasuko.eckert@amd.com if (iFRAT) { 349010234Syasuko.eckert@amd.com delete iFRAT; 349110234Syasuko.eckert@amd.com iFRAT = NULL; 349210234Syasuko.eckert@amd.com } 349310234Syasuko.eckert@amd.com if (fFRAT) { 349410234Syasuko.eckert@amd.com delete fFRAT; 349510234Syasuko.eckert@amd.com fFRAT = NULL; 349610234Syasuko.eckert@amd.com } 349710234Syasuko.eckert@amd.com if (iRRAT) { 349810234Syasuko.eckert@amd.com delete iRRAT; 349910234Syasuko.eckert@amd.com iRRAT = NULL; 350010234Syasuko.eckert@amd.com } 350110234Syasuko.eckert@amd.com if (iFRAT) { 350210234Syasuko.eckert@amd.com delete iFRAT; 350310234Syasuko.eckert@amd.com iFRAT = NULL; 350410234Syasuko.eckert@amd.com } 350510234Syasuko.eckert@amd.com if (ifreeL) { 350610234Syasuko.eckert@amd.com delete ifreeL; 350710234Syasuko.eckert@amd.com ifreeL = NULL; 350810234Syasuko.eckert@amd.com } 350910234Syasuko.eckert@amd.com if (ffreeL) { 351010234Syasuko.eckert@amd.com delete ffreeL; 351110234Syasuko.eckert@amd.com ffreeL = NULL; 351210234Syasuko.eckert@amd.com } 351310234Syasuko.eckert@amd.com if (idcl) { 351410234Syasuko.eckert@amd.com delete idcl; 351510234Syasuko.eckert@amd.com idcl = NULL; 351610234Syasuko.eckert@amd.com } 351710234Syasuko.eckert@amd.com if (fdcl) { 351810234Syasuko.eckert@amd.com delete fdcl; 351910234Syasuko.eckert@amd.com fdcl = NULL; 352010234Syasuko.eckert@amd.com } 352110234Syasuko.eckert@amd.com if (RAHT) { 352210234Syasuko.eckert@amd.com delete RAHT; 352310234Syasuko.eckert@amd.com RAHT = NULL; 352410234Syasuko.eckert@amd.com } 352510234Syasuko.eckert@amd.com} 352610234Syasuko.eckert@amd.com 352710234Syasuko.eckert@amd.comLoadStoreU ::~LoadStoreU() { 352810234Syasuko.eckert@amd.com 352910234Syasuko.eckert@amd.com if (!exist) return; 353010234Syasuko.eckert@amd.com if (LSQ) { 353110234Syasuko.eckert@amd.com delete LSQ; 353210234Syasuko.eckert@amd.com LSQ = NULL; 353310234Syasuko.eckert@amd.com } 353410234Syasuko.eckert@amd.com if (dcache) { 353510234Syasuko.eckert@amd.com delete dcache; 353610234Syasuko.eckert@amd.com dcache = NULL; 353710234Syasuko.eckert@amd.com } 353810234Syasuko.eckert@amd.com} 353910234Syasuko.eckert@amd.com 354010234Syasuko.eckert@amd.comMemManU ::~MemManU() { 354110234Syasuko.eckert@amd.com 354210234Syasuko.eckert@amd.com if (!exist) return; 354310234Syasuko.eckert@amd.com if (itlb) { 354410234Syasuko.eckert@amd.com delete itlb; 354510234Syasuko.eckert@amd.com itlb = NULL; 354610234Syasuko.eckert@amd.com } 354710234Syasuko.eckert@amd.com if (dtlb) { 354810234Syasuko.eckert@amd.com delete dtlb; 354910234Syasuko.eckert@amd.com dtlb = NULL; 355010234Syasuko.eckert@amd.com } 355110234Syasuko.eckert@amd.com} 355210234Syasuko.eckert@amd.com 355310234Syasuko.eckert@amd.comRegFU ::~RegFU() { 355410234Syasuko.eckert@amd.com 355510234Syasuko.eckert@amd.com if (!exist) return; 355610234Syasuko.eckert@amd.com if (IRF) { 355710234Syasuko.eckert@amd.com delete IRF; 355810234Syasuko.eckert@amd.com IRF = NULL; 355910234Syasuko.eckert@amd.com } 356010234Syasuko.eckert@amd.com if (FRF) { 356110234Syasuko.eckert@amd.com delete FRF; 356210234Syasuko.eckert@amd.com FRF = NULL; 356310234Syasuko.eckert@amd.com } 356410234Syasuko.eckert@amd.com if (RFWIN) { 356510234Syasuko.eckert@amd.com delete RFWIN; 356610234Syasuko.eckert@amd.com RFWIN = NULL; 356710234Syasuko.eckert@amd.com } 356810234Syasuko.eckert@amd.com} 356910234Syasuko.eckert@amd.com 357010234Syasuko.eckert@amd.comSchedulerU ::~SchedulerU() { 357110234Syasuko.eckert@amd.com 357210234Syasuko.eckert@amd.com if (!exist) return; 357310234Syasuko.eckert@amd.com if (int_inst_window) { 357410234Syasuko.eckert@amd.com delete int_inst_window; 357510234Syasuko.eckert@amd.com int_inst_window = NULL; 357610234Syasuko.eckert@amd.com } 357710234Syasuko.eckert@amd.com if (fp_inst_window) { 357810234Syasuko.eckert@amd.com delete int_inst_window; 357910234Syasuko.eckert@amd.com int_inst_window = NULL; 358010234Syasuko.eckert@amd.com } 358110234Syasuko.eckert@amd.com if (ROB) { 358210234Syasuko.eckert@amd.com delete ROB; 358310234Syasuko.eckert@amd.com ROB = NULL; 358410234Syasuko.eckert@amd.com } 358510234Syasuko.eckert@amd.com if (int_instruction_selection) { 358610234Syasuko.eckert@amd.com delete int_instruction_selection; 358710234Syasuko.eckert@amd.com int_instruction_selection = NULL; 358810234Syasuko.eckert@amd.com } 358910234Syasuko.eckert@amd.com if (fp_instruction_selection) { 359010234Syasuko.eckert@amd.com delete fp_instruction_selection; 359110234Syasuko.eckert@amd.com fp_instruction_selection = NULL; 359210234Syasuko.eckert@amd.com } 359310234Syasuko.eckert@amd.com} 359410234Syasuko.eckert@amd.com 359510234Syasuko.eckert@amd.comEXECU ::~EXECU() { 359610234Syasuko.eckert@amd.com 359710234Syasuko.eckert@amd.com if (!exist) return; 359810234Syasuko.eckert@amd.com if (int_bypass) { 359910234Syasuko.eckert@amd.com delete int_bypass; 360010234Syasuko.eckert@amd.com int_bypass = NULL; 360110234Syasuko.eckert@amd.com } 360210234Syasuko.eckert@amd.com if (intTagBypass) { 360310234Syasuko.eckert@amd.com delete intTagBypass; 360410234Syasuko.eckert@amd.com intTagBypass = NULL; 360510234Syasuko.eckert@amd.com } 360610234Syasuko.eckert@amd.com if (int_mul_bypass) { 360710234Syasuko.eckert@amd.com delete int_mul_bypass; 360810234Syasuko.eckert@amd.com int_mul_bypass = NULL; 360910234Syasuko.eckert@amd.com } 361010234Syasuko.eckert@amd.com if (intTag_mul_Bypass) { 361110234Syasuko.eckert@amd.com delete intTag_mul_Bypass; 361210234Syasuko.eckert@amd.com intTag_mul_Bypass = NULL; 361310234Syasuko.eckert@amd.com } 361410234Syasuko.eckert@amd.com if (fp_bypass) { 361510234Syasuko.eckert@amd.com delete fp_bypass; 361610234Syasuko.eckert@amd.com fp_bypass = NULL; 361710234Syasuko.eckert@amd.com } 361810234Syasuko.eckert@amd.com if (fpTagBypass) { 361910234Syasuko.eckert@amd.com delete fpTagBypass; 362010234Syasuko.eckert@amd.com fpTagBypass = NULL; 362110234Syasuko.eckert@amd.com } 362210234Syasuko.eckert@amd.com if (fp_u) { 362310234Syasuko.eckert@amd.com delete fp_u; 362410234Syasuko.eckert@amd.com fp_u = NULL; 362510234Syasuko.eckert@amd.com } 362610234Syasuko.eckert@amd.com if (exeu) { 362710234Syasuko.eckert@amd.com delete exeu; 362810234Syasuko.eckert@amd.com exeu = NULL; 362910234Syasuko.eckert@amd.com } 363010234Syasuko.eckert@amd.com if (mul) { 363110234Syasuko.eckert@amd.com delete mul; 363210234Syasuko.eckert@amd.com mul = NULL; 363310234Syasuko.eckert@amd.com } 363410234Syasuko.eckert@amd.com if (rfu) { 363510234Syasuko.eckert@amd.com delete rfu; 363610234Syasuko.eckert@amd.com rfu = NULL; 363710234Syasuko.eckert@amd.com } 363810234Syasuko.eckert@amd.com if (scheu) { 363910234Syasuko.eckert@amd.com delete scheu; 364010234Syasuko.eckert@amd.com scheu = NULL; 364110234Syasuko.eckert@amd.com } 364210234Syasuko.eckert@amd.com} 364310234Syasuko.eckert@amd.com 364410234Syasuko.eckert@amd.comCore::~Core() { 364510234Syasuko.eckert@amd.com 364610234Syasuko.eckert@amd.com if (ifu) { 364710234Syasuko.eckert@amd.com delete ifu; 364810234Syasuko.eckert@amd.com ifu = NULL; 364910234Syasuko.eckert@amd.com } 365010234Syasuko.eckert@amd.com if (lsu) { 365110234Syasuko.eckert@amd.com delete lsu; 365210234Syasuko.eckert@amd.com lsu = NULL; 365310234Syasuko.eckert@amd.com } 365410234Syasuko.eckert@amd.com if (rnu) { 365510234Syasuko.eckert@amd.com delete rnu; 365610234Syasuko.eckert@amd.com rnu = NULL; 365710234Syasuko.eckert@amd.com } 365810234Syasuko.eckert@amd.com if (mmu) { 365910234Syasuko.eckert@amd.com delete mmu; 366010234Syasuko.eckert@amd.com mmu = NULL; 366110234Syasuko.eckert@amd.com } 366210234Syasuko.eckert@amd.com if (exu) { 366310234Syasuko.eckert@amd.com delete exu; 366410234Syasuko.eckert@amd.com exu = NULL; 366510234Syasuko.eckert@amd.com } 366610234Syasuko.eckert@amd.com if (corepipe) { 366710234Syasuko.eckert@amd.com delete corepipe; 366810234Syasuko.eckert@amd.com corepipe = NULL; 366910234Syasuko.eckert@amd.com } 367010234Syasuko.eckert@amd.com if (undiffCore) { 367110234Syasuko.eckert@amd.com delete undiffCore; 367210234Syasuko.eckert@amd.com undiffCore = NULL; 367310234Syasuko.eckert@amd.com } 367410234Syasuko.eckert@amd.com if (l2cache) { 367510234Syasuko.eckert@amd.com delete l2cache; 367610234Syasuko.eckert@amd.com l2cache = NULL; 367710234Syasuko.eckert@amd.com } 367810234Syasuko.eckert@amd.com} 367910234Syasuko.eckert@amd.com 368010234Syasuko.eckert@amd.comvoid Core::initialize_params() { 368110234Syasuko.eckert@amd.com memset(&core_params, 0, sizeof(CoreParameters)); 368210234Syasuko.eckert@amd.com core_params.peak_issueW = -1; 368310234Syasuko.eckert@amd.com core_params.peak_commitW = -1; 368410234Syasuko.eckert@amd.com} 368510234Syasuko.eckert@amd.com 368610234Syasuko.eckert@amd.comvoid Core::initialize_stats() { 368710234Syasuko.eckert@amd.com memset(&core_stats, 0, sizeof(CoreStatistics)); 368810234Syasuko.eckert@amd.com core_stats.IFU_duty_cycle = 1.0; 368910234Syasuko.eckert@amd.com core_stats.ALU_duty_cycle = 1.0; 369010234Syasuko.eckert@amd.com core_stats.FPU_duty_cycle = 1.0; 369110234Syasuko.eckert@amd.com core_stats.MUL_duty_cycle = 1.0; 369210234Syasuko.eckert@amd.com core_stats.ALU_cdb_duty_cycle = 1.0; 369310234Syasuko.eckert@amd.com core_stats.FPU_cdb_duty_cycle = 1.0; 369410234Syasuko.eckert@amd.com core_stats.MUL_cdb_duty_cycle = 1.0; 369510234Syasuko.eckert@amd.com core_stats.pipeline_duty_cycle = 1.0; 369610234Syasuko.eckert@amd.com core_stats.IFU_duty_cycle = 1.0; 369710234Syasuko.eckert@amd.com core_stats.LSU_duty_cycle = 1.0; 369810234Syasuko.eckert@amd.com core_stats.MemManU_D_duty_cycle = 1.0; 369910234Syasuko.eckert@amd.com core_stats.MemManU_I_duty_cycle = 1.0; 370010234Syasuko.eckert@amd.com} 370110234Syasuko.eckert@amd.com 370210234Syasuko.eckert@amd.comvoid Core::set_core_param() { 370310234Syasuko.eckert@amd.com initialize_params(); 370410234Syasuko.eckert@amd.com initialize_stats(); 370510234Syasuko.eckert@amd.com 370610234Syasuko.eckert@amd.com int num_children = xml_data->nChildNode("param"); 370710234Syasuko.eckert@amd.com int i; 370810234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 370910234Syasuko.eckert@amd.com XMLNode* paramNode = xml_data->getChildNodePtr("param", &i); 371010234Syasuko.eckert@amd.com XMLCSTR node_name = paramNode->getAttribute("name"); 371110234Syasuko.eckert@amd.com XMLCSTR value = paramNode->getAttribute("value"); 371210234Syasuko.eckert@amd.com 371310234Syasuko.eckert@amd.com if (!node_name) 371410234Syasuko.eckert@amd.com warnMissingParamName(paramNode->getAttribute("id")); 371510234Syasuko.eckert@amd.com 371610234Syasuko.eckert@amd.com ASSIGN_STR_IF("name", name); 371710234Syasuko.eckert@amd.com ASSIGN_INT_IF("opt_local", core_params.opt_local); 371810234Syasuko.eckert@amd.com ASSIGN_FP_IF("clock_rate", core_params.clockRate); 371910234Syasuko.eckert@amd.com ASSIGN_INT_IF("instruction_length", core_params.instruction_length); 372010234Syasuko.eckert@amd.com ASSIGN_INT_IF("opcode_width", core_params.opcode_width); 372110234Syasuko.eckert@amd.com ASSIGN_INT_IF("x86", core_params.x86); 372210234Syasuko.eckert@amd.com ASSIGN_INT_IF("Embedded", core_params.Embedded); 372310234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("machine_type", core_params.core_ty, Core_type); 372410234Syasuko.eckert@amd.com ASSIGN_INT_IF("micro_opcode_width", core_params.micro_opcode_length); 372510234Syasuko.eckert@amd.com ASSIGN_INT_IF("number_hardware_threads", core_params.num_hthreads); 372610234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_width", core_params.fetchW); 372710234Syasuko.eckert@amd.com ASSIGN_INT_IF("decode_width", core_params.decodeW); 372810234Syasuko.eckert@amd.com ASSIGN_INT_IF("issue_width", core_params.issueW); 372910234Syasuko.eckert@amd.com ASSIGN_INT_IF("peak_issue_width", core_params.peak_issueW); 373010234Syasuko.eckert@amd.com ASSIGN_INT_IF("commit_width", core_params.commitW); 373110234Syasuko.eckert@amd.com ASSIGN_INT_IF("prediction_width", core_params.predictionW); 373210234Syasuko.eckert@amd.com ASSIGN_INT_IF("ALU_per_core", core_params.num_alus); 373310234Syasuko.eckert@amd.com ASSIGN_INT_IF("FPU_per_core", core_params.num_fpus); 373410234Syasuko.eckert@amd.com ASSIGN_INT_IF("MUL_per_core", core_params.num_muls); 373510234Syasuko.eckert@amd.com ASSIGN_INT_IF("fp_issue_width", core_params.fp_issueW); 373610234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("instruction_window_scheme", core_params.scheu_ty, 373710234Syasuko.eckert@amd.com Scheduler_type); 373810234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("rename_scheme", core_params.rm_ty, Renaming_type); 373910234Syasuko.eckert@amd.com ASSIGN_INT_IF("archi_Regs_IRF_size", core_params.archi_Regs_IRF_size); 374010234Syasuko.eckert@amd.com ASSIGN_INT_IF("archi_Regs_FRF_size", core_params.archi_Regs_FRF_size); 374110234Syasuko.eckert@amd.com ASSIGN_INT_IF("ROB_size", core_params.ROB_size); 374210234Syasuko.eckert@amd.com ASSIGN_INT_IF("ROB_assoc", core_params.ROB_assoc); 374310234Syasuko.eckert@amd.com ASSIGN_INT_IF("ROB_nbanks", core_params.ROB_nbanks); 374410234Syasuko.eckert@amd.com ASSIGN_INT_IF("ROB_tag_width", core_params.ROB_tag_width); 374510234Syasuko.eckert@amd.com ASSIGN_INT_IF("scheduler_assoc", core_params.scheduler_assoc); 374610234Syasuko.eckert@amd.com ASSIGN_INT_IF("scheduler_nbanks", core_params.scheduler_nbanks); 374710234Syasuko.eckert@amd.com ASSIGN_INT_IF("register_window_size", 374810234Syasuko.eckert@amd.com core_params.register_window_size); 374910234Syasuko.eckert@amd.com ASSIGN_INT_IF("register_window_throughput", 375010234Syasuko.eckert@amd.com core_params.register_window_throughput); 375110234Syasuko.eckert@amd.com ASSIGN_INT_IF("register_window_latency", 375210234Syasuko.eckert@amd.com core_params.register_window_latency); 375310234Syasuko.eckert@amd.com ASSIGN_INT_IF("register_window_assoc", 375410234Syasuko.eckert@amd.com core_params.register_window_assoc); 375510234Syasuko.eckert@amd.com ASSIGN_INT_IF("register_window_nbanks", 375610234Syasuko.eckert@amd.com core_params.register_window_nbanks); 375710234Syasuko.eckert@amd.com ASSIGN_INT_IF("register_window_tag_width", 375810234Syasuko.eckert@amd.com core_params.register_window_tag_width); 375910234Syasuko.eckert@amd.com ASSIGN_INT_IF("register_window_rw_ports", 376010234Syasuko.eckert@amd.com core_params.register_window_rw_ports); 376110234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_IRF_size", core_params.phy_Regs_IRF_size); 376210234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_IRF_assoc", core_params.phy_Regs_IRF_assoc); 376310234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_IRF_nbanks", core_params.phy_Regs_IRF_nbanks); 376410234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_IRF_tag_width", 376510234Syasuko.eckert@amd.com core_params.phy_Regs_IRF_tag_width); 376610234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_IRF_rd_ports", 376710234Syasuko.eckert@amd.com core_params.phy_Regs_IRF_rd_ports); 376810234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_IRF_wr_ports", 376910234Syasuko.eckert@amd.com core_params.phy_Regs_IRF_wr_ports); 377010234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_FRF_size", core_params.phy_Regs_FRF_size); 377110234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_FRF_assoc", core_params.phy_Regs_FRF_assoc); 377210234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_FRF_nbanks", core_params.phy_Regs_FRF_nbanks); 377310234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_FRF_tag_width", 377410234Syasuko.eckert@amd.com core_params.phy_Regs_FRF_tag_width); 377510234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_FRF_rd_ports", 377610234Syasuko.eckert@amd.com core_params.phy_Regs_FRF_rd_ports); 377710234Syasuko.eckert@amd.com ASSIGN_INT_IF("phy_Regs_FRF_wr_ports", 377810234Syasuko.eckert@amd.com core_params.phy_Regs_FRF_wr_ports); 377910234Syasuko.eckert@amd.com ASSIGN_INT_IF("front_rat_nbanks", core_params.front_rat_nbanks); 378010234Syasuko.eckert@amd.com ASSIGN_INT_IF("front_rat_rw_ports", core_params.front_rat_rw_ports); 378110234Syasuko.eckert@amd.com ASSIGN_INT_IF("retire_rat_nbanks", core_params.retire_rat_nbanks); 378210234Syasuko.eckert@amd.com ASSIGN_INT_IF("retire_rat_rw_ports", core_params.retire_rat_rw_ports); 378310234Syasuko.eckert@amd.com ASSIGN_INT_IF("freelist_nbanks", core_params.freelist_nbanks); 378410234Syasuko.eckert@amd.com ASSIGN_INT_IF("freelist_rw_ports", core_params.freelist_rw_ports); 378510234Syasuko.eckert@amd.com ASSIGN_INT_IF("memory_ports", core_params.memory_ports); 378610234Syasuko.eckert@amd.com ASSIGN_INT_IF("load_buffer_size", core_params.load_buffer_size); 378710234Syasuko.eckert@amd.com ASSIGN_INT_IF("load_buffer_assoc", core_params.load_buffer_assoc); 378810234Syasuko.eckert@amd.com ASSIGN_INT_IF("load_buffer_nbanks", core_params.load_buffer_nbanks); 378910234Syasuko.eckert@amd.com ASSIGN_INT_IF("store_buffer_size", core_params.store_buffer_size); 379010234Syasuko.eckert@amd.com ASSIGN_INT_IF("store_buffer_assoc", core_params.store_buffer_assoc); 379110234Syasuko.eckert@amd.com ASSIGN_INT_IF("store_buffer_nbanks", core_params.store_buffer_nbanks); 379210234Syasuko.eckert@amd.com ASSIGN_INT_IF("instruction_window_size", 379310234Syasuko.eckert@amd.com core_params.instruction_window_size); 379410234Syasuko.eckert@amd.com ASSIGN_INT_IF("fp_instruction_window_size", 379510234Syasuko.eckert@amd.com core_params.fp_instruction_window_size); 379610234Syasuko.eckert@amd.com ASSIGN_INT_IF("instruction_buffer_size", 379710234Syasuko.eckert@amd.com core_params.instruction_buffer_size); 379810234Syasuko.eckert@amd.com ASSIGN_INT_IF("instruction_buffer_assoc", 379910234Syasuko.eckert@amd.com core_params.instruction_buffer_assoc); 380010234Syasuko.eckert@amd.com ASSIGN_INT_IF("instruction_buffer_nbanks", 380110234Syasuko.eckert@amd.com core_params.instruction_buffer_nbanks); 380210234Syasuko.eckert@amd.com ASSIGN_INT_IF("instruction_buffer_tag_width", 380310234Syasuko.eckert@amd.com core_params.instruction_buffer_tag_width); 380410234Syasuko.eckert@amd.com ASSIGN_INT_IF("number_instruction_fetch_ports", 380510234Syasuko.eckert@amd.com core_params.number_instruction_fetch_ports); 380610234Syasuko.eckert@amd.com ASSIGN_INT_IF("RAS_size", core_params.RAS_size); 380710234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("execu_broadcast_wt", core_params.execu_broadcast_wt, 380810234Syasuko.eckert@amd.com Wire_type); 380910234Syasuko.eckert@amd.com ASSIGN_INT_IF("execu_wire_mat_type", core_params.execu_wire_mat_type); 381010234Syasuko.eckert@amd.com ASSIGN_INT_IF("execu_int_bypass_ports", 381110234Syasuko.eckert@amd.com core_params.execu_int_bypass_ports); 381210234Syasuko.eckert@amd.com ASSIGN_INT_IF("execu_mul_bypass_ports", 381310234Syasuko.eckert@amd.com core_params.execu_mul_bypass_ports); 381410234Syasuko.eckert@amd.com ASSIGN_INT_IF("execu_fp_bypass_ports", 381510234Syasuko.eckert@amd.com core_params.execu_fp_bypass_ports); 381610234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("execu_bypass_wire_type", 381710234Syasuko.eckert@amd.com core_params.execu_bypass_wire_type, Wire_type); 381810234Syasuko.eckert@amd.com ASSIGN_FP_IF("execu_bypass_base_width", 381910234Syasuko.eckert@amd.com core_params.execu_bypass_base_width); 382010234Syasuko.eckert@amd.com ASSIGN_FP_IF("execu_bypass_base_height", 382110234Syasuko.eckert@amd.com core_params.execu_bypass_base_height); 382210234Syasuko.eckert@amd.com ASSIGN_INT_IF("execu_bypass_start_wiring_level", 382310234Syasuko.eckert@amd.com core_params.execu_bypass_start_wiring_level); 382410234Syasuko.eckert@amd.com ASSIGN_FP_IF("execu_bypass_route_over_perc", 382510234Syasuko.eckert@amd.com core_params.execu_bypass_route_over_perc); 382610234Syasuko.eckert@amd.com ASSIGN_FP_IF("broadcast_numerator", core_params.broadcast_numerator); 382710234Syasuko.eckert@amd.com ASSIGN_INT_IF("int_pipeline_depth", core_params.pipeline_stages); 382810234Syasuko.eckert@amd.com ASSIGN_INT_IF("fp_pipeline_depth", core_params.fp_pipeline_stages); 382910234Syasuko.eckert@amd.com ASSIGN_INT_IF("int_pipelines", core_params.num_pipelines); 383010234Syasuko.eckert@amd.com ASSIGN_INT_IF("fp_pipelines", core_params.num_fp_pipelines); 383110234Syasuko.eckert@amd.com ASSIGN_INT_IF("globalCheckpoint", core_params.globalCheckpoint); 383210234Syasuko.eckert@amd.com ASSIGN_INT_IF("perThreadState", core_params.perThreadState); 383310234Syasuko.eckert@amd.com ASSIGN_INT_IF("instruction_length", core_params.instruction_length); 383410234Syasuko.eckert@amd.com 383510234Syasuko.eckert@amd.com else { 383610234Syasuko.eckert@amd.com warnUnrecognizedParam(node_name); 383710152Satgutier@umich.edu } 383810234Syasuko.eckert@amd.com } 383910234Syasuko.eckert@amd.com 384010234Syasuko.eckert@amd.com // Change from MHz to Hz 384110234Syasuko.eckert@amd.com core_params.clockRate *= 1e6; 384210234Syasuko.eckert@amd.com clockRate = core_params.clockRate; 384310234Syasuko.eckert@amd.com 384410234Syasuko.eckert@amd.com core_params.peak_commitW = core_params.peak_issueW; 384510234Syasuko.eckert@amd.com core_params.fp_decodeW = core_params.fp_issueW; 384610234Syasuko.eckert@amd.com 384710234Syasuko.eckert@amd.com 384810234Syasuko.eckert@amd.com num_children = xml_data->nChildNode("stat"); 384910234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 385010234Syasuko.eckert@amd.com XMLNode* statNode = xml_data->getChildNodePtr("stat", &i); 385110234Syasuko.eckert@amd.com XMLCSTR node_name = statNode->getAttribute("name"); 385210234Syasuko.eckert@amd.com XMLCSTR value = statNode->getAttribute("value"); 385310234Syasuko.eckert@amd.com 385410234Syasuko.eckert@amd.com if (!node_name) 385510234Syasuko.eckert@amd.com warnMissingStatName(statNode->getAttribute("id")); 385610234Syasuko.eckert@amd.com 385710234Syasuko.eckert@amd.com ASSIGN_FP_IF("ALU_duty_cycle", core_stats.ALU_duty_cycle); 385810234Syasuko.eckert@amd.com ASSIGN_FP_IF("FPU_duty_cycle", core_stats.FPU_duty_cycle); 385910234Syasuko.eckert@amd.com ASSIGN_FP_IF("MUL_duty_cycle", core_stats.MUL_duty_cycle); 386010234Syasuko.eckert@amd.com ASSIGN_FP_IF("ALU_cdb_duty_cycle", core_stats.ALU_cdb_duty_cycle); 386110234Syasuko.eckert@amd.com ASSIGN_FP_IF("FPU_cdb_duty_cycle", core_stats.FPU_cdb_duty_cycle); 386210234Syasuko.eckert@amd.com ASSIGN_FP_IF("MUL_cdb_duty_cycle", core_stats.MUL_cdb_duty_cycle); 386310234Syasuko.eckert@amd.com ASSIGN_FP_IF("pipeline_duty_cycle", core_stats.pipeline_duty_cycle); 386410234Syasuko.eckert@amd.com ASSIGN_FP_IF("total_cycles", core_stats.total_cycles); 386510234Syasuko.eckert@amd.com ASSIGN_FP_IF("busy_cycles", core_stats.busy_cycles); 386610234Syasuko.eckert@amd.com ASSIGN_FP_IF("idle_cycles", core_stats.idle_cycles); 386710234Syasuko.eckert@amd.com ASSIGN_FP_IF("IFU_duty_cycle", core_stats.IFU_duty_cycle); 386810234Syasuko.eckert@amd.com ASSIGN_FP_IF("BR_duty_cycle", core_stats.BR_duty_cycle); 386910234Syasuko.eckert@amd.com ASSIGN_FP_IF("LSU_duty_cycle", core_stats.LSU_duty_cycle); 387010234Syasuko.eckert@amd.com ASSIGN_FP_IF("MemManU_D_duty_cycle", core_stats.MemManU_D_duty_cycle); 387110234Syasuko.eckert@amd.com ASSIGN_FP_IF("MemManU_I_duty_cycle", core_stats.MemManU_I_duty_cycle); 387210234Syasuko.eckert@amd.com ASSIGN_FP_IF("cdb_fpu_accesses", core_stats.cdb_fpu_accesses); 387310234Syasuko.eckert@amd.com ASSIGN_FP_IF("cdb_alu_accesses", core_stats.cdb_alu_accesses); 387410234Syasuko.eckert@amd.com ASSIGN_FP_IF("cdb_mul_accesses", core_stats.cdb_mul_accesses); 387510234Syasuko.eckert@amd.com ASSIGN_FP_IF("function_calls", core_stats.function_calls); 387610234Syasuko.eckert@amd.com ASSIGN_FP_IF("total_instructions", core_stats.total_instructions); 387710234Syasuko.eckert@amd.com ASSIGN_FP_IF("int_instructions", core_stats.int_instructions); 387810234Syasuko.eckert@amd.com ASSIGN_FP_IF("fp_instructions", core_stats.fp_instructions); 387910234Syasuko.eckert@amd.com ASSIGN_FP_IF("branch_instructions", core_stats.branch_instructions); 388010234Syasuko.eckert@amd.com ASSIGN_FP_IF("branch_mispredictions", 388110234Syasuko.eckert@amd.com core_stats.branch_mispredictions); 388210234Syasuko.eckert@amd.com ASSIGN_FP_IF("load_instructions", core_stats.load_instructions); 388310234Syasuko.eckert@amd.com ASSIGN_FP_IF("store_instructions", core_stats.store_instructions); 388410234Syasuko.eckert@amd.com ASSIGN_FP_IF("committed_instructions", 388510234Syasuko.eckert@amd.com core_stats.committed_instructions); 388610234Syasuko.eckert@amd.com ASSIGN_FP_IF("committed_int_instructions", 388710234Syasuko.eckert@amd.com core_stats.committed_int_instructions); 388810234Syasuko.eckert@amd.com ASSIGN_FP_IF("committed_fp_instructions", 388910234Syasuko.eckert@amd.com core_stats.committed_fp_instructions); 389010234Syasuko.eckert@amd.com ASSIGN_FP_IF("ROB_reads", core_stats.ROB_reads); 389110234Syasuko.eckert@amd.com ASSIGN_FP_IF("ROB_writes", core_stats.ROB_writes); 389210234Syasuko.eckert@amd.com ASSIGN_FP_IF("rename_reads", core_stats.rename_reads); 389310234Syasuko.eckert@amd.com ASSIGN_FP_IF("rename_writes", core_stats.rename_writes); 389410234Syasuko.eckert@amd.com ASSIGN_FP_IF("fp_rename_reads", core_stats.fp_rename_reads); 389510234Syasuko.eckert@amd.com ASSIGN_FP_IF("fp_rename_writes", core_stats.fp_rename_writes); 389610234Syasuko.eckert@amd.com ASSIGN_FP_IF("inst_window_reads", core_stats.inst_window_reads); 389710234Syasuko.eckert@amd.com ASSIGN_FP_IF("inst_window_writes", core_stats.inst_window_writes); 389810234Syasuko.eckert@amd.com ASSIGN_FP_IF("inst_window_wakeup_accesses", 389910234Syasuko.eckert@amd.com core_stats.inst_window_wakeup_accesses); 390010234Syasuko.eckert@amd.com ASSIGN_FP_IF("fp_inst_window_reads", core_stats.fp_inst_window_reads); 390110234Syasuko.eckert@amd.com ASSIGN_FP_IF("fp_inst_window_writes", 390210234Syasuko.eckert@amd.com core_stats.fp_inst_window_writes); 390310234Syasuko.eckert@amd.com ASSIGN_FP_IF("fp_inst_window_wakeup_accesses", 390410234Syasuko.eckert@amd.com core_stats.fp_inst_window_wakeup_accesses); 390510234Syasuko.eckert@amd.com ASSIGN_FP_IF("int_regfile_reads", core_stats.int_regfile_reads); 390610234Syasuko.eckert@amd.com ASSIGN_FP_IF("float_regfile_reads", core_stats.float_regfile_reads); 390710234Syasuko.eckert@amd.com ASSIGN_FP_IF("int_regfile_writes", core_stats.int_regfile_writes); 390810234Syasuko.eckert@amd.com ASSIGN_FP_IF("float_regfile_writes", core_stats.float_regfile_writes); 390910234Syasuko.eckert@amd.com ASSIGN_FP_IF("context_switches", core_stats.context_switches); 391010234Syasuko.eckert@amd.com ASSIGN_FP_IF("ialu_accesses", core_stats.ialu_accesses); 391110234Syasuko.eckert@amd.com ASSIGN_FP_IF("fpu_accesses", core_stats.fpu_accesses); 391210234Syasuko.eckert@amd.com ASSIGN_FP_IF("mul_accesses", core_stats.mul_accesses); 391310234Syasuko.eckert@amd.com 391410234Syasuko.eckert@amd.com else { 391510234Syasuko.eckert@amd.com warnUnrecognizedStat(node_name); 391610152Satgutier@umich.edu } 391710234Syasuko.eckert@amd.com } 391810234Syasuko.eckert@amd.com 391910234Syasuko.eckert@amd.com // Initialize a few variables 392010234Syasuko.eckert@amd.com core_params.multithreaded = core_params.num_hthreads > 1 ? true : false; 392110234Syasuko.eckert@amd.com core_params.pc_width = virtual_address_width; 392210234Syasuko.eckert@amd.com core_params.v_address_width = virtual_address_width; 392310234Syasuko.eckert@amd.com core_params.p_address_width = physical_address_width; 392410234Syasuko.eckert@amd.com core_params.int_data_width = int(ceil(data_path_width / 32.0)) * 32; 392510234Syasuko.eckert@amd.com core_params.fp_data_width = core_params.int_data_width; 392610234Syasuko.eckert@amd.com core_params.arch_ireg_width = 392710234Syasuko.eckert@amd.com int(ceil(log2(core_params.archi_Regs_IRF_size))); 392810234Syasuko.eckert@amd.com core_params.arch_freg_width 392910234Syasuko.eckert@amd.com = int(ceil(log2(core_params.archi_Regs_FRF_size))); 393010234Syasuko.eckert@amd.com core_params.num_IRF_entry = core_params.archi_Regs_IRF_size; 393110234Syasuko.eckert@amd.com core_params.num_FRF_entry = core_params.archi_Regs_FRF_size; 393210234Syasuko.eckert@amd.com 393310234Syasuko.eckert@amd.com if (core_params.instruction_length <= 0) { 393410234Syasuko.eckert@amd.com errorNonPositiveParam("instruction_length"); 393510234Syasuko.eckert@amd.com } 393610234Syasuko.eckert@amd.com 393710234Syasuko.eckert@amd.com if (core_params.num_hthreads <= 0) { 393810234Syasuko.eckert@amd.com errorNonPositiveParam("number_hardware_threads"); 393910234Syasuko.eckert@amd.com } 394010234Syasuko.eckert@amd.com 394110234Syasuko.eckert@amd.com if (core_params.opcode_width <= 0) { 394210234Syasuko.eckert@amd.com errorNonPositiveParam("opcode_width"); 394310234Syasuko.eckert@amd.com } 394410234Syasuko.eckert@amd.com 394510234Syasuko.eckert@amd.com if (core_params.instruction_buffer_size <= 0) { 394610234Syasuko.eckert@amd.com errorNonPositiveParam("instruction_buffer_size"); 394710234Syasuko.eckert@amd.com } 394810234Syasuko.eckert@amd.com 394910234Syasuko.eckert@amd.com if (core_params.number_instruction_fetch_ports <= 0) { 395010234Syasuko.eckert@amd.com errorNonPositiveParam("number_instruction_fetch_ports"); 395110234Syasuko.eckert@amd.com } 395210234Syasuko.eckert@amd.com 395310234Syasuko.eckert@amd.com if (core_params.peak_issueW <= 0) { 395410234Syasuko.eckert@amd.com errorNonPositiveParam("peak_issue_width"); 395510234Syasuko.eckert@amd.com } else { 395610234Syasuko.eckert@amd.com assert(core_params.peak_commitW > 0); 395710234Syasuko.eckert@amd.com } 395810234Syasuko.eckert@amd.com 395910234Syasuko.eckert@amd.com if (core_params.core_ty == OOO) { 396010234Syasuko.eckert@amd.com if (core_params.scheu_ty == PhysicalRegFile) { 396110234Syasuko.eckert@amd.com core_params.phy_ireg_width = 396210234Syasuko.eckert@amd.com int(ceil(log2(core_params.phy_Regs_IRF_size))); 396310234Syasuko.eckert@amd.com core_params.phy_freg_width = 396410234Syasuko.eckert@amd.com int(ceil(log2(core_params.phy_Regs_FRF_size))); 396510234Syasuko.eckert@amd.com core_params.num_ifreelist_entries = 396610234Syasuko.eckert@amd.com core_params.num_IRF_entry = core_params.phy_Regs_IRF_size; 396710234Syasuko.eckert@amd.com core_params.num_ffreelist_entries = 396810234Syasuko.eckert@amd.com core_params.num_FRF_entry = core_params.phy_Regs_FRF_size; 396910234Syasuko.eckert@amd.com } else if (core_params.scheu_ty == ReservationStation) { 397010234Syasuko.eckert@amd.com core_params.phy_ireg_width = int(ceil(log2(core_params.ROB_size))); 397110234Syasuko.eckert@amd.com core_params.phy_freg_width = int(ceil(log2(core_params.ROB_size))); 397210234Syasuko.eckert@amd.com core_params.num_ifreelist_entries = core_params.ROB_size; 397310234Syasuko.eckert@amd.com core_params.num_ffreelist_entries = core_params.ROB_size; 397410234Syasuko.eckert@amd.com } 397510234Syasuko.eckert@amd.com } 397610234Syasuko.eckert@amd.com 397710234Syasuko.eckert@amd.com core_params.regWindowing = 397810234Syasuko.eckert@amd.com (core_params.register_window_size > 0 && 397910234Syasuko.eckert@amd.com core_params.core_ty == Inorder) ? true : false; 398010234Syasuko.eckert@amd.com 398110234Syasuko.eckert@amd.com if (core_params.regWindowing) { 398210234Syasuko.eckert@amd.com if (core_params.register_window_throughput <= 0) { 398310234Syasuko.eckert@amd.com errorNonPositiveParam("register_window_throughput"); 398410234Syasuko.eckert@amd.com } else if (core_params.register_window_latency <= 0) { 398510234Syasuko.eckert@amd.com errorNonPositiveParam("register_window_latency"); 398610234Syasuko.eckert@amd.com } 398710234Syasuko.eckert@amd.com } 398810234Syasuko.eckert@amd.com 398910234Syasuko.eckert@amd.com set_pppm(core_params.pppm_lkg_multhread, 0, core_params.num_hthreads, 399010234Syasuko.eckert@amd.com core_params.num_hthreads, 0); 399110234Syasuko.eckert@amd.com 399210234Syasuko.eckert@amd.com if (!((core_params.core_ty == OOO) || (core_params.core_ty == Inorder))) { 399310234Syasuko.eckert@amd.com cout << "Invalid Core Type" << endl; 399410234Syasuko.eckert@amd.com exit(0); 399510234Syasuko.eckert@amd.com } 399610234Syasuko.eckert@amd.com 399710234Syasuko.eckert@amd.com if (!((core_params.scheu_ty == PhysicalRegFile) || 399810234Syasuko.eckert@amd.com (core_params.scheu_ty == ReservationStation))) { 399910234Syasuko.eckert@amd.com cout << "Invalid OOO Scheduler Type" << endl; 400010234Syasuko.eckert@amd.com exit(0); 400110234Syasuko.eckert@amd.com } 400210234Syasuko.eckert@amd.com 400310234Syasuko.eckert@amd.com if (!((core_params.rm_ty == RAMbased) || 400410234Syasuko.eckert@amd.com (core_params.rm_ty == CAMbased))) { 400510234Syasuko.eckert@amd.com cout << "Invalid OOO Renaming Type" << endl; 400610234Syasuko.eckert@amd.com exit(0); 400710234Syasuko.eckert@amd.com } 400810152Satgutier@umich.edu 400910152Satgutier@umich.edu} 4010