1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Author: Brad Beckmann
29 *
30 */
31
32#include "mem/ruby/structures/BankedArray.hh"
33
34#include "base/intmath.hh"
35#include "mem/ruby/system/RubySystem.hh"
36
37BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
38                         unsigned int startIndexBit, RubySystem *rs)
39    : m_ruby_system(rs)
40{
41    this->banks = banks;
42    this->accessLatency = accessLatency;
43    this->startIndexBit = startIndexBit;
44
45    if (banks != 0) {
46        bankBits = floorLog2(banks);
47    }
48
49    busyBanks.resize(banks);
50}
51
52bool
53BankedArray::tryAccess(int64_t idx)
54{
55    if (accessLatency == 0)
56        return true;
57
58    unsigned int bank = mapIndexToBank(idx);
59    assert(bank < banks);
60
61    if (busyBanks[bank].endAccess >= curTick()) {
62            return false;
63    }
64
65    return true;
66}
67
68void
69BankedArray::reserve(int64_t idx)
70{
71    if (accessLatency == 0)
72        return;
73
74    unsigned int bank = mapIndexToBank(idx);
75    assert(bank < banks);
76
77    if (busyBanks[bank].endAccess >= curTick()) {
78        if (busyBanks[bank].startAccess == curTick() &&
79             busyBanks[bank].idx == idx) {
80            // this is the same reservation (can happen when
81            // e.g., reserve the same resource for read and write)
82            return; // OK
83        } else {
84            panic("BankedArray reservation error");
85        }
86    }
87
88    busyBanks[bank].idx = idx;
89    busyBanks[bank].startAccess = curTick();
90    busyBanks[bank].endAccess = curTick() +
91        (accessLatency-1) * m_ruby_system->clockPeriod();
92}
93
94unsigned int
95BankedArray::mapIndexToBank(int64_t idx)
96{
97    if (banks == 1) {
98        return 0;
99    }
100    return idx % banks;
101}
102