| /gem5/ext/systemc/src/sysc/qt/md/ |
| H A D | axp_b.s | 72 $L2:
86 bgt $16,$L2
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| H A D | mips_b.s | 63 $L2:
76 bgtz $4,$L2
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| H A D | vax_b.s | 58 L2: label
71 bgtr L2
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| H A D | sparc_b.s | 70 L2: label
83 bg L2
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| H A D | m88k_b.s | 60 L2: label
83 bcnd.n gt0,r2,L2
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| H A D | powerpc_mach_b.s | 145 L2: label
155 blt L2
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| H A D | powerpc_sys5_b.s | 145 L2: label
155 blt L2
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| /gem5/configs/common/ |
| H A D | GPUTLBConfig.py | 104 L2 = [{'name': 'l2', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
107 TLB_hierarchy = [L1, L2, L3]
192 # L1 <-> L2
201 # L2 <-> L3
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| /gem5/util/statetrace/arch/sparc/ |
| H A D | tracechild.hh | 57 L0, L1, L2, L3, L4, L5, L6, L7, enumerator in enum:SparcTraceChild::RegNum
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| H A D | tracechild.cc | 101 case SparcTraceChild::L2: return locals[2];
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| /gem5/configs/example/arm/ |
| H A D | fs_bigLITTLE.py | 89 devices.WalkCache, devices.L2 ]
97 devices.WalkCache, devices.L2 ]
105 ex5_big.WalkCache, ex5_big.L2 ]
113 ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, ex5_LITTLE.L2 ]
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| H A D | starter_fs.py | 79 devices.L2),
143 # clusters have core-private L1 caches and an L2 that's shared
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| H A D | starter_se.py | 73 devices.L2),
111 # private L1 caches and a shared L2 cache.
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| H A D | devices.py | 84 class L2(L2Cache): class in inherits:L2Cache
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| /gem5/configs/common/cores/arm/ |
| H A D | ex5_LITTLE.py | 106 # Consider the L2 a victim cache also for clean lines
123 # Use a cache as a L2 TLB
137 # L2 Cache
138 class L2(Cache): class in inherits:Cache
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| H A D | ex5_big.py | 157 # Consider the L2 a victim cache also for clean lines
175 # Use a cache as a L2 TLB
189 # L2 Cache
190 class L2(Cache): class in inherits:Cache
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| /gem5/configs/splash2/ |
| H A D | run.py | 168 # Base L2 Cache Definition
171 class L2(Cache): class in inherits:Cache
204 system.l2 = L2(size = options.l2size, assoc = 8)
207 # Connect the L2 cache and memory together
216 # Connect the L2 cache and clusters together
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| H A D | cluster.py | 147 # Base L2 Cache Definition
150 class L2(Cache): class in inherits:Cache
219 system.l2 = L2(size = options.l2size, assoc = 8)
222 # Connect the L2 cache and memory together
230 # Connect the L2 cache and clusters together
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| /gem5/src/arch/arm/ |
| H A D | table_walker.cc | 150 stateQueues[L2].empty() && stateQueues[L3].empty() &&
576 start_lookup_level = currState->vtcr.sl0 ? L1 : L2;
626 start_lookup_level = L2;
650 start_lookup_level = L2;
775 L2, L3, L3, __, // sl0 == 0
776 L1, L2, L2, __, // sl0 == 1, etc.
1525 currState->l1Desc.domain(), L2);
1710 case L2:
1743 DPRINTF(TLB, "L2 descripto
[all...] |
| H A D | table_walker.hh | 192 /** Address of L2 descriptor if it exists */
259 lookupLevel = L2;
265 lookupLevel = L2;
275 return "Inserting L2 Descriptor into TLB\n";
437 return lookupLevel == L2 ? Block : Invalid;
523 else // lookupLevel == L2
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| H A D | pagetable.hh | 80 L2, enumerator in enum:ArmISA::LookupLevel
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| /gem5/ext/mcpat/ |
| H A D | basic_components.h | 78 L2, enumerator in enum:CacheLevel
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| H A D | cacheunit.cc | 576 cache_params.cache_level = L2;
|