1/***************************************************************************** 2 * McPAT 3 * SOFTWARE LICENSE AGREEMENT 4 * Copyright 2012 Hewlett-Packard Development Company, L.P. 5 * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 6 * All Rights Reserved 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer; 12 * redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution; 15 * neither the name of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 ***************************************************************************/ 32 33#ifndef BASIC_COMPONENTS_H_ 34#define BASIC_COMPONENTS_H_ 35 36#include <vector> 37 38#include "component.h" 39#include "parameter.h" 40#include "xmlParser.h" 41 42/** 43 * TODO: Since revisions to McPAT aim to make the component hierarchy more 44 * modular, many of the parameter and statistics classes/structs included in 45 * this file should be moved to the files for their respective components. 46 */ 47const double cdb_overhead = 1.1; 48 49enum FU_type { 50 FPU, 51 ALU, 52 MUL 53}; 54 55enum Core_type { 56 OOO, 57 Inorder 58}; 59 60enum Renaming_type { 61 RAMbased, 62 CAMbased 63}; 64 65enum Scheduler_type { 66 PhysicalRegFile, 67 ReservationStation 68}; 69 70enum Cache_type { 71 DATA_CACHE, 72 INSTRUCTION_CACHE, 73 MIXED 74}; 75 76enum CacheLevel { 77 L1, 78 L2, 79 L3, 80 L1Directory, 81 L2Directory 82}; 83 84enum MemoryCtrl_type { 85 MC, //memory controller 86 FLASHC //flash controller 87}; 88 89enum Dir_type { 90 ST,//shadowed tag 91 DC,//directory cache 92 SBT,//static bank tag 93 NonDir 94 95}; 96 97enum Cache_policy { 98 Write_through, 99 Write_back 100}; 101 102enum Device_ty { 103 Core_device, 104 Uncore_device, 105 LLC_device 106}; 107 108enum Access_mode { 109 Normal, 110 Sequential, 111 Fast 112}; 113 114class statsComponents { 115public: 116 double access; 117 double hit; 118 double miss; 119 120 statsComponents() : access(0), hit(0), miss(0) {} 121 statsComponents(const statsComponents & obj) { 122 *this = obj; 123 } 124 statsComponents & operator=(const statsComponents & rhs) { 125 access = rhs.access; 126 hit = rhs.hit; 127 miss = rhs.miss; 128 return *this; 129 } 130 void reset() { 131 access = 0; 132 hit = 0; 133 miss = 0; 134 } 135 136 friend statsComponents operator+(const statsComponents & x, 137 const statsComponents & y); 138 friend statsComponents operator*(const statsComponents & x, 139 double const * const y); 140}; 141 142class statsDef { 143public: 144 statsComponents readAc; 145 statsComponents writeAc; 146 statsComponents searchAc; 147 statsComponents dataReadAc; 148 statsComponents dataWriteAc; 149 statsComponents tagReadAc; 150 statsComponents tagWriteAc; 151 152 statsDef() : readAc(), writeAc(), searchAc() { } 153 void reset() { 154 readAc.reset(); 155 writeAc.reset(); 156 searchAc.reset(); 157 } 158 159 friend statsDef operator+(const statsDef & x, const statsDef & y); 160 friend statsDef operator*(const statsDef & x, double const * const y); 161}; 162 163/** 164 * An object to store the computed data that will be output from McPAT on a 165 * per-component-instance basis. Currently, this includes the amount of storage 166 * that the component comprises, its chip area, and power and energy 167 * calculations. 168 */ 169class McPATOutput { 170public: 171 // Storage is in bytes (B) 172 double storage; 173 // Area is in mm^2 174 double area; 175 // Peak Dynamic Power is in W 176 double peak_dynamic_power; 177 // Subthreshold Leakage Power is in W 178 double subthreshold_leakage_power; 179 // Gate Leakage Power is in W 180 double gate_leakage_power; 181 // Runtime Dynamic Energy is in J 182 double runtime_dynamic_energy; 183 184 void reset(); 185 186 friend McPATOutput operator+(const McPATOutput &lhs, const McPATOutput &rhs); 187 void operator+=(const McPATOutput &rhs); 188}; 189 190/** 191 * A McPATComponent encompasses all the parts that are common to any component 192 * for which McPAT may compute and print power, area, and timing data. It 193 * includes a pointer to the XML data from which the component gathers its 194 * input parameters, it stores the variables that are commonly used in all 195 * components, and it maintains the hierarchical structure to recursively 196 * compute and print output. This is a base class from which all components 197 * should inherit these functionality (possibly through other descended 198 * classes. 199*/ 200class McPATComponent : public Component { 201public: 202 static bool debug; 203 204 // Variables shared across the system by all McPATComponents 205 static bool opt_for_clk; 206 static int longer_channel_device; 207 static double execution_time; 208 static int physical_address_width; 209 static int virtual_address_width; 210 static int virtual_memory_page_size; 211 static int data_path_width; 212 213 // Although these two variables are static right now, they need to be 214 // modulated on a per-frequency-domain basis eventually. 215 static double target_core_clockrate; 216 static double total_cycles; 217 218 XMLNode* xml_data; 219 InputParameter interface_ip; 220 string name; 221 // Number of cycles per second (consider changing name) 222 double clockRate; 223 vector<McPATComponent*> children; 224 // The data structure that is printed in displayData 225 McPATOutput output_data; 226 // Set this to contain the stats to calculate peak dynamic power 227 statsDef tdp_stats; 228 // Set this to contain the stats to calculate runtime dynamic energy/power 229 statsDef rtp_stats; 230 // Holds the peak dynamic power calculation 231 powerDef power_t; 232 // Holds the runtime dynamic power calculation 233 powerDef rt_power; 234 235 McPATComponent(); 236 // Which of these is a better way of doing things?! 237 McPATComponent(XMLNode* _xml_data); 238 McPATComponent(XMLNode* _xml_data, InputParameter* _interface_ip); 239 virtual void recursiveInstantiate(); 240 virtual void computeArea(); 241 // This function should probably be pure virtual, but it's too early in 242 // the modifying process to know for sure. Note that each component has 243 // to calculate it's own power consumption 244 virtual void computeEnergy(); 245 virtual void displayData(uint32_t indent, int plevel); 246 ~McPATComponent(); 247 248 protected: 249 void errorUnspecifiedParam(string param); 250 void errorNonPositiveParam(string param); 251 void warnUnrecognizedComponent(XMLCSTR component); 252 void warnUnrecognizedParam(XMLCSTR param); 253 void warnUnrecognizedStat(XMLCSTR stat); 254 void warnIncompleteComponentType(XMLCSTR type); 255 void warnMissingComponentType(XMLCSTR id); 256 void warnMissingParamName(XMLCSTR id); 257 void warnMissingStatName(XMLCSTR id); 258}; 259 260double longer_channel_device_reduction( 261 enum Device_ty device_ty = Core_device, 262 enum Core_type core_ty = Inorder); 263 264class CoreParameters { 265public: 266 bool opt_local; 267 bool x86; 268 bool Embedded; 269 enum Core_type core_ty; 270 enum Renaming_type rm_ty; 271 enum Scheduler_type scheu_ty; 272 double clockRate; 273 int arch_ireg_width; 274 int arch_freg_width; 275 int archi_Regs_IRF_size; 276 int archi_Regs_FRF_size; 277 int phy_ireg_width; 278 int phy_freg_width; 279 int num_IRF_entry; 280 int num_FRF_entry; 281 int num_ifreelist_entries; 282 int num_ffreelist_entries; 283 int fetchW; 284 int decodeW; 285 int issueW; 286 int peak_issueW; 287 int commitW; 288 int peak_commitW; 289 int predictionW; 290 int fp_issueW; 291 int fp_decodeW; 292 int perThreadState; 293 int globalCheckpoint; 294 int instruction_length; 295 int pc_width; 296 int opcode_width; 297 int micro_opcode_length; 298 int num_hthreads; 299 int pipeline_stages; 300 int fp_pipeline_stages; 301 int num_pipelines; 302 int num_fp_pipelines; 303 int num_alus; 304 int num_muls; 305 double num_fpus; 306 int int_data_width; 307 int fp_data_width; 308 int v_address_width; 309 int p_address_width; 310 bool regWindowing; 311 bool multithreaded; 312 double pppm_lkg_multhread[4]; 313 int ROB_size; 314 int ROB_assoc; 315 int ROB_nbanks; 316 int ROB_tag_width; 317 int scheduler_assoc; 318 int scheduler_nbanks; 319 int register_window_size; 320 double register_window_throughput; 321 double register_window_latency; 322 int register_window_assoc; 323 int register_window_nbanks; 324 int register_window_tag_width; 325 int register_window_rw_ports; 326 int phy_Regs_IRF_size; 327 int phy_Regs_IRF_assoc; 328 int phy_Regs_IRF_nbanks; 329 int phy_Regs_IRF_tag_width; 330 int phy_Regs_IRF_rd_ports; 331 int phy_Regs_IRF_wr_ports; 332 int phy_Regs_FRF_size; 333 int phy_Regs_FRF_assoc; 334 int phy_Regs_FRF_nbanks; 335 int phy_Regs_FRF_tag_width; 336 int phy_Regs_FRF_rd_ports; 337 int phy_Regs_FRF_wr_ports; 338 int front_rat_nbanks; 339 int front_rat_rw_ports; 340 int retire_rat_nbanks; 341 int retire_rat_rw_ports; 342 int freelist_nbanks; 343 int freelist_rw_ports; 344 int memory_ports; 345 int load_buffer_size; 346 int load_buffer_assoc; 347 int load_buffer_nbanks; 348 int store_buffer_size; 349 int store_buffer_assoc; 350 int store_buffer_nbanks; 351 int instruction_window_size; 352 int fp_instruction_window_size; 353 int instruction_buffer_size; 354 int instruction_buffer_assoc; 355 int instruction_buffer_nbanks; 356 int instruction_buffer_tag_width; 357 int number_instruction_fetch_ports; 358 int RAS_size; 359 int execu_int_bypass_ports; 360 int execu_mul_bypass_ports; 361 int execu_fp_bypass_ports; 362 Wire_type execu_bypass_wire_type; 363 Wire_type execu_broadcast_wt; 364 int execu_wire_mat_type; 365 double execu_bypass_base_width; 366 double execu_bypass_base_height; 367 int execu_bypass_start_wiring_level; 368 double execu_bypass_route_over_perc; 369 double broadcast_numerator; 370}; 371 372class CoreStatistics { 373public: 374 double pipeline_duty_cycle; 375 double total_cycles; 376 double busy_cycles; 377 double idle_cycles; 378 double IFU_duty_cycle; 379 double BR_duty_cycle; 380 double LSU_duty_cycle; 381 double MemManU_I_duty_cycle; 382 double MemManU_D_duty_cycle; 383 double ALU_duty_cycle; 384 double MUL_duty_cycle; 385 double FPU_duty_cycle; 386 double ALU_cdb_duty_cycle; 387 double MUL_cdb_duty_cycle; 388 double FPU_cdb_duty_cycle; 389 double ROB_reads; 390 double ROB_writes; 391 double total_instructions; 392 double int_instructions; 393 double fp_instructions; 394 double branch_instructions; 395 double branch_mispredictions; 396 double load_instructions; 397 double store_instructions; 398 double committed_instructions; 399 double committed_int_instructions; 400 double committed_fp_instructions; 401 double rename_reads; 402 double rename_writes; 403 double fp_rename_reads; 404 double fp_rename_writes; 405 double inst_window_reads; 406 double inst_window_writes; 407 double inst_window_wakeup_accesses; 408 double fp_inst_window_reads; 409 double fp_inst_window_writes; 410 double fp_inst_window_wakeup_accesses; 411 double int_regfile_reads; 412 double float_regfile_reads; 413 double int_regfile_writes; 414 double float_regfile_writes; 415 double context_switches; 416 double ialu_accesses; 417 double fpu_accesses; 418 double mul_accesses; 419 double cdb_alu_accesses; 420 double cdb_fpu_accesses; 421 double cdb_mul_accesses; 422 double function_calls; 423}; 424 425class MCParameters { 426public: 427 double clockRate; 428 enum MemoryCtrl_type mc_type; 429 double num_mcs; 430 int num_channels; 431 int llcBlockSize; 432 int dataBusWidth; 433 int databus_width; 434 int llc_line_length; 435 int req_window_size_per_channel; 436 int IO_buffer_size_per_channel; 437 int addressbus_width; 438 int opcodeW; 439 int type; 440 bool LVDS; 441 bool withPHY; 442 int peak_transfer_rate; 443 int number_ranks; 444 int reorder_buffer_assoc; 445 int reorder_buffer_nbanks; 446 int read_buffer_assoc; 447 int read_buffer_nbanks; 448 int read_buffer_tag_width; 449 int write_buffer_assoc; 450 int write_buffer_nbanks; 451 int write_buffer_tag_width; 452}; 453 454class MCStatistics { 455public: 456 double duty_cycle; 457 double perc_load; 458 double reads; 459 double writes; 460}; 461 462class NIUParameters { 463 public: 464 double clockRate; 465 int num_units; 466 int type; 467}; 468 469class NIUStatistics { 470 public: 471 double duty_cycle; 472 double perc_load; 473}; 474 475class PCIeParameters { 476 public: 477 double clockRate; 478 int num_channels; 479 int num_units; 480 bool withPHY; 481 int type; 482}; 483 484class PCIeStatistics { 485 public: 486 double duty_cycle; 487 double perc_load; 488}; 489#endif /* BASIC_COMPONENTS_H_ */ 490