/gem5/src/mem/ |
H A D | AbstractMemory.py | 53 null = Param.Bool(False, "Do not store data, always return zero") 58 in_addr_map = Param.Bool(True, "Memory part of the global address map") 64 kvm_map = Param.Bool(True, "Should KVM map this memory for the guest") 69 conf_table_reported = Param.Bool(True, "Report to configuration table")
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H A D | CommMonitor.py | 66 disable_burst_length_hists = Param.Bool(False, "Disable burst length " \ 71 disable_bandwidth_hists = Param.Bool(False, "Disable bandwidth histograms") 75 disable_latency_hists = Param.Bool(False, "Disable latency histograms") 83 disable_itt_dists = Param.Bool(False, "Disable ITT distributions") 89 disable_outstanding_hists = Param.Bool(False, "Disable outstanding " \ 95 disable_transaction_hists = Param.Bool(False, "Disable transaction count " \ 102 disable_addr_dists = Param.Bool(True, "Disable address distributions")
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H A D | DRAMSim2.py | 56 enableDebug = Param.Bool(False, "Enable DRAMSim2 debug output")
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/gem5/ext/googletest/googletest/test/ |
H A D | gtest_pred_impl_unittest.cc | 56 struct Bool { struct 57 explicit Bool(int val) : value(val != 0) {} function in struct:Bool 59 bool operator>(int n) const { return value > Bool(n).value; } 61 Bool operator+(const Bool& rhs) const { return Bool(value + rhs.value); } 63 bool operator==(const Bool& rhs) const { return value == rhs.value; } 68 // Enables Bool to be used in assertions. 69 std::ostream& operator<<(std::ostream& os, const Bool& x) { 87 bool PredFunction1Bool(Bool v [all...] |
/gem5/src/cpu/ |
H A D | CheckerCPU.py | 37 exitOnError = Param.Bool(False, "Exit on an error") 38 updateOnError = Param.Bool(False, 40 warnOnlyOnLoadError = Param.Bool(True,
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H A D | FuncUnit.py | 67 pipelined = Param.Bool(True, "set to true when the functional unit for"
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/gem5/src/mem/probes/ |
H A D | StackDistProbe.py | 56 verify = Param.Bool(False, "Verify behaviuor with reference implementation") 60 disable_linear_hists = Param.Bool(False, "Disable linear histograms") 64 disable_log_hists = Param.Bool(False, "Disable logarithmic histograms")
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H A D | MemTraceProbe.py | 47 trace_compress = Param.Bool(True, "Enable trace compression") 50 with_pc = Param.Bool(False, "Include PC info in the trace")
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/gem5/src/arch/arm/tracers/ |
H A D | TarmacTrace.py | 53 exit_on_diff = Param.Bool(False, 56 exit_on_insn_diff = Param.Bool(False, 59 mem_wr_check = Param.Bool(False, 62 cpu_id = Param.Bool(False,
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/gem5/src/arch/arm/ |
H A D | ArmSystem.py | 60 multi_proc = Param.Bool(True, "Multiprocessor system?") 67 have_security = Param.Bool(False, 69 have_virtualization = Param.Bool(False, 71 have_crypto = Param.Bool(False, 73 have_lpae = Param.Bool(True, "True if LPAE is implemented") 76 auto_reset_addr = Param.Bool(False, 78 highest_el_is_64 = Param.Bool(False, 83 have_large_asid_64 = Param.Bool(False, 85 have_sve = Param.Bool(True, 89 have_lse = Param.Bool(Tru [all...] |
H A D | ArmNativeTrace.py | 37 stop_on_pc_error = Param.Bool(True,
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/gem5/src/mem/ruby/system/ |
H A D | GPUCoalescer.py | 48 assume_rfo = Param.Bool(True, "assume protocol implementes Read for " 56 garnet_standalone = Param.Bool(False, "")
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H A D | RubySystem.py | 37 randomization = Param.Bool(False, 48 access_backing_store = Param.Bool(False, "Use phys_mem as the functional \ 52 hot_lines = Param.Bool(False, "") 53 all_instructions = Param.Bool(False, "")
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H A D | Sequencer.py | 47 using_ruby_tester = Param.Bool(False, "") 48 no_retry_on_stall = Param.Bool(False, "") 51 support_data_reqs = Param.Bool(True, "data cache requests supported") 52 support_inst_reqs = Param.Bool(True, "inst cache requests supported") 53 is_cpu_sequencer = Param.Bool(True, "connected to a cpu") 71 garnet_standalone = Param.Bool(False, "")
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/gem5/src/cpu/kvm/ |
H A D | BaseKvmCPU.py | 67 useCoalescedMMIO = Param.Bool(False, "Use coalesced MMIO (EXPERIMENTAL)") 68 usePerfOverflow = Param.Bool(False, "Use perf event overflow counters (EXPERIMENTAL)") 69 alwaysSyncTC = Param.Bool(False,
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/gem5/src/base/ |
H A D | CPA.py | 8 enabled = Param.Bool(False, "Is Annotation enabled?")
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.py | 37 ordered = Param.Bool(False, "Whether the buffer is ordered") 40 randomization = Param.Bool(False, "Insert random delays on message \
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/gem5/src/sim/ |
H A D | Root.py | 71 full_system = Param.Bool("if this is a full system simulation") 74 time_sync_enable = Param.Bool(False, "whether time syncing is enabled")
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H A D | DVFSHandler.py | 59 enable = Param.Bool(False, "Enable/Disable the handler")
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/gem5/src/cpu/simple/ |
H A D | AtomicSimpleCPU.py | 62 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 63 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
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/gem5/src/dev/serial/ |
H A D | Uart.py | 57 big_endian = Param.Bool(False, "Is the device Big Endian?") 59 end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
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/gem5/src/mem/qos/ |
H A D | QoSMemCtrl.py | 72 qos_syncro_scheduler = Param.Bool(False, 76 qos_priority_escalation = Param.Bool(False,
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/gem5/src/gpu-compute/ |
H A D | GPU.py | 111 perLaneTLB = Param.Bool(False, "enable per-lane TLB") 119 xactCasMode = Param.Bool(False, "Behavior of xact_cas_load magic instr."); 120 debugSegFault = Param.Bool(False, "enable debugging GPU seg faults") 121 functionalTLB = Param.Bool(False, "Assume TLB causes no delay") 123 localMemBarrier = Param.Bool(False, "Assume Barriers do not wait on "\ 126 countPages = Param.Bool(False, "Generate per-CU file of all pages touched "\ 138 out_of_order_data_delivery = Param.Bool(False, "enable OoO data delivery" 148 impl_kern_boundary_sync = Param.Bool(True, """Insert acq/rel packets into 150 separate_acquire_release = Param.Bool(False, 154 timing = Param.Bool(Fals [all...] |
/gem5/src/arch/riscv/ |
H A D | RiscvSystem.py | 40 bare_metal = Param.Bool(False, "Using Bare Metal Application?")
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/gem5/src/base/vnc/ |
H A D | Vnc.py | 46 frame_capture = Param.Bool(False, "capture changed frames to files")
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