Searched refs:vaddr (Results 1 - 25 of 72) sorted by relevance

123

/gem5/src/arch/riscv/
H A Dvtophys.hh49 vtophys(Addr vaddr) argument
52 return vaddr;
56 vtophys(ThreadContext *tc, Addr vaddr) argument
59 return vtophys(vaddr);
/gem5/src/arch/mips/
H A Dvtophys.hh43 Addr vtophys(Addr vaddr);
44 Addr vtophys(ThreadContext *tc, Addr vaddr);
H A Dvtophys.cc47 MipsISA::vtophys(Addr vaddr) argument
/gem5/src/arch/sparc/
H A Dvtophys.hh42 Addr vtophys(Addr vaddr);
43 Addr vtophys(ThreadContext *tc, Addr vaddr);
H A Dtlb.cc423 Addr vaddr = req->getVaddr();
429 vaddr, req->getSize());
434 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
435 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
436 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
440 req->setPaddr(vaddr & PAddrImplMask);
476 req->setPaddr(vaddr & PAddrImplMask);
481 if (vaddr & 0x3) {
487 vaddr = vaddr
540 Addr vaddr = req->getVaddr(); local
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/gem5/src/arch/x86/
H A Dvtophys.hh50 Addr vtophys(Addr vaddr);
51 Addr vtophys(ThreadContext *tc, Addr vaddr);
H A Dvtophys.cc55 vtophys(Addr vaddr) argument
61 vtophys(ThreadContext *tc, Addr vaddr) argument
65 Addr addr = vaddr;
70 Addr masked_addr = vaddr & mask(logBytes);
72 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
H A Dtlb.cc102 assert(newEntry->vaddr == vpn);
114 newEntry->vaddr = vpn;
176 Addr vaddr = req->getVaddr(); local
177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
181 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
185 if (!msrAddrToIndex(regNum, vaddr))
197 Addr IOPort = vaddr & ~IntAddrPrefixMask;
285 Addr vaddr = req->getVaddr(); local
286 DPRINTF(TLB, "Translating vaddr
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H A Dpagetable.cc51 : paddr(0), vaddr(0), logBytes(0), writable(0),
59 paddr(_paddr), vaddr(_vaddr), logBytes(PageShift), writable(!read_only),
68 SERIALIZE_SCALAR(vaddr);
83 UNSERIALIZE_SCALAR(vaddr);
/gem5/src/arch/alpha/
H A Dvtophys.cc49 kernel_pte_lookup(PortProxy &mem, Addr ptbr, VAddr vaddr) argument
51 Addr level1_pte = ptbr + vaddr.level1();
54 DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
58 Addr level2_pte = level1.paddr() + vaddr.level2();
61 DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
65 Addr level3_pte = level2.paddr() + vaddr.level3();
68 DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
75 vtophys(Addr vaddr) argument
78 if (IsUSeg(vaddr))
79 DPRINTF(VtoPhys, "vtophys: invalid vaddr
93 VAddr vaddr = addr; local
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H A Dvtophys.hh45 VAddr vaddr);
47 Addr vtophys(Addr vaddr);
48 Addr vtophys(ThreadContext *tc, Addr vaddr);
H A Dfaults.hh135 VAddr vaddr; member in class:AlphaISA::DtbFault
141 : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
158 NDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) argument
159 : DtbFault(vaddr, reqFlags, flags)
176 PDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) argument
177 : DtbFault(vaddr, reqFlags, flags)
192 DtbPageFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) argument
193 : DtbFault(vaddr, reqFlags, flags)
208 DtbAcvFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) argument
209 : DtbFault(vaddr, reqFlag
224 DtbAlignmentFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) argument
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H A Dtlb.hh95 void insert(Addr vaddr, TlbEntry &entry);
102 demapPage(Addr vaddr, uint64_t asn) override
105 flushAddr(vaddr, asn);
110 validVirtualAddress(Addr vaddr)
113 Addr unimplBits = vaddr & VAddrUnImplMask;
H A Dfaults.cc160 tc->setMiscRegNoEffect(IPR_VA, vaddr);
171 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
202 VAddr vaddr(pc);
203 TlbEntry entry(p->pTable->pid(), vaddr.page(), pte->paddr,
206 dynamic_cast<TLB *>(tc->getITBPtr())->insert(vaddr.page(), entry);
218 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
219 if (!pte && p->fixupStackFault(vaddr))
220 pte = p->pTable->lookup(vaddr);
221 panic_if(!pte, "Tried to access unmapped address %#x.\n", (Addr)vaddr);
222 TlbEntry entry(p->pTable->pid(), vaddr
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/gem5/src/mem/
H A Dpage_table.cc49 EmulationPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags) argument
53 assert(pageOffset(vaddr) == 0);
55 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr + size);
58 auto it = pTable.find(vaddr);
63 vaddr);
66 pTable.emplace(vaddr, Entry(paddr, flags));
70 vaddr += pageSize;
76 EmulationPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) argument
78 assert(pageOffset(vaddr)
105 unmap(Addr vaddr, int64_t size) argument
121 isUnmapped(Addr vaddr, int64_t size) argument
134 lookup(Addr vaddr) argument
144 translate(Addr vaddr, Addr &paddr) argument
197 Addr vaddr; local
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H A Dpage_table.hh112 * @param vaddr The starting virtual address of the region.
118 virtual void map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags = 0);
119 virtual void remap(Addr vaddr, int64_t size, Addr new_vaddr);
120 virtual void unmap(Addr vaddr, int64_t size);
124 * @param vaddr The starting virtual address of the region.
128 virtual bool isUnmapped(Addr vaddr, int64_t size);
132 * @param vaddr The virtual address.
133 * @return The page table entry corresponding to vaddr.
135 const Entry *lookup(Addr vaddr);
139 * @param vaddr Th
150 translate(Addr vaddr) argument
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H A Dmulti_level_page_table.hh137 walk(System *system, Addr pageSize, Addr table, Addr vaddr, argument
140 entry->read(system->physProxy, table, vaddr);
148 walk(System *system, Addr pageSize, Addr table, Addr vaddr, argument
152 first.read(system->physProxy, table, vaddr);
165 system, pageSize, next, vaddr, allocate, entry);
171 walk(System *system, Addr pageSize, Addr table, Addr vaddr, argument
175 system, pageSize, table, vaddr, allocate, entry);
216 map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags = 0) override
218 EmulationPageTable::map(vaddr, paddr, size, flags);
224 vaddr
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/gem5/src/arch/arm/
H A Dvtophys.hh45 Addr vtophys(Addr vaddr);
46 Addr vtophys(ThreadContext *tc, Addr vaddr);
47 bool virtvalid(ThreadContext *tc, Addr vaddr);
H A Dvtophys.cc62 ArmISA::vtophys(Addr vaddr) argument
64 fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
72 // to get it to translate the vaddr to a paddr
108 ArmISA::virtvalid(ThreadContext *tc, Addr vaddr) argument
110 const std::pair<bool, Addr> translation(try_translate(tc, vaddr));
/gem5/src/arch/power/
H A Dvtophys.hh46 Addr vtophys(Addr vaddr);
47 Addr vtophys(ThreadContext *tc, Addr vaddr);
H A Dvtophys.cc36 PowerISA::vtophys(Addr vaddr) argument
/gem5/src/sim/
H A Dfaults.hh96 Addr vaddr; member in class:GenericPageTableFault
99 GenericPageTableFault(Addr va) : vaddr(va) {}
102 Addr getFaultVAddr() const { return vaddr; }
108 Addr vaddr; member in class:GenericAlignmentFault
111 GenericAlignmentFault(Addr va) : vaddr(va) {}
114 Addr getFaultVAddr() const { return vaddr; }
H A Dfaults.cc72 handled = p->fixupStackFault(vaddr);
75 panic("Page table fault when accessing virtual address %#x\n", vaddr);
81 panic("Alignment fault when accessing virtual address %#x\n", vaddr);
/gem5/src/gpu-compute/
H A Dfetch_unit.cc119 Addr vaddr = wavefront->pc(); local
127 vaddr +=
130 vaddr = wavefront->basePtr + vaddr;
133 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, vaddr);
139 Addr split_addr = roundDown(vaddr + block_size - 1, block_size);
142 if (split_addr > vaddr) {
144 size = split_addr - vaddr;
149 0, vaddr, size, Request::INST_FETCH,
172 vaddr);
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H A Dgpu_tlb.cc176 newEntry->vaddr = vpn;
195 if ((*entry)->vaddr <= va && (*entry)->vaddr + page_size > va) {
196 DPRINTF(GPUTLB, "Matched vaddr %#x to entry starting at %#x "
197 "with size %#x.\n", va, (*entry)->vaddr, page_size);
280 Addr vaddr = req->getVaddr(); local
281 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
286 vaddr = vaddr >> 3;
290 switch (vaddr
662 Addr vaddr = req->getVaddr(); local
716 Addr vaddr = req->getVaddr(); local
1164 Addr vaddr = pkt->req->getVaddr(); local
1323 Addr vaddr = pkt->req->getVaddr(); local
1417 Addr vaddr = pkt->req->getVaddr(); local
1525 Addr vaddr = pkt->req->getVaddr(); local
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