arch/sparc/tlb.cc

423     Addr vaddr = req->getVaddr();
429             vaddr, req->getSize());
434             if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
435                 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
436                 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
440             req->setPaddr(vaddr & PAddrImplMask);
476         req->setPaddr(vaddr & PAddrImplMask);
481     if (vaddr & 0x3) {
487         vaddr = vaddr & VAddrAMask;
489     if (!validVirtualAddress(vaddr, addr_mask)) {
495         e = lookup(vaddr, part_id, true);
499         e = lookup(vaddr, part_id, false, context);
503         writeTagAccess(vaddr, context);
517         writeTagAccess(vaddr, context);
527     req->setPaddr(e->pte.translate(vaddr));
528     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
540     Addr vaddr = req->getVaddr();
546     bool unaligned = vaddr & (size - 1);
549             vaddr, size, asi);
561             req->setPaddr(vaddr & PAddrImplMask);
574                     ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
576                     req->setPaddr(ce->pte.translate(vaddr));
581                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
589                     ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
591                     req->setPaddr(ce->pte.translate(vaddr));
596                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
636             writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
641             writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
694         writeSfsr(vaddr, false, ct, false, OtherFault, asi);
699         vaddr = vaddr & VAddrAMask;
701     if (!validVirtualAddress(vaddr, addr_mask)) {
702         writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
712         req->setPaddr(vaddr & PAddrImplMask);
716     e = lookup(vaddr, part_id, real, context);
719         writeTagAccess(vaddr, context);
734         writeTagAccess(vaddr, context);
735         writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
740         writeTagAccess(vaddr, context);
741         writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
746         writeTagAccess(vaddr, context);
747         writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
752         writeTagAccess(vaddr, context);
753         writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
776     req->setPaddr(e->pte.translate(vaddr));
777     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
783         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
792         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
800     if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
801         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
808         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
811     if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
812         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
819         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);