Searched refs:std (Results 1401 - 1425 of 1914) sorted by relevance

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/gem5/src/systemc/tests/systemc/utils/sc_vector/test02/
H A Dtest02.cpp117 std::vector<sc_object*> children = dut.get_child_objects();
/gem5/src/arch/arm/
H A Dstage2_lookup.hh85 req = std::make_shared<Request>();
/gem5/src/arch/riscv/insts/
H A Dstatic_inst.hh70 std::vector<StaticInstPtr> microops;
/gem5/src/arch/x86/
H A Dintmessage.hh82 RequestPtr req = std::make_shared<Request>(
H A Ddecoder.hh75 std::vector<MachInst> chunks;
76 std::vector<MachInst> masks;
229 typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap;
233 typedef std::unordered_map<
/gem5/src/cpu/testers/directedtest/
H A DSeriesRequestGenerator.cc63 RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId);
H A DInvalidateGenerator.cc63 RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId);
H A DRubyDirectedTester.cc82 RubyDirectedTester::getPort(const std::string &if_name, PortID idx)
/gem5/src/dev/mips/
H A Dmalta_cchip.cc54 using namespace std;
/gem5/util/systemc/gem5_within_systemc/
H A DMakefile46 CXXFLAGS += -std=c++0x
/gem5/ext/googletest/googletest/samples/
H A Dprime_tables.h103 ::std::fill(is_prime_, is_prime_ + is_prime_size_, true);
/gem5/ext/googletest/googletest/test/
H A Dgtest-typed-test_test.cc61 // We used to use std::list here, but switched to std::vector since
63 typedef std::vector<T> Vector;
64 typedef std::set<int> IntSet;
320 typedef Types<std::vector<double>, std::set<char> > MyContainers;
H A Dgtest_env_var_test_.cc43 using ::std::cout;
/gem5/src/base/
H A Dbitunion.test.cc39 using namespace std;
268 is64 = std::is_same<BitUnionBaseType<Dummy64>, uint64_t>::value;
270 is64 = std::is_same<BitUnionBaseType<Dummy32>, uint64_t>::value;
277 std::stringstream ss;
H A Dmatch.cc35 using namespace std;
/gem5/src/dev/net/
H A Detherlink.cc67 using namespace std;
92 EtherLink::getPort(const std::string &if_name, PortID idx)
147 txQueue.emplace_back(std::make_pair(curTick() + linkDelay, packet));
257 txQueue.emplace_back(std::make_pair(tick, delayed_packet));
H A Dsinic.hh154 typedef std::vector<VirtualReg> VirtualRegs;
155 typedef std::list<unsigned> VirtualList;
233 Port &getPort(const std::string &if_name,
308 Interface(const std::string &name, Device *d)
/gem5/src/mem/cache/prefetch/
H A Dstride.cc109 auto insertion_result = pcTables.insert(std::make_pair(context,
118 StridePrefetcher::PCTable::PCTable(int assoc, int sets, const std::string name,
142 std::vector<AddrPriority> &addresses)
235 std::vector<ReplaceableEntry*> possible_entries;
/gem5/src/systemc/ext/tlm_core/1/req_rsp/ports/
H A Devent_finder.hh62 std::ostringstream out;
/gem5/src/systemc/ext/core/
H A Dsc_port.hh61 std::string name;
63 sc_trace_params(sc_trace_file *tf, const std::string &name) :
67 typedef std::vector<sc_trace_params *> sc_trace_params_vec;
217 std::vector<IF *> _interfaces;
/gem5/src/arch/arm/tracers/
H A Dtarmac_base.hh95 std::string disassemble;
H A Dtarmac_base.cc81 std::for_each(disassemble.begin(), disassemble.end(),
/gem5/src/arch/sparc/linux/
H A Dprocess.cc45 using namespace std;
/gem5/src/base/loader/
H A Dhex_file.cc42 using namespace std;
/gem5/src/cpu/
H A Dthread_context.cc177 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
183 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
218 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
224 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);

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