/gem5/src/systemc/tests/include/ |
H A D | SimpleATInitiator1.h | 39 #include <queue> 328 std::queue<mytransaction_type*> mEndResponseQueue;
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H A D | ExplicitATTarget.h | 28 #include <queue>
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H A D | SimpleATInitiator2.h | 39 #include <queue>
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/gem5/util/batch/ |
H A D | send.py | 79 %(progname)s [-c] [-e] [-f] [-j <jobfile>] [-q queue] [-v] <regexp> 85 -q <queue> submit job to the named queue 110 queue = '' variable 140 queue = arg variable 283 #if queue: 284 # qsub.queue = queue
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/gem5/src/gpu-compute/ |
H A D | lds_state.hh | 41 #include <queue> 227 // the queue of packets that are going back to the CU after a 230 std::queue<std::pair<Tick, PacketPtr>> returnQueue;
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H A D | gpu_tlb.hh | 41 #include <queue> 407 // this FIFO queue keeps track of the virt. page addresses 409 std::queue<Addr> cleanupQueue;
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H A D | compute_unit.hh | 181 * queue, such that on simulation exit, all callbacks in the callback 182 * queue will have their process() function called. 525 * here we queue all the translation requests that were 572 * here we queue all the translation requests that were 615 * here we queue all the requests that were 618 std::queue<PacketPtr> retries;
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/gem5/src/cpu/kvm/ |
H A D | base.hh | 47 #include <queue> 234 * Execute the CPU until the next event in the main event queue or 422 * Get a pointer to the event queue owning devices. 424 * Devices always live in a separate device event queue when 426 * this queue when accessing devices. By convention, devices and 427 * the VM use the same event queue. 601 std::queue<PacketPtr> pendingMMIOPkts; 670 * the thread that is going to execute our event queue. For 674 * SimObject's event queue. 713 * instruction event queue an [all...] |
/gem5/src/dev/virtio/ |
H A D | fs9p.cc | 121 queue(params->system->physProxy, params->queueSize, *this) 128 registerQueue(queue); 189 queue.produceDescriptor(main_desc, sizeof(P9MsgHeader) + size);
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H A D | fs9p.hh | 156 std::string name() const { return parent.name() + ".queue"; } 162 FSQueue queue; member in class:VirtIO9PBase
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/gem5/src/sim/ |
H A D | eventq.hh | 71 //! The current event queue for the running thread. Access to this queue 79 //! Function for returning eventq queue for the provided 80 //! index. The function allocates a new queue in case one 112 static const FlagsType IsMainQueue = 0x0020; // on main event queue 183 * An item on an event queue. The action caused by a given 194 // The event queue is now a linked list of linked lists. The 223 /// queue to which this event belongs (though it may or may not be 224 /// scheduled on this queue yet) 225 EventQueue *queue; member in class:Event [all...] |
H A D | eventq.cc | 177 assert(event->queue == this);
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/gem5/src/cpu/minor/ |
H A D | fetch1.cc | 167 DPRINTF(Fetch, "Inserting fetch into the fetch queue " 286 DPRINTF(Fetch, "Fetch not at front of requests queue, can't" 305 * for this queue->queue transfer */ 381 Fetch1::popAndDiscard(FetchQueue &queue) argument 383 if (!queue.empty()) { 384 delete queue.front(); 385 queue.pop(); 422 * should hit the responses queue. It's the job of 'step' to throw them 653 /* Take up a slot in the fetch queue */ [all...] |
H A D | fetch1.hh | 85 * A request can be submitted by pushing it onto the requests queue after 91 * memory system and the transfers queue (state becomes RequestIssuing). 92 * Retries are handled by leaving the packet on the requests queue and 97 * transfers queue to pass on to Fetch2. */ 310 /** Count of the number fetches which have left the transfers queue 317 * transfers queue */ 350 * head of the requests queue. Also tries to move the request 365 /** Pop a request from the given queue and correctly deallocate and 367 void popAndDiscard(FetchQueue &queue); 369 /** Handle pushing a TLB response onto the right queue */ [all...] |
/gem5/src/cpu/trace/ |
H A D | trace_cpu.hh | 47 #include <queue> 117 * better than looping the entire queue. An alternative choice would be to 1041 * into the queue in that order. Thus nodes are more likely to 1044 std::queue<const GraphNode*> depFreeQueue;
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/gem5/src/cpu/checker/ |
H A D | cpu.hh | 49 #include <queue> 143 // keep them all in a std::queue 144 std::queue<InstResult> result; 153 std::queue<int> miscRegIdxs;
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/gem5/src/dev/arm/ |
H A D | gic_v3_its.hh | 43 #include <queue> 323 std::queue<ItsAction> packetsToRetry; 337 * ITS queue (ItsCommand). 416 * queue. Only one command can be executed per time.
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/gem5/src/cpu/o3/ |
H A D | cpu.hh | 52 #include <queue> 544 std::queue<ListIt> removeList; 636 /** The fetch stage's instruction queue. */ 639 /** The decode stage's instruction queue. */ 642 /** The rename stage's instruction queue. */ 645 /** The IEW stage's instruction queue. */
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H A D | commit.hh | 47 #include <queue> 163 /** Sets the pointer to the queue coming from rename. */ 166 /** Sets the pointer to the queue coming from IEW. */ 344 /** IEW instruction queue interface. */ 347 /** Wire to read information from IEW queue. */ 350 /** Rename instruction queue interface, for ROB. */ 353 /** Wire to read information from rename queue. */ 407 * instructions to get from the rename instruction queue.
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H A D | inst_queue.hh | 49 #include <queue> 66 * A standard instruction queue class. It holds ready instructions, in 78 * latency, the instruction is put into the queue to execute, where it will 107 /** Pointer back to the instruction queue. */ 137 /** Resets all instruction queue state. */ 217 * the queue to execute. 257 /** Notify instruction queue that a previous blockage has resolved */ 297 /** The queue to the execute stage. Issued instructions will be written 335 * Struct for comparing entries to be added to the priority queue. 339 * priority queue [all...] |
H A D | decode_impl.hh | 191 // Setup wire to write information to proper place in decode queue. 201 // Setup wire to read information from fetch queue. 668 std::queue<DynInstPtr> 705 // queue. The next instruction may not be valid, so check to
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H A D | lsq_unit.hh | 51 #include <queue> 107 /** Constructs an empty store queue entry. */ 172 /** Constructs an empty store queue entry. */ 474 /** The store queue. */ 477 /** The load queue. */ 504 /** Wire to read information from the issue stage time queue. */ 878 // This function only writes the data to the store queue, so no fault
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/gem5/src/dev/net/ |
H A D | dist_iface.cc | 46 #include <queue> 436 // receiver thread shares the event queue with the simulation thread 517 // descriptors are saved in the ordered queue. The currently scheduled 518 // packet is always on the top of the queue. 519 // NOTE: we use the event queue lock to protect the receive desc queue, 540 // the event queue queue lock when this is called! 575 // serialize the receive desc queue 576 std::queue<Des [all...] |
/gem5/src/mem/cache/prefetch/ |
H A D | Prefetcher.py | 127 queue_filter = Param.Bool(True, "Don't queue redundant prefetches") 425 delay_queue_enable = Param.Bool(True, "Enable the delay queue") 427 "Number of entries in the delay queue") 430 queue")
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/gem5/src/mem/cache/ |
H A D | base.hh | 160 * current MSHR status. This queue has a pointer to our specific 216 /** The cache-specific queue. */ 266 /** A normal packet queue used to store responses. */ 267 RespPacketQueue queue; member in class:BaseCache::CacheSlavePort 587 * Return the next queue entry to service, either a pending miss 588 * from the MSHR queue, a buffered write from the write buffer, or 1235 * send it out. This construct allows a queue entry to choose a suitable 1244 * Similar to sendMSHR, but for a write-queue entry 1248 * @param wq_entry The write-queue entry to turn into a packet and send
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