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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
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10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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19
20#ifndef __EXPLICIT_AT_TARGET_H__
21#define __EXPLICIT_AT_TARGET_H__
22
23#include "tlm.h"
24#include "tlm_utils/simple_target_socket.h"
25//#include <systemc>
26#include <cassert>
27#include <vector>
28#include <queue>
29//#include <iostream>
30
31class ExplicitATTarget : public sc_core::sc_module
32{
33public:
34  typedef tlm::tlm_generic_payload                 transaction_type;
35  typedef tlm::tlm_phase                           phase_type;
36  typedef tlm::tlm_sync_enum                       sync_enum_type;
37  typedef tlm_utils::simple_target_socket<ExplicitATTarget>     target_socket_type;
38
39public:
40  target_socket_type socket;
41
42public:
43  SC_HAS_PROCESS(ExplicitATTarget);
44  ExplicitATTarget(sc_core::sc_module_name name) :
45    sc_core::sc_module(name),
46    socket("socket"),
47    mCurrentTransaction(0)
48  {
49    // register nb_transport method
50    socket.register_nb_transport_fw(this, &ExplicitATTarget::myNBTransport);
51    socket.register_transport_dbg(this, &ExplicitATTarget::transport_dbg);
52
53    SC_THREAD(beginResponse)
54  }
55
56  sync_enum_type myNBTransport(transaction_type& trans, phase_type& phase, sc_core::sc_time& t)
57  {
58    if (phase == tlm::BEGIN_REQ) {
59      sc_dt::uint64 address = trans.get_address();
60      assert(address < 400);
61
62      // This target only supports one transaction at a time
63      // This will only work with LT initiators
64      assert(mCurrentTransaction == 0);
65
66      unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
67      if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
68        std::cout << name() << ": Received write request: A = 0x"
69                  << std::hex << (unsigned int)address << ", D = 0x" << data
70                  << std::dec << " @ " << sc_core::sc_time_stamp()
71                  << std::endl;
72
73        *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
74
75        // Synchronization on demand (eg need to assert an interrupt)
76        mResponseEvent.notify(t);
77        mCurrentTransaction = &trans;
78
79        // End request phase
80        phase = tlm::END_REQ;
81        return tlm::TLM_UPDATED;
82
83      } else {
84        std::cout << name() << ": Received read request: A = 0x"
85                  << std::hex << (unsigned int)address
86                  << std::dec << " @ " << sc_core::sc_time_stamp()
87                  << std::endl;
88
89        data = *reinterpret_cast<unsigned int*>(&mMem[address]);
90        trans.set_response_status(tlm::TLM_OK_RESPONSE);
91
92        // Finish transaction (use timing annotation)
93        t += sc_core::sc_time(100, sc_core::SC_NS);
94        return tlm::TLM_COMPLETED;
95      }
96
97    } else if (phase == tlm::END_RESP) {
98
99      // Transaction finished
100      mCurrentTransaction = 0;
101      return tlm::TLM_COMPLETED;
102    }
103
104    // Not possible
105    assert(0); exit(1);
106//    return tlm::TLM_COMPLETED;  //unreachable code
107  }
108
109  void beginResponse()
110  {
111    while (true) {
112      // Wait for next synchronization request
113      wait(mResponseEvent);
114
115      assert(mCurrentTransaction);
116      // start response phase
117      phase_type phase = tlm::BEGIN_RESP;
118      sc_core::sc_time t = sc_core::SC_ZERO_TIME;
119
120      // Set response data
121      mCurrentTransaction->set_response_status(tlm::TLM_OK_RESPONSE);
122      assert(mCurrentTransaction->get_command() == tlm::TLM_WRITE_COMMAND);
123
124      sc_dt::uint64 address = mCurrentTransaction->get_address();
125      assert(address < 400);
126      *reinterpret_cast<unsigned int*>(mCurrentTransaction->get_data_ptr()) =
127        *reinterpret_cast<unsigned int*>(&mMem[address]);
128
129      // We are synchronized, we can read/write sc_signals, wait,...
130      // Wait before sending the response
131      wait(50, sc_core::SC_NS);
132
133      if (socket->nb_transport_bw(*mCurrentTransaction, phase, t) == tlm::TLM_COMPLETED) {
134        mCurrentTransaction = 0;
135
136      } else {
137        // Initiator will call nb_transport(trans, END_RESP, t)
138      }
139    }
140  }
141
142  unsigned int transport_dbg(transaction_type& r)
143  {
144    if (r.get_address() >= 400) return 0;
145
146    unsigned int tmp = (int)r.get_address();
147    unsigned int num_bytes;
148    if (tmp + r.get_data_length() >= 400) {
149      num_bytes = 400 - tmp;
150
151    } else {
152      num_bytes = r.get_data_length();
153    }
154    if (!r.is_read() && !r.is_write()) {
155      return 0;
156	}
157    if (r.is_read()) {
158      for (unsigned int i = 0; i < num_bytes; ++i) {
159        r.get_data_ptr()[i] = mMem[i + tmp];
160      }
161
162    } else {
163      for (unsigned int i = 0; i < num_bytes; ++i) {
164        mMem[i + tmp] = r.get_data_ptr()[i];
165      }
166    }
167    return num_bytes;
168  }
169
170private:
171  unsigned char mMem[400];
172  sc_core::sc_event mResponseEvent;
173  transaction_type* mCurrentTransaction;
174};
175
176#endif
177