/gem5/src/mem/ruby/system/ |
H A D | GPUCoalescer.cc | 1158 MemSlavePort *port = ss->port; local 1159 assert(port != NULL); 1163 port->hitCallback(mylist[i]);
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/gem5/src/cpu/trace/ |
H A D | trace_cpu.cc | 478 if (port.sendTimingReq(retryPkt)) { 682 bool success = port.sendTimingReq(pkt); 1070 if (!port.sendTimingReq(retryPkt)) { 1171 bool success = port.sendTimingReq(pkt);
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/gem5/configs/example/ |
H A D | apu_se.py | 458 # Connect cache port's to ruby 468 system.cpu[i].itb.walker.port = ruby_port.slave 469 system.cpu[i].dtb.walker.port = ruby_port.slave
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/gem5/src/mem/cache/ |
H A D | base.hh | 118 * A cache master port is used for the memory-side port of the 119 * cache, and in addition to the basic timing port that only sends 123 * and the sendDeferredPacket of the timing port is modified to 150 * Memory-side port always snoops. 159 * the memory-side cache port to also send requests based on the 173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port, argument 176 ReqPacketQueue(cache, port, label), cache(cache), 209 * The memory-side port extends the base cache master port wit [all...] |
/gem5/src/cpu/simple/ |
H A D | atomic.cc | 278 AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) 280 return port.sendAtomic(pkt);
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/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | hppa.s | 14 ; This file (pa-risc.s) is part of the port of QuickThreads for
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/gem5/configs/splash2/ |
H A D | cluster.py | 225 system.physmem.port = system.membus.master
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/gem5/src/systemc/ext/core/ |
H A D | sc_module.hh | 94 sc_port_base *port() const { return _port; } function in class:sc_core::sc_bind_proxy
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/gem5/src/mem/ |
H A D | DRAMCtrl.py | 79 port = SlavePort("Slave port") variable in class:DRAMCtrl
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H A D | dram_ctrl.cc | 64 port(name() + ".port", *this), isTimingMode(false), 193 if (!port.isConnected()) { 196 port.sendRangeChange(); 651 // remember that we have to retry this port 665 // remember that we have to retry this port 767 port.sendRetryReq(); 941 port.schedTimingResp(pkt, response_time); 1633 port.sendRetryReq(); 2853 if (if_name != "port") { [all...] |
H A D | dram_ctrl.hh | 103 // For now, make use of a queued slave port to avoid dealing with 128 * Our incoming port, for a multi-ported controller add a crossbar 131 MemoryPort port; member in class:DRAMCtrl
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H A D | xbar.cc | 83 // the master port index translates directly to the vector position 88 // the slave port index translates directly to the vector position 136 port(_port), xbar(_xbar), _name(_name), state(IDLE), 166 // retrying port (or in the case of the snoop ports the snoop 167 // response port that mirrors the actual slave port) as we leave 172 // destination port is already engaged in a transaction waiting 175 // the port should not be waiting already 179 // put the port at the end of the retry list waiting for the 210 // this port [all...] |
/gem5/configs/example/arm/ |
H A D | fs_bigLITTLE.py | 126 sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.master)
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/gem5/src/dev/arm/ |
H A D | RealView.py | 516 port_node = FdtNode("port") 596 cur_sys.bootmem.port = mem_bus.master 879 cur_sys.bootmem.port = mem_bus.master 898 cur_sys.bootmem.port = mem_bus.master 1078 cur_sys.bootmem.port = mem_bus.master
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/gem5/src/cpu/minor/ |
H A D | lsq.hh | 88 /** Exposable data port */ 118 * translation, the queues in this port and back from the memory 125 /** Owning port */ 126 LSQ &port; member in class:Minor::LSQ::LSQRequest 724 /** Return the raw-bindable port */
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/gem5/src/arch/arm/ |
H A D | table_walker.cc | 61 stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), 105 port = &m->getDMAPort(); 113 fatal_if(!port, "Table walker must have a valid port\n"); 120 if (if_name == "port") { 122 return *port; 124 fatal("Cannot access table walker port through stage-two walker\n"); 2021 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 2030 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 2040 port [all...] |
H A D | table_walker.hh | 830 DmaPort* port; member in class:ArmISA::TableWalker::LongDescriptor
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/gem5/configs/common/ |
H A D | HMC.py | 242 crossbar between port and Link Controller")
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/gem5/src/base/ |
H A D | inet.hh | 244 uint8_t port() const { return _port; } function in struct:Net::IpWithPort
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H A D | remote_gdb.cc | 154 #include "mem/port.hh" 357 DPRINTF(GDBMisc, "Can't bind port %d\n", _port); 364 ccprintf(cerr, "%d: %s: listening for remote gdb on port %d\n", 385 BaseRemoteGDB::port() const function in class:BaseRemoteGDB 388 "Remote GDB port is unknown until listen() has been called.\n");
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/gem5/src/cpu/kvm/ |
H A D | base.cc | 1070 panic("KVM: Unhandled guest IO (dir: %i, size: %i, port: 0x%x, count: %i)\n", 1072 _kvmRun->io.port, _kvmRun->io.count);
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