Searched refs:memory (Results 51 - 75 of 107) sorted by relevance
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/gem5/src/arch/riscv/ |
H A D | interrupts.hh | 35 #include <memory>
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/gem5/src/arch/sparc/ |
H A D | process.hh | 35 #include <memory> 88 // Set up stack. On SPARC Linux, stack goes from the top of memory 132 // Set up stack. On SPARC Linux, stack goes from the top of memory
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/gem5/src/mem/cache/compressors/ |
H A D | bdi.hh | 40 #include <memory>
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/gem5/src/mem/ |
H A D | dram_ctrl.hh | 74 * The DRAM controller is a single-channel memory controller capturing 76 * contemporary DRAM. For multi-channel memory systems, the controller 86 * evaluate the system impact of a wide range of memory technologies, 109 DRAMCtrl& memory; member in class:DRAMCtrl::MemoryPort 134 * Remember if the memory system is in timing mode 288 DRAMCtrl& memory; member in class:DRAMCtrl::Rank 449 return csprintf("%s_%d", memory.name(), rank); 494 ((memory.busStateNext == WRITE) && (writeEntries != 0)); 833 * system packet if the pakcet is larger than burst of the memory. The 846 * The memory schdule [all...] |
/gem5/src/arch/arm/ |
H A D | system.hh | 46 #include <memory> 142 * Range for memory-mapped m5 pseudo ops. The range will be 279 * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
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H A D | pmu.hh | 45 #include <memory> 89 * memory references synthesized from loads and stores), the PMU
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H A D | semihosting.hh | 44 #include <memory> 281 * needed to read its parameters from guest memory. 302 /** Number of aarch32 arguments to read from guest memory. -1 305 /** Number of aarch32 arguments to read from guest memory. -1
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/gem5/src/arch/alpha/ |
H A D | interrupts.hh | 35 #include <memory>
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/gem5/src/dev/virtio/ |
H A D | fs9p.hh | 44 #include <memory>
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/gem5/src/systemc/core/ |
H A D | process.hh | 34 #include <memory>
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | dirty.S | 33 # Set SUM=1 so user memory access is permitted
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/gem5/configs/example/ |
H A D | hmctest.py | 21 parser.add_argument("--external-memory-system", default=0, action="store", 22 type=int, help="External memory system") 24 parser.add_argument("--tlm-memory", action="store_true", help="use\ 63 # Config memory system with given HMC arch 99 main memory")
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/gem5/src/sim/ |
H A D | fd_entry.hh | 39 #include <memory>
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | base.hh | 45 #include <memory> 60 * the memory system, based on a collection of simple generator 63 * memory controllers, or function as a black box replacement for
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/gem5/src/base/ |
H A D | types.hh | 43 #include <memory>
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/gem5/ext/pybind11/include/pybind11/ |
H A D | iostream.h | 17 #include <memory>
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/gem5/system/alpha/console/ |
H A D | dbmentry.S | 48 /* Processor 0 start stack frame is begining of physical memory (0) 177 mb # ensure memory coherence
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/gem5/src/dev/arm/ |
H A D | pl111.hh | 50 #include <memory>
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H A D | hdlcd.hh | 60 * of the current frame. This compromise was made to save on memory and 80 #include <memory>
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/gem5/src/gpu-compute/ |
H A D | wavefront.hh | 41 #include <memory> 81 * The hardware/finalizer can support arguments in hardware or use memory to 209 // outstanding global+local memory requests 211 // memory requests between scoreboard 214 // outstanding global memory write requests 216 // outstanding local memory write requests 218 // outstanding global memory read requests 220 // outstanding local memory read requests 269 // A pointer to the private memory area 271 // The size of the private memory are [all...] |
H A D | cl_driver.cc | 38 #include <memory> 122 // all kernels will share the same read-only memory
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/gem5/configs/learning_gem5/part3/ |
H A D | msi_caches.py | 76 # Create a single directory controller (Really the memory cntrl) 137 # This is the cache memory object that stores the cache data and tags 194 """ranges are the memory ranges assigned to this controller. 203 # Connect this directory to the memory side. 204 self.memory = mem_ctrls[0].port 219 # from memory back to the controller. Any messages received on the 220 # memory port (see self.memory above) will be directed to this
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H A D | ruby_caches_MI_example.py | 76 # Create a single directory controller (Really the memory cntrl) 134 # This is the cache memory object that stores the cache data and tags 183 """ranges are the memory ranges assigned to this controller. 192 # Connect this directory to the memory side. 193 self.memory = mem_ctrls[0].port
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/gem5/src/cpu/ |
H A D | static_inst.hh | 48 #include <memory>
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/gem5/src/dev/ |
H A D | dma_device.hh | 49 #include <memory> 355 * them in the memory location pointed to by dst. The method
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