Lines Matching refs:memory
74 * The DRAM controller is a single-channel memory controller capturing
76 * contemporary DRAM. For multi-channel memory systems, the controller
86 * evaluate the system impact of a wide range of memory technologies,
109 DRAMCtrl& memory;
134 * Remember if the memory system is in timing mode
288 DRAMCtrl& memory;
449 return csprintf("%s_%d", memory.name(), rank);
494 ((memory.busStateNext == WRITE) && (writeEntries != 0));
833 * system packet if the pakcet is larger than burst of the memory. The
846 * The memory schduler/arbiter - picks which request needs to
955 * The following are basic design parameters of the memory
984 * Basic memory timing parameters initialized based on parameter
1080 // per-master bytes read and written to memory
1084 // per-master bytes read and written to memory rate
1088 // per-master read and write serviced memory accesses
1092 // per-master read and write total memory access latency
1096 // per-master raed and write average memory access latency