Searched refs:masterId (Results 26 - 50 of 64) sorted by relevance

123

/gem5/src/cpu/testers/rubytest/
H A DCheck.cc111 m_tester_ptr->masterId(), curTick(), m_pc);
149 m_tester_ptr->masterId(), curTick(), m_pc);
182 writeAddr, 1, flags, m_tester_ptr->masterId(), curTick(), m_pc);
246 m_tester_ptr->masterId(), curTick(), m_pc);
H A DRubyTester.hh120 MasterID masterId() { return _masterId; } function in class:RubyTester
/gem5/src/gpu-compute/
H A Ddispatcher.hh60 MasterID masterId() { return _masterId; } function in class:GpuDispatcher
H A Dfetch_unit.cc150 computeUnit->masterId(), 0, 0, nullptr);
H A Dshader.cc344 cuList[0]->masterId(), 0, 0, nullptr);
/gem5/src/cpu/checker/
H A Dcpu.cc65 masterId = systemPtr->getMasterId(this);
163 flags, masterId, thread->pcState().instAddr(),
169 flags, masterId, thread->pcState().instAddr(),
H A Dcpu_impl.hh249 sizeof(MachInst), 0, masterId, fetch_PC,
253 Request::INST_FETCH, masterId,
/gem5/src/dev/arm/
H A Dsmmu_v3.hh93 const MasterID masterId; member in class:SMMUv3
/gem5/src/systemc/tlm_bridge/
H A Dtlm_to_gem5.hh177 const MasterID masterId; member in class:sc_gem5::TlmToGem5Bridge
/gem5/src/cpu/testers/memtest/
H A Dmemtest.cc98 masterId(p->system->getMasterId(this)),
249 RequestPtr req = std::make_shared<Request>(paddr, 1, flags, masterId);
/gem5/src/mem/cache/
H A Dnoncoherent_cache.cc280 assert(tgt_pkt->req->masterId() < system->maxMasters());
281 missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
H A Dbase.hh1196 assert(pkt->req->masterId() < system->maxMasters());
1197 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
1207 assert(pkt->req->masterId() < system->maxMasters());
1208 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
H A Dcache.cc337 mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
384 pkt->req->masterId());
778 assert(tgt_pkt->req->masterId() < system->maxMasters());
779 missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
H A Dbase.cc275 assert(pkt->req->masterId() < system->maxMasters());
276 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
299 assert(pkt->req->masterId() < system->maxMasters());
300 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
448 assert(pkt->req->masterId() < system->maxMasters());
449 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
452 assert(pkt->req->masterId() < system->maxMasters());
453 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
781 assert(pkt->req->masterId() < system->maxMasters());
782 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]
[all...]
/gem5/src/mem/cache/prefetch/
H A Dqueued.cc294 masterId, tagPrefetch, pf_time);
345 addr, blkSize, pkt->req->getFlags(), masterId, pfi.getPC(),
434 dpp.createPkt(target_paddr, blkSize, masterId, tagPrefetch, pf_time);
/gem5/src/dev/
H A Ddma_device.cc60 device(dev), sys(s), masterId(s->getMasterId(dev)),
174 gen.addr(), gen.size(), flag, masterId);
H A Ddma_device.hh121 const MasterID masterId; member in class:DmaPort
/gem5/src/mem/
H A Ddram_ctrl.hh707 inline MasterID masterId() const { return _masterId; } function in class:DRAMCtrl::DRAMPacket
738 _masterId(pkt->masterId()),
H A Ddram_ctrl.cc434 masterReadAccesses[pkt->masterId()]++;
488 logRequest(MemCtrl::READ, pkt->masterId(), pkt->qosValue(),
532 masterWriteAccesses[pkt->masterId()]++;
553 logRequest(MemCtrl::WRITE, pkt->masterId(), pkt->qosValue(),
1313 masterReadTotalLat[dram_pkt->masterId()] +=
1318 masterReadBytes[dram_pkt->masterId()] += dram_pkt->size;
1325 masterWriteBytes[dram_pkt->masterId()] += dram_pkt->size;
1326 masterWriteTotalLat[dram_pkt->masterId()] +=
1492 logResponse(MemCtrl::READ, (*to_read)->masterId(),
1592 logResponse(MemCtrl::WRITE, dram_pkt->masterId(),
[all...]
H A Dpacket.hh714 inline MasterID masterId() const { return req->masterId(); } function
/gem5/src/mem/qos/
H A Dmem_ctrl.cc232 return schedule(pkt->req->masterId(), pkt->getSize());
/gem5/src/mem/cache/tags/
H A Dbase.cc109 MasterID master_id = pkt->req->masterId();
/gem5/src/arch/hsail/insts/
H A Dmem.hh466 gpuDynInst->computeUnit()->masterId(),
593 gpuDynInst->computeUnit()->masterId(),
1019 gpuDynInst->computeUnit()->masterId(),
1071 gpuDynInst->computeUnit()->masterId(),
1493 gpuDynInst->computeUnit()->masterId(),
1626 gpuDynInst->computeUnit()->masterId(),
1680 gpuDynInst->computeUnit()->masterId(),
/gem5/src/arch/x86/
H A Dpagetable_walker.cc524 nextRead, oldRead->getSize(), flags, walker->masterId);
593 topAddr, dataSize, flags, walker->masterId);
/gem5/util/tlm/src/
H A Dsc_master_port.cc52 owner.masterId);

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