16899SN/A/* 29542Sandreas.hansson@arm.com * Copyright (c) 2013 ARM Limited 39542Sandreas.hansson@arm.com * All rights reserved 49542Sandreas.hansson@arm.com * 59542Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69542Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79542Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89542Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99542Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109542Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119542Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129542Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139542Sandreas.hansson@arm.com * 146899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 156899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 166899SN/A * All rights reserved. 176899SN/A * 186899SN/A * Redistribution and use in source and binary forms, with or without 196899SN/A * modification, are permitted provided that the following conditions are 206899SN/A * met: redistributions of source code must retain the above copyright 216899SN/A * notice, this list of conditions and the following disclaimer; 226899SN/A * redistributions in binary form must reproduce the above copyright 236899SN/A * notice, this list of conditions and the following disclaimer in the 246899SN/A * documentation and/or other materials provided with the distribution; 256899SN/A * neither the name of the copyright holders nor the names of its 266899SN/A * contributors may be used to endorse or promote products derived from 276899SN/A * this software without specific prior written permission. 286899SN/A * 296899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406899SN/A */ 416899SN/A 427053SN/A#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__ 437053SN/A#define __CPU_RUBYTEST_RUBYTESTER_HH__ 446899SN/A 457055SN/A#include <iostream> 468229Snate@binkert.org#include <string> 477454SN/A#include <vector> 487055SN/A 497632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/CheckTable.hh" 508229Snate@binkert.org#include "mem/packet.hh" 5113892Sgabeblack@google.com#include "mem/port.hh" 5211017Snilay@cs.wisc.edu#include "mem/ruby/common/SubBlock.hh" 5311017Snilay@cs.wisc.edu#include "mem/ruby/common/TypeDefines.hh" 546899SN/A#include "params/RubyTester.hh" 5513892Sgabeblack@google.com#include "sim/clocked_object.hh" 566899SN/A 5713892Sgabeblack@google.comclass RubyTester : public ClockedObject 586899SN/A{ 597053SN/A public: 608922Swilliam.wang@arm.com class CpuPort : public MasterPort 617053SN/A { 627053SN/A private: 637053SN/A RubyTester *tester; 6411266SBrad.Beckmann@amd.com // index for m_last_progress_vector and hitCallback 6511266SBrad.Beckmann@amd.com PortID globalIdx; 666899SN/A 677053SN/A public: 688932SBrad.Beckmann@amd.com // 698932SBrad.Beckmann@amd.com // Currently, each instatiation of the RubyTester::CpuPort supports 708932SBrad.Beckmann@amd.com // only instruction or data requests, not both. However, for those 718932SBrad.Beckmann@amd.com // RubyPorts that support both types of requests, separate InstOnly 728932SBrad.Beckmann@amd.com // and DataOnly CpuPorts will map to that RubyPort 738932SBrad.Beckmann@amd.com 7411266SBrad.Beckmann@amd.com CpuPort(const std::string &_name, RubyTester *_tester, PortID _id, 7511266SBrad.Beckmann@amd.com PortID _index) 7611266SBrad.Beckmann@amd.com : MasterPort(_name, _tester, _id), tester(_tester), 7711266SBrad.Beckmann@amd.com globalIdx(_index) 787053SN/A {} 796899SN/A 807053SN/A protected: 818975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 8210713Sandreas.hansson@arm.com virtual void recvReqRetry() 838922Swilliam.wang@arm.com { panic("%s does not expect a retry\n", name()); } 847053SN/A }; 856899SN/A 867053SN/A struct SenderState : public Packet::SenderState 877053SN/A { 889542Sandreas.hansson@arm.com SubBlock subBlock; 896899SN/A 9011025Snilay@cs.wisc.edu SenderState(Addr addr, int size) : subBlock(addr, size) {} 916899SN/A 927053SN/A }; 936899SN/A 947053SN/A typedef RubyTesterParams Params; 957053SN/A RubyTester(const Params *p); 967053SN/A ~RubyTester(); 976899SN/A 9813784Sgabeblack@google.com Port &getPort(const std::string &if_name, 9913784Sgabeblack@google.com PortID idx=InvalidPortID) override; 1006899SN/A 10111266SBrad.Beckmann@amd.com bool isInstOnlyCpuPort(int idx); 10211266SBrad.Beckmann@amd.com bool isInstDataCpuPort(int idx); 1038950Sandreas.hansson@arm.com 1048932SBrad.Beckmann@amd.com MasterPort* getReadableCpuPort(int idx); 1058932SBrad.Beckmann@amd.com MasterPort* getWritableCpuPort(int idx); 1066899SN/A 10713799SAndrea.Mondelli@ucf.edu void init() override; 1086899SN/A 1097053SN/A void wakeup(); 1106899SN/A 1117053SN/A void incrementCheckCompletions() { m_checks_completed++; } 1126899SN/A 1137055SN/A void printStats(std::ostream& out) const {} 1147053SN/A void clearStats() {} 1157055SN/A void printConfig(std::ostream& out) const {} 1166899SN/A 1177055SN/A void print(std::ostream& out) const; 1188184Ssomayeh@cs.wisc.edu bool getCheckFlush() { return m_check_flush; } 1196899SN/A 1208832SAli.Saidi@ARM.com MasterID masterId() { return _masterId; } 1217053SN/A protected: 12212129Sspwilson2@wisc.edu EventFunctionWrapper checkStartEvent; 1237053SN/A 1248832SAli.Saidi@ARM.com MasterID _masterId; 1258832SAli.Saidi@ARM.com 1266899SN/A private: 1277053SN/A void hitCallback(NodeID proc, SubBlock* data); 1286899SN/A 1297053SN/A void checkForDeadlock(); 1306899SN/A 1317053SN/A // Private copy constructor and assignment operator 1327053SN/A RubyTester(const RubyTester& obj); 1337053SN/A RubyTester& operator=(const RubyTester& obj); 1346899SN/A 1357053SN/A CheckTable* m_checkTable_ptr; 13610302Snilay@cs.wisc.edu std::vector<Cycles> m_last_progress_vector; 1376899SN/A 1388932SBrad.Beckmann@amd.com int m_num_cpus; 13911061Snilay@cs.wisc.edu uint64_t m_checks_completed; 1408950Sandreas.hansson@arm.com std::vector<MasterPort*> writePorts; 1418950Sandreas.hansson@arm.com std::vector<MasterPort*> readPorts; 14211061Snilay@cs.wisc.edu uint64_t m_checks_to_complete; 1437053SN/A int m_deadlock_threshold; 1448932SBrad.Beckmann@amd.com int m_num_writers; 1458932SBrad.Beckmann@amd.com int m_num_readers; 1467053SN/A int m_wakeup_frequency; 1478184Ssomayeh@cs.wisc.edu bool m_check_flush; 14811266SBrad.Beckmann@amd.com int m_num_inst_only_ports; 14911266SBrad.Beckmann@amd.com int m_num_inst_data_ports; 1506899SN/A}; 1516899SN/A 1527055SN/Ainline std::ostream& 1537055SN/Aoperator<<(std::ostream& out, const RubyTester& obj) 1546899SN/A{ 1557053SN/A obj.print(out); 1567055SN/A out << std::flush; 1577053SN/A return out; 1586899SN/A} 1596899SN/A 1607053SN/A#endif // __CPU_RUBYTEST_RUBYTESTER_HH__ 161