/gem5/ext/dsent/model/network/ |
H A D | PhotonicClos.cc | 421 double delay = 1.0 / clock_freq; local 425 double input_to_ingress_link_delay = delay * 0.8; 429 double egress_to_output_link_delay = delay * 0.8; 430 double ingress_router_delay = delay; 431 double middle_router_delay = delay; 432 double egress_router_delay = delay;
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/gem5/src/dev/net/ |
H A D | dist_iface.cc | 450 // sanity check (we need atleast a send delay long window) 453 "Receive window is smaller than send delay"); 467 // Schedule pending packets asap in case link speed/delay changed when 824 DistIface::readyToCkpt(Tick delay, Tick period) argument 827 DPRINTF(DistEthernet, "DistIface::readyToCkpt() called, delay:%lu " 828 "period:%lu\n", delay, period); 830 if (delay == 0) { 831 inform("m5 checkpoint called with zero delay => triggering collaborative " 835 inform("m5 checkpoint called with non-zero delay => triggering immediate " 898 DistIface::readyToExit(Tick delay) argument [all...] |
H A D | etherswitch.hh | 75 uint64_t outputBufferSize, Tick delay, Tick delay_var,
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H A D | dist_iface.hh | 68 * transmission delay to ensure that a corresponding receive event can always 376 * The link delay in ticks for the simulated Ethernet link. 393 * @param send_delay The simulated delay at the sender side. 450 * @note Link speed and delay parameters may change at resume. 559 * @param link_delay The link delay for the simulated Ethernet link. 589 * @param send_delay The delay in ticks for the send completion event. 611 * @param delay Delay param from the m5 exit command. If Delay is zero 619 static bool readyToExit(Tick delay); 622 * @param delay Delay param from the m5 checkpoint command. If Delay is 630 static bool readyToCkpt(Tick delay, Tic [all...] |
/gem5/src/cpu/minor/ |
H A D | buffers.hh | 225 Cycles delay; member in class:Minor::Latch 230 /** forward/backwardDelay specify the delay from input to output in each 236 delay(delay_), 244 * pipeline. Latched and Immediate specify delay for backward data. 275 Output output() { return Output(buffer.getWire(-delay)); }
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | AbstractController.cc | 103 AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay) argument 106 m_delayHistogram.sample(delay); 107 m_delayVCHistogram[virtualNetwork]->sample(delay);
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H A D | AbstractController.hh | 174 //! Profiles the delay associated with messages. 175 void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 211 //! Histogram for profiling delay for the messages this controller
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | base.cc | 307 // remember how much delay was incurred due to back-pressure 310 Tick delay = curTick() - retryPktTick; local 312 stats.retryTicks += delay; 317 delay);
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/gem5/configs/example/arm/ |
H A D | dist_bigLITTLE.py | 92 help="Link delay in seconds\nDEFAULT: 10us") 110 delay = options.ethernet_linkdelay,
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H A D | devices.py | 214 self.iobridge = Bridge(delay='50ns') 223 self.dmabridge = Bridge(delay='50ns',
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/gem5/src/systemc/tlm_bridge/ |
H A D | tlm_to_gem5.hh | 134 sc_core::sc_time &delay);
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/gem5/src/arch/arm/ |
H A D | tlb.cc | 566 Translation *translation, bool &delay, bool timing) 1037 Translation *translation, bool &delay, bool timing, 1145 if ((te == NULL) && (fault == NoFault)) delay = true; 1210 bool delay = false; local 1213 fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 1215 fault = translateSe(req, tc, mode, NULL, delay, false); 1216 assert(!delay); 1231 bool delay = false; local 1234 fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 1236 fault = translateSe(req, tc, mode, NULL, delay, fals 565 translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) argument 1036 translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) argument 1263 bool delay = false; local [all...] |
H A D | tlb.hh | 355 Translation *translation, bool &delay, 358 Translation *translation, bool &delay, bool timing);
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/gem5/ext/mcpat/cacti/ |
H A D | crossbar.cc | 152 // delay calculation 159 delay = horowitz(w1.signal_rise_time(), res * cap, deviceType->Vth / 176 cout << "Crossbar Delay : " << delay*1e12 << " ps\n";
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H A D | component.cc | 49 : area(), power(), rt_power(), delay(0) {
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H A D | Ucache.cc | 77 min_delay = (min_delay > res->nuca_pda.delay) ? res->nuca_pda.delay : min_delay; 278 ptr_array->delay_route_to_bank = uca->htree_in_add->delay; 279 ptr_array->delay_input_htree = uca->bank.htree_in_add->delay; 281 uca->bank.mat.r_predec->delay; 282 ptr_array->delay_row_decoder = uca->bank.mat.row_dec->delay; 288 ptr_array->delay_dout_htree = uca->bank.htree_out_data->delay; 686 * 3. Cache area, delay, power, and cycle time for different 729 // If it's a cache, first calculate the area, delay and power for all tag array partitions. 764 // calculate the area, delay an [all...] |
/gem5/src/mem/qos/ |
H A D | mem_ctrl.cc | 145 Addr addr, uint64_t entries, double delay) 189 double latency = (double) (curTick() + delay - requestTime) 144 logResponse(BusState dir, MasterID m_id, uint8_t qos, Addr addr, uint64_t entries, double delay) argument
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/gem5/src/dev/arm/ |
H A D | smmu_v3_slaveifc.cc | 136 return a.delay; 186 return a.delay;
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H A D | smmu_v3.cc | 236 Tick delay = 0; local 248 delay += masterTableWalkPort.sendAtomic(action.pkt); 254 delay += masterPort.sendAtomic(action.pkt); 265 delay += action.delay; 276 action.delay = delay;
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H A D | gic_v3_its.cc | 101 a.delay = 0; 125 a.delay = 0; 141 a.delay = 0; 342 a.delay = 0; 1194 Tick delay = 0; local 1202 delay += dmaPort.sendAtomic(action.pkt); 1217 action.delay = delay;
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/gem5/src/cpu/kvm/ |
H A D | base.cc | 183 Tick delay = sendAtomic(pkt); local 185 return delay; 619 Tick delay(0); 625 delay = handleKvmExit(); 660 delay = kvmRunDrain(); 662 delay = kvmRun(ticksToExecute); 705 schedule(tickEvent, clockEdge(ticksToCycles(delay)));
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/gem5/configs/common/ |
H A D | FSConfig.py | 114 self.bridge = Bridge(delay='50ns', 161 self.bridge = Bridge(delay='50ns') 226 self.bridge = Bridge(delay='50ns') 412 self.bridge = Bridge(delay='50ns') 455 x86_sys.bridge = Bridge(delay='50ns') 475 x86_sys.apicbridge = Bridge(delay='50ns') 697 delay = linkdelay,
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/gem5/src/mem/ |
H A D | comm_monitor.cc | 352 const Tick delay(masterPort.sendAtomic(pkt)); 356 stats.updateRespStats(req_pkt_info, delay, true); 362 return delay;
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/gem5/src/cpu/o3/ |
H A D | cpu.hh | 143 void scheduleTickEvent(Cycles delay) argument 146 reschedule(tickEvent, clockEdge(delay)); 148 schedule(tickEvent, clockEdge(delay)); 517 * There's also an option to not squash delay slot instructions.*/
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.cc | 199 // compute the delay cycles and set enqueue time 234 // get the delay cycles 236 Tick delay = message->getDelayedTicks(); local 261 return delay;
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