110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT/CACTI 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu#include "crossbar.h" 3410152Satgutier@umich.edu 3510152Satgutier@umich.edu#define ASPECT_THRESHOLD .8 3610152Satgutier@umich.edu#define ADJ 1 3710152Satgutier@umich.edu 3810152Satgutier@umich.eduCrossbar::Crossbar( 3910152Satgutier@umich.edu double n_inp_, 4010152Satgutier@umich.edu double n_out_, 4110152Satgutier@umich.edu double flit_size_, 4210152Satgutier@umich.edu TechnologyParameter::DeviceType *dt 4310234Syasuko.eckert@amd.com): n_inp(n_inp_), n_out(n_out_), flit_size(flit_size_), deviceType(dt) { 4410234Syasuko.eckert@amd.com min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; 4510234Syasuko.eckert@amd.com Vdd = dt->Vdd; 4610234Syasuko.eckert@amd.com CB_ADJ = 1; 4710152Satgutier@umich.edu} 4810152Satgutier@umich.edu 4910234Syasuko.eckert@amd.comCrossbar::~Crossbar() {} 5010152Satgutier@umich.edu 5110234Syasuko.eckert@amd.comdouble Crossbar::output_buffer() { 5210152Satgutier@umich.edu 5310234Syasuko.eckert@amd.com //Wire winit(4, 4); 5410234Syasuko.eckert@amd.com double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; 5510234Syasuko.eckert@amd.com Wire w1(g_ip->wt, l_eff); 5610234Syasuko.eckert@amd.com //double s1 = w1.repeater_size *l_eff*ADJ/w1.repeater_spacing; 5710234Syasuko.eckert@amd.com double s1 = w1.repeater_size * (l_eff < w1.repeater_spacing ? 5810234Syasuko.eckert@amd.com l_eff * ADJ / w1.repeater_spacing : ADJ); 5910234Syasuko.eckert@amd.com double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; 6010234Syasuko.eckert@amd.com // the model assumes input capacitance of the wire driver = input capacitance of nand + nor = input cap of the driver transistor 6110234Syasuko.eckert@amd.com TriS1 = s1 * (1 + pton_size) / (2 + pton_size + 1 + 2 * pton_size); 6210234Syasuko.eckert@amd.com TriS2 = s1; //driver transistor 6310152Satgutier@umich.edu 6410234Syasuko.eckert@amd.com if (TriS1 < 1) 6510234Syasuko.eckert@amd.com TriS1 = 1; 6610152Satgutier@umich.edu 6710234Syasuko.eckert@amd.com double input_cap = gate_C(TriS1 * (2 * min_w_pmos + g_tp.min_w_nmos_), 0) + 6810234Syasuko.eckert@amd.com gate_C(TriS1 * (min_w_pmos + 2 * g_tp.min_w_nmos_), 0); 6910152Satgutier@umich.edu// input_cap += drain_C_(TriS1*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + 7010152Satgutier@umich.edu// drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 + 7110152Satgutier@umich.edu// gate_C(TriS2*g_tp.min_w_nmos_, 0)+ 7210152Satgutier@umich.edu// drain_C_(TriS1*min_w_pmos, NCH, 1, 1, g_tp.cell_h_def)*2 + 7310152Satgutier@umich.edu// drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + 7410152Satgutier@umich.edu// gate_C(TriS2*min_w_pmos, 0); 7510234Syasuko.eckert@amd.com tri_int_cap = drain_C_(TriS1 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + 7610234Syasuko.eckert@amd.com drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 + 7710234Syasuko.eckert@amd.com gate_C(TriS2 * g_tp.min_w_nmos_, 0) + 7810234Syasuko.eckert@amd.com drain_C_(TriS1 * min_w_pmos, NCH, 1, 1, g_tp.cell_h_def) * 2 + 7910234Syasuko.eckert@amd.com drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + 8010234Syasuko.eckert@amd.com gate_C(TriS2 * min_w_pmos, 0); 8110234Syasuko.eckert@amd.com double output_cap = drain_C_(TriS2 * g_tp.min_w_nmos_, NCH, 1, 1, 8210234Syasuko.eckert@amd.com g_tp.cell_h_def) + 8310234Syasuko.eckert@amd.com drain_C_(TriS2 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def); 8410234Syasuko.eckert@amd.com double ctr_cap = gate_C(TriS2 * (min_w_pmos + g_tp.min_w_nmos_), 0); 8510152Satgutier@umich.edu 8610234Syasuko.eckert@amd.com tri_inp_cap = input_cap; 8710234Syasuko.eckert@amd.com tri_out_cap = output_cap; 8810234Syasuko.eckert@amd.com tri_ctr_cap = ctr_cap; 8910234Syasuko.eckert@amd.com return input_cap + output_cap + ctr_cap; 9010152Satgutier@umich.edu} 9110152Satgutier@umich.edu 9210234Syasuko.eckert@amd.comvoid Crossbar::compute_power() { 9310152Satgutier@umich.edu 9410234Syasuko.eckert@amd.com Wire winit(4, 4); 9510234Syasuko.eckert@amd.com double tri_cap = output_buffer(); 9610234Syasuko.eckert@amd.com assert(tri_cap > 0); 9710234Syasuko.eckert@amd.com //area of a tristate logic 9810234Syasuko.eckert@amd.com double g_area = compute_gate_area(INV, 1, TriS2 * g_tp.min_w_nmos_, 9910234Syasuko.eckert@amd.com TriS2 * min_w_pmos, g_tp.cell_h_def); 10010234Syasuko.eckert@amd.com g_area *= 2; // to model area of output transistors 10110234Syasuko.eckert@amd.com g_area += compute_gate_area (NAND, 2, TriS1 * 2 * g_tp.min_w_nmos_, 10210234Syasuko.eckert@amd.com TriS1 * min_w_pmos, g_tp.cell_h_def); 10310234Syasuko.eckert@amd.com g_area += compute_gate_area (NOR, 2, TriS1 * g_tp.min_w_nmos_, 10410234Syasuko.eckert@amd.com TriS1 * 2 * min_w_pmos, g_tp.cell_h_def); 10510234Syasuko.eckert@amd.com double width /*per tristate*/ = g_area / (CB_ADJ * g_tp.cell_h_def); 10610234Syasuko.eckert@amd.com // effective no. of tristate buffers that need to be laid side by side 10710234Syasuko.eckert@amd.com int ntri = (int)ceil(g_tp.cell_h_def / (g_tp.wire_outside_mat.pitch)); 10810234Syasuko.eckert@amd.com double wire_len = MAX(width * ntri * n_out, 10910234Syasuko.eckert@amd.com flit_size * g_tp.wire_outside_mat.pitch * n_out); 11010234Syasuko.eckert@amd.com Wire w1(g_ip->wt, wire_len); 11110152Satgutier@umich.edu 11210234Syasuko.eckert@amd.com area.w = wire_len; 11310234Syasuko.eckert@amd.com area.h = g_tp.wire_outside_mat.pitch * n_inp * flit_size * CB_ADJ; 11410234Syasuko.eckert@amd.com Wire w2(g_ip->wt, area.h); 11510152Satgutier@umich.edu 11610234Syasuko.eckert@amd.com double aspect_ratio_cb = (area.h / area.w) * (n_out / n_inp); 11710234Syasuko.eckert@amd.com if (aspect_ratio_cb > 1) aspect_ratio_cb = 1 / aspect_ratio_cb; 11810152Satgutier@umich.edu 11910234Syasuko.eckert@amd.com if (aspect_ratio_cb < ASPECT_THRESHOLD) { 12010234Syasuko.eckert@amd.com if (n_out > 2 && n_inp > 2) { 12110234Syasuko.eckert@amd.com CB_ADJ += 0.2; 12210234Syasuko.eckert@amd.com //cout << "CB ADJ " << CB_ADJ << endl; 12310234Syasuko.eckert@amd.com if (CB_ADJ < 4) { 12410234Syasuko.eckert@amd.com this->compute_power(); 12510234Syasuko.eckert@amd.com } 12610234Syasuko.eckert@amd.com } 12710152Satgutier@umich.edu } 12810152Satgutier@umich.edu 12910152Satgutier@umich.edu 13010152Satgutier@umich.edu 13110234Syasuko.eckert@amd.com power.readOp.dynamic = 13210234Syasuko.eckert@amd.com (w1.power.readOp.dynamic + w2.power.readOp.dynamic + 13310234Syasuko.eckert@amd.com (tri_inp_cap * n_out + tri_out_cap * n_inp + tri_ctr_cap + 13410234Syasuko.eckert@amd.com tri_int_cap) * Vdd * Vdd) * flit_size; 13510234Syasuko.eckert@amd.com power.readOp.leakage = n_inp * n_out * flit_size * ( 13610234Syasuko.eckert@amd.com cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2, 13710234Syasuko.eckert@amd.com 1, inv) * Vdd + 13810234Syasuko.eckert@amd.com cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 13910234Syasuko.eckert@amd.com 2, nand) * Vdd + 14010234Syasuko.eckert@amd.com cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 14110234Syasuko.eckert@amd.com 2, nor) * Vdd + 14210234Syasuko.eckert@amd.com w1.power.readOp.leakage + w2.power.readOp.leakage); 14310234Syasuko.eckert@amd.com power.readOp.gate_leakage = n_inp * n_out * flit_size * ( 14410234Syasuko.eckert@amd.com cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2, 14510234Syasuko.eckert@amd.com 1, inv) * Vdd + 14610234Syasuko.eckert@amd.com cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 14710234Syasuko.eckert@amd.com 2, nand) * Vdd + 14810234Syasuko.eckert@amd.com cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 14910234Syasuko.eckert@amd.com 2, nor) * Vdd + 15010234Syasuko.eckert@amd.com w1.power.readOp.gate_leakage + w2.power.readOp.gate_leakage); 15110152Satgutier@umich.edu 15210234Syasuko.eckert@amd.com // delay calculation 15310234Syasuko.eckert@amd.com double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; 15410234Syasuko.eckert@amd.com Wire wdriver(g_ip->wt, l_eff); 15510234Syasuko.eckert@amd.com double res = g_tp.wire_outside_mat.R_per_um * (area.w + area.h) + 15610234Syasuko.eckert@amd.com tr_R_on(g_tp.min_w_nmos_ * wdriver.repeater_size, NCH, 1); 15710234Syasuko.eckert@amd.com double cap = g_tp.wire_outside_mat.C_per_um * (area.w + area.h) + n_out * 15810234Syasuko.eckert@amd.com tri_inp_cap + n_inp * tri_out_cap; 15910234Syasuko.eckert@amd.com delay = horowitz(w1.signal_rise_time(), res * cap, deviceType->Vth / 16010234Syasuko.eckert@amd.com deviceType->Vdd, deviceType->Vth / deviceType->Vdd, RISE); 16110152Satgutier@umich.edu 16210234Syasuko.eckert@amd.com Wire wreset(); 16310152Satgutier@umich.edu} 16410152Satgutier@umich.edu 16510234Syasuko.eckert@amd.comvoid Crossbar::print_crossbar() { 16610234Syasuko.eckert@amd.com cout << "\nCrossbar Stats (" << n_inp << "x" << n_out << ")\n\n"; 16710234Syasuko.eckert@amd.com cout << "Flit size : " << flit_size << " bits" << endl; 16810234Syasuko.eckert@amd.com cout << "Width : " << area.w << " u" << endl; 16910234Syasuko.eckert@amd.com cout << "Height : " << area.h << " u" << endl; 17010234Syasuko.eckert@amd.com cout << "Dynamic Power : " << power.readOp.dynamic*1e9 * 17110234Syasuko.eckert@amd.com MIN(n_inp, n_out) << " (nJ)" << endl; 17210234Syasuko.eckert@amd.com cout << "Leakage Power : " << power.readOp.leakage*1e3 << " (mW)" 17310234Syasuko.eckert@amd.com << endl; 17410234Syasuko.eckert@amd.com cout << "Gate Leakage Power : " << power.readOp.gate_leakage*1e3 17510234Syasuko.eckert@amd.com << " (mW)" << endl; 17610234Syasuko.eckert@amd.com cout << "Crossbar Delay : " << delay*1e12 << " ps\n"; 17710152Satgutier@umich.edu} 17810152Satgutier@umich.edu 17910152Satgutier@umich.edu 180