Searched refs:clock (Results 251 - 275 of 302) sorted by relevance

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/gem5/src/systemc/tests/systemc/kernel/process_control/test02/
H A Dtest02.cpp190 sc_clock clock; local
194 dut.m_clk(clock);
/gem5/src/systemc/tests/systemc/kernel/reset_signal_is/test05/
H A Dtest05.cpp211 sc_clock clock; local
214 dut.m_clk(clock);
/gem5/src/systemc/tests/systemc/kernel/sc_process_handle/test01/
H A Dtest01.cpp153 sc_clock clock; local
158 dut.m_clk(clock);
/gem5/configs/example/
H A Druby_direct_test.py96 # Create a top-level voltage domain and clock domain
99 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
108 # Since Ruby runs at an independent frequency, create a seperate clock
109 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Druby_random_test.py106 # Create a top-level voltage domain and clock domain
109 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
114 # Create a seperate clock domain for Ruby
115 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Dhmc_hello.py55 # set the clock fequency of the system
58 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
H A Druby_gpu_random_test.py132 # Create a top-level voltage domain and clock domain
135 system.clk_domain = SrcClockDomain(clock=options.sys_clock,
140 # Create a seperate clock domain for Ruby
141 system.ruby.clk_domain = SrcClockDomain(clock=options.ruby_clock,
H A Dgarnet_synth_traffic.py120 # Create a top-level voltage domain and clock domain
123 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
128 # Create a seperate clock domain for Ruby
129 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
/gem5/tests/configs/
H A Dgpu-randomtest-ruby.py92 # We set the testers as cpu for ruby to find the correct clock domains
96 # Dummy voltage domain for all our clock domains
98 system.clk_domain = SrcClockDomain(clock = '1GHz',
105 # Create a separate clock domain for Ruby
106 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
H A Dgpu-ruby.py123 help="CPU clock")
125 help="GPU clock")
175 clock = options.GPUClock, variable
266 # Dummy voltage domain for all our clock domains
268 system.clk_domain = SrcClockDomain(clock = '1GHz',
271 # Create a seperate clock domain for components that should run at
273 system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz',
285 # Create a separate clock for Ruby
286 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
/gem5/ext/sst/
H A DExtMaster.hh105 void clock();
H A DExtMaster.cc115 ExtMaster::clock(void) function in class:ExtMaster
117 nic->clock();
/gem5/src/systemc/tests/systemc/1666-2011-compliance/async_reset/
H A Dasync_reset.cpp118 clock();
123 clock();
127 clock();
131 clock();
143 clock();
151 clock(); // Clocked while asynch reset is active
155 clock();
175 clock();
187 clock();
192 clock();
510 void clock() function in struct:Top
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/gem5/src/dev/arm/
H A Dtimer_sp804.cc58 : _name(__name), parent(_parent), intNum(int_num), clock(_clock), control(0x20),
92 DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
93 zeroEvent.when(), clock, control.timerPrescale);
96 time = time / clock / power(16, control.timerPrescale);
182 Tick time = clock * power(16, control.timerPrescale);
/gem5/tests/gem5/memory/
H A Dsimple-run.py70 clk_domain = SrcClockDomain(clock = '1GHz',
/gem5/configs/learning_gem5/part3/
H A Dsimple_ruby.py59 # Set the clock fequency of the system (and all of its children)
61 system.clk_domain.clock = '1GHz'
/gem5/src/systemc/tests/systemc/kernel/process_control/disable_enable/test1/
H A Dtest1.cpp193 sc_clock clock( "clock", 1.0, SC_NS );
196 top_p->m_clk(clock);
/gem5/src/systemc/tests/systemc/kernel/process_control/disable_enable/test2/
H A Dtest2.cpp214 sc_clock clock( "clock", 2.0, SC_NS );
217 top_p->m_clk(clock);
/gem5/src/systemc/tests/systemc/kernel/process_control/suspend_resume/test1/
H A Dtest1.cpp207 sc_clock clock( "clock", 1.0, SC_NS );
210 top_p->m_clk(clock);
/gem5/src/systemc/tests/systemc/kernel/process_control/suspend_resume/test2/
H A Dtest2.cpp228 sc_clock clock( "clock", 2.0, SC_NS );
231 top_p->m_clk(clock);
/gem5/src/systemc/tests/systemc/kernel/process_control/test01/
H A Dtest01.cpp217 sc_clock clock; local
221 dut.m_clk(clock);
/gem5/configs/common/
H A DGPUTLBConfig.py53 clock = options.GPUClock,\
65 clock = options.GPUClock,\
/gem5/src/systemc/tests/systemc/datatypes/misc/concat/test05/
H A Dtest05.cpp20 sc_clock clock; local
/gem5/configs/learning_gem5/part1/
H A Dsimple.py52 # Set the clock fequency of the system (and all of its children)
54 system.clk_domain.clock = '1GHz'
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py47 # Set the clock fequency of the system (and all of its children)
49 system.clk_domain.clock = '1GHz'

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