| /gem5/src/systemc/tests/systemc/kernel/phase_callbacks/test02/ |
| H A D | test02.cpp | 34 sc_clock clock; local
38 x.clk(clock);
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| /gem5/src/systemc/tests/systemc/kernel/process_control/test05/ |
| H A D | test05.cpp | 103 sc_clock clock; local
106 dut.m_clk(clock);
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| /gem5/src/systemc/tests/systemc/kernel/sc_name_gen/test1/ |
| H A D | test1.cpp | 75 sc_clock clock; local
76 a.m_clk(clock);
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| /gem5/src/systemc/tests/systemc/kernel/sc_object_manager/test02/ |
| H A D | test02.cpp | 79 sc_clock clock; local
83 dut.m_clk(clock);
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| /gem5/src/systemc/tests/systemc/kernel/sc_process_handle/test02/ |
| H A D | test02.cpp | 83 sc_clock clock; local
86 dut.m_clk(clock);
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| /gem5/src/systemc/tests/systemc/kernel/sc_stop/test01/ |
| H A D | test01.cpp | 87 sc_clock clock; local
89 x.clk(clock);
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| /gem5/src/systemc/tests/systemc/kernel/sc_stop/test02/ |
| H A D | test02.cpp | 87 sc_clock clock; local
89 x.clk(clock);
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| /gem5/tests/configs/ |
| H A D | o3-timing-mp-ruby.py | 41 clk_domain = SrcClockDomain(clock = '1GHz'))
43 # Create a seperate clock domain for components that should run at
45 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
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| H A D | simple-atomic-mp-ruby.py | 40 clk_domain = SrcClockDomain(clock = '1GHz'))
42 # Create a seperate clock domain for components that should run at
44 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
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| H A D | t1000-simple-atomic.py | 40 system.clk_domain = SrcClockDomain(clock = '1GHz',
42 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
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| H A D | simple-timing-ruby.py | 66 # Dummy voltage domain for all our clock domains
68 system.clk_domain = SrcClockDomain(clock = '1GHz',
71 # Create a seperate clock domain for components that should run at
73 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
79 # Create a separate clock for Ruby
80 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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| H A D | simple-timing-mp-ruby.py | 68 system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
70 # Create a seperate clock domain for components that should run at
72 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
76 # Create a separate clock domain for Ruby
77 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
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| /gem5/src/sim/ |
| H A D | ClockDomain.py | 44 # Abstract clock domain
50 # Source clock domain with an actual clock, and a list of voltage and frequency
56 # Single clock frequency value, or list of frequencies for DVFS
59 clock = VectorParam.Clock("Clock period") variable in class:SrcClockDomain
61 # A source clock must be associated with a voltage domain
75 # Derived clock domain with a parent clock domain and a frequency
80 clk_domain = Param.ClockDomain("Parent clock domain")
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| /gem5/src/systemc/tests/systemc/kernel/sc_object_manager/test01/ |
| H A D | test01.cpp | 90 sc_clock clock; local
94 module_a.m_clk(clock);
95 tb.m_clk(clock);
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| /gem5/src/systemc/tests/systemc/misc/communication/channel/test1/ |
| H A D | test1.cpp | 127 sc_clock clock("CLK", 20, SC_NS);
129 proc1 p1("P1", clock, c);
130 proc2 p2("P2", clock, c);
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| /gem5/src/systemc/tests/systemc/misc/communication/channel/test2/ |
| H A D | test2.cpp | 129 sc_clock clock("CLK", 20, SC_NS);
131 proc1 p1("P1", clock, c);
132 proc2 p2("P2", clock, c);
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| /gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
| H A D | main.cpp | 112 // clock -------------------------------------------------------------------
113 sc_clock clock ("CLOCK", 40, SC_NS, 0.5); // assume 25MHz
134 clock,
153 clock,
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| /gem5/src/systemc/tests/systemc/misc/user_guide/async_chn/test2/ |
| H A D | test2.cpp | 115 sc_clock clock("Clock", 20, SC_NS);
117 p1 Proc1("Proc1", a, b, clock, 10);
118 p2 Proc2("Proc2", clock, b, a, 129);
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| /gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test4/ |
| H A D | test4.cpp | 77 sc_in<bool> clock; local
88 clock(CLOCK);
91 sensitive << clock; local
100 if (clock.posedge()) cout << "Posedge - ";
101 if (clock.negedge()) cout << "Negedge - ";
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| /gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test5/ |
| H A D | test5.cpp | 77 sc_in<bool> clock; local
88 clock(CLOCK);
91 sensitive << clock; local
100 if (clock.posedge()) cout << "Posedge - ";
101 if (clock.negedge()) cout << "Negedge - ";
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| /gem5/src/gpu-compute/ |
| H A D | tlb_coalescer.hh | 71 // TLB clock: will inherit clock from shader's clock period in terms
72 // of nuber of ticks of curTime (aka global simulation clock)
73 // The assignment of TLB clock from shader clock is done in the
75 int clock; member in class:TLBCoalescer
150 Tick frequency() const { return SimClock::Frequency / clock; }
151 Tick ticks(int numCycles) const { return (Tick)clock * numCycles; }
152 Tick curCycle() const { return curTick() / clock; }
[all...] |
| /gem5/src/systemc/tests/systemc/1666-2011-compliance/async_reset_port/ |
| H A D | async_reset_port.cpp | 231 clock();
235 clock();
239 clock();
243 clock();
247 clock();
251 clock();
255 clock();
262 clock();
266 clock();
273 clock();
315 void clock() function in struct:Top
[all...] |
| /gem5/src/systemc/tests/systemc/misc/communication/channel/hshake1/ |
| H A D | hshake1.cpp | 124 sc_clock clock("CLK", 20, SC_NS);
126 proc1 p1("P1", clock, c, a, d, b);
127 proc2 p2("P2", clock, d, b, c, a);
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| /gem5/src/systemc/tests/systemc/misc/communication/channel/hshake2/ |
| H A D | hshake2.cpp | 123 sc_clock clock("CLK", 20, SC_NS);
125 proc1 p1("P1", clock, c, a, d, b);
126 proc2 p2("P2", clock, d, b, c, a);
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| /gem5/src/systemc/tests/systemc/misc/communication/channel/test3/ |
| H A D | test3.cpp | 142 sc_clock clock("CLK", 20, SC_NS);
144 proc1 p1("P1", clock, c);
145 proc2 p2("P2", clock, c);
|