Searched refs:Addr (Results 426 - 450 of 767) sorted by relevance

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/gem5/src/arch/arm/
H A Dutility.hh232 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
234 Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
342 Addr truncPage(Addr addr);
343 Addr roundPage(Addr addr);
/gem5/src/cpu/o3/
H A Dfetch.hh319 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
326 checkInterrupt(Addr pc)
375 Addr fetchBufferAlignPC(Addr addr)
440 Addr fetchOffset[Impl::MaxThreads];
503 Addr fetchBufferMask;
509 Addr fetchBufferPC[Impl::MaxThreads];
/gem5/src/arch/generic/
H A Dtlb.hh90 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
152 void demapPage(Addr vaddr, uint64_t asn) override;
/gem5/src/dev/arm/
H A DGic.py98 dist_addr = Param.Addr("Address for distributor")
99 cpu_addr = Param.Addr("Address for cpu")
100 cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
125 addr = Param.Addr("Address for frame PIO")
140 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
141 hv_addr = Param.Addr(0, "Address for hv control")
208 dist_addr = Param.Addr("Address for distributor")
210 redist_addr = Param.Addr("Address for redistributors")
H A Dgic_v3.cc102 const Addr addr = pkt->getAddr();
109 const Addr daddr = addr - distRange.start();
117 Addr daddr = (addr - redistRange.start()) % redistSize;
141 const Addr addr = pkt->getAddr();
146 const Addr daddr = addr - distRange.start();
154 Addr daddr = (addr - redistRange.start()) % redistSize;
229 Gicv3::getRedistributorByAddr(Addr addr) const
234 const Addr daddr = addr - redistRange.start();
H A Dufs_device.hh439 Addr responseStartAddr;
443 Addr address;
455 Addr address;
467 Addr address;
479 Addr finalAddress;
490 Addr start;
877 uint32_t req_pos, Addr finaladdress, uint32_t finalsize);
895 request_in, int req_pos, Addr finaladdress,
919 void transferDone(Addr responseStartAddr, uint32_t req_pos,
921 Addr addres
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/gem5/src/dev/x86/
H A Di8254.cc55 Addr offset = pkt->getAddr() - pioAddr;
71 Addr offset = pkt->getAddr() - pioAddr;
/gem5/src/cpu/pred/
H A Dtage_sc_l.cc129 ThreadID tid, Addr pc, TAGEBase::BranchInfo* bi)
144 Addr t = (pc ^ (threadHistory[tid].pathHist &
171 TAGE_SC_L_TAGE::getUseAltIdx(TAGEBase::BranchInfo* bi, Addr branch_pc)
180 TAGE_SC_L_TAGE::gindex(ThreadID tid, Addr pc, int bank) const
223 TAGE_SC_L_TAGE::bindex(Addr pc) const
231 ThreadHistory& tHist, int brtype, bool taken, Addr branch_pc, Addr target)
266 ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b,
267 bool speculative, const StaticInstPtr &inst, Addr target)
290 Addr targe
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H A Dbi_mode.cc72 BiModeBP::uncondBranch(ThreadID tid, Addr pc, void * &bpHistory)
103 BiModeBP::lookup(ThreadID tid, Addr branchAddr, void * &bpHistory)
142 BiModeBP::btbUpdate(ThreadID tid, Addr branchAddr, void * &bpHistory)
154 BiModeBP::update(ThreadID tid, Addr branchAddr, bool taken, void *bpHistory,
155 bool squashed, const StaticInstPtr & inst, Addr corrTarget)
H A Dmultiperspective_perceptron_tage_8KB.cc72 MPP_StatisticalCorrector_8KB::getBiasLSUM(Addr branch_pc,
82 MPP_StatisticalCorrector_8KB::gPredictions(ThreadID tid, Addr branch_pc,
105 MPP_StatisticalCorrector_8KB::gUpdates(ThreadID tid, Addr pc, bool taken,
121 MPP_StatisticalCorrector_8KB::scHistoryUpdate(Addr branch_pc,
123 StatisticalCorrector::BranchInfo *bi, Addr corrTarget)
H A Dmultiperspective_perceptron_tage.cc53 MPP_TAGE::handleTAGEUpdate(Addr branch_pc, bool taken,
161 MPP_TAGE::bindex(Addr pc_in) const
169 MPP_TAGE::getUseAltIdx(TAGEBase::BranchInfo* bi, Addr branch_pc)
188 ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b,
189 bool speculative, const StaticInstPtr &inst, Addr target)
208 ThreadHistory& tHist, int brtype, bool taken, Addr branch_pc, Addr target)
298 MPP_StatisticalCorrector::getIndBias(Addr branch_pc,
306 MPP_StatisticalCorrector::getIndBiasSK(Addr branch_pc,
314 MPP_StatisticalCorrector::getIndBiasBank(Addr branch_p
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/gem5/src/dev/pci/
H A Dhost.cc139 const Addr size(pkt->getSize());
186 std::pair<PciBusAddr, Addr>
187 GenericPciHost::decodeAddress(Addr addr)
189 const Addr offset(addr & mask(confDeviceBits));
190 const Addr bus_addr(addr >> confDeviceBits);
/gem5/src/base/loader/
H A Dobject_file.cc77 Addr addr_mask, Addr offset)
80 Addr addr = (sec->baseAddr & addr_mask) + offset;
94 ObjectFile::loadSections(const PortProxy& mem_proxy, Addr addr_mask,
95 Addr offset)
/gem5/src/arch/riscv/
H A Dtlb.cc81 TLB::lookup(Addr vpn, uint8_t asn) const
92 Addr Mask = pte->Mask;
93 Addr InvMask = ~Mask;
94 Addr VPN = pte->VPN;
119 TLB::probeEntry(Addr vpn, uint8_t asn) const
130 Addr Mask = pte->Mask;
131 Addr InvMask = ~Mask;
132 Addr VPN = pte->VPN;
149 Addr VAddrUncacheable = 0xA0000000;
188 TLB::insert(Addr add
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/gem5/src/arch/sparc/
H A Dfaults.hh210 Addr vaddr;
212 FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
223 Addr vaddr;
225 FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
357 void getREDVector(RegVal TT, Addr &PC, Addr &NPC);
359 void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT);
361 void getPrivVector(ThreadContext *tc, Addr &PC, Addr
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/gem5/src/arch/arm/insts/
H A Dmem64.hh62 Addr pc, const SymbolTable *symtab) const override;
143 Addr pc, const SymbolTable *symtab) const override;
159 Addr pc, const SymbolTable *symtab) const override;
175 Addr pc, const SymbolTable *symtab) const override;
188 Addr pc, const SymbolTable *symtab) const override;
201 Addr pc, const SymbolTable *symtab) const override;
220 Addr pc, const SymbolTable *symtab) const override;
232 Addr pc, const SymbolTable *symtab) const override;
247 Addr pc, const SymbolTable *symtab) const override;
261 Addr p
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/gem5/src/arch/arm/kvm/
H A Dgic.cc50 KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
141 KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
148 KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
155 KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
162 KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
288 ContextID ctx, Addr daddr)
297 ContextID ctx, Addr daddr)
306 Addr daddr, size_t size)
315 Addr dadd
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/gem5/src/gpu-compute/
H A Dgpu_tlb.cc157 GpuTLB::insert(Addr vpn, TlbEntry &entry)
183 GpuTLB::lookupIt(Addr va, bool update_lru)
213 GpuTLB::lookup(Addr va, bool update_lru)
264 GpuTLB::demapPage(Addr va, uint64_t asn)
280 Addr vaddr = req->getVaddr();
281 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
288 Addr regNum = 0;
612 Addr IOPort = vaddr & ~IntAddrPrefixMask;
623 Addr configAddress =
662 Addr vadd
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/gem5/src/cpu/
H A Dbase_dyn_inst.hh212 Addr effAddr;
215 Addr physEffAddr;
293 void demapPage(Addr vaddr, uint64_t asn)
297 void demapInstPage(Addr vaddr, uint64_t asn)
301 void demapDataPage(Addr vaddr, uint64_t asn)
306 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
309 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
313 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
477 Addr predInstAddr() { return predPC.instAddr(); }
480 Addr predNextInstAdd
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/gem5/src/arch/power/
H A Dprocess.cc59 Addr brk_point = objFile->dataBase() + objFile->dataSize() +
63 Addr stack_base = 0xbf000000L;
65 Addr max_stack_size = 8 * 1024 * 1024;
68 Addr next_thread_stack_base = stack_base - max_stack_size;
71 Addr mmap_end = 0x70000000L;
197 Addr stack_min = memState->getStackBase() - space_needed;
250 Addr auxv_array_end = auxv_array_base;
/gem5/src/python/pybind11/
H A Dcore.cc151 .def(py::init<Addr &, Addr &>())
152 .def(py::init<Addr, Addr, const std::vector<Addr> &, uint8_t>())
154 .def(py::init<Addr, Addr, uint8_t, uint8_t, uint8_t, uint8_t>())
/gem5/src/mem/ruby/system/
H A DSequencer.hh70 void writeCallback(Addr address,
78 void readCallback(Addr address,
97 void checkCoherence(Addr address);
100 void evictionCallback(Addr address);
101 void invalidateSC(Addr address);
169 bool handleLlsc(Addr address, SequencerRequest* request);
189 typedef std::unordered_map<Addr, SequencerRequest*> RequestTable;
/gem5/src/arch/x86/bios/
H A Dsmbios.cc78 X86ISA::SMBios::SMBiosStructure::writeOut(PortProxy& proxy, Addr addr)
97 PortProxy& proxy, Addr addr)
100 Addr offset = 0;
175 X86ISA::SMBios::BiosInformation::writeOut(PortProxy& proxy, Addr addr)
217 X86ISA::SMBios::SMBiosTable::writeOut(PortProxy& proxy, Addr addr,
218 Addr &headerSize, Addr &structSize)
282 Addr base = smbiosHeader.intermediateHeader.tableAddr;
283 Addr offset = 0;
/gem5/src/mem/ruby/profiler/
H A DAddressProfiler.cc44 lookupTraceForAddress(Addr addr, AddressMap& record_map)
248 AddressProfiler::profileGetX(Addr datablock, Addr PC,
266 AddressProfiler::profileGetS(Addr datablock, Addr PC,
283 AddressProfiler::addTraceSample(Addr data_addr, Addr pc_addr,
301 Addr macro_addr = maskLowOrderBits(data_addr, 10);
320 AddressProfiler::profileRetry(Addr data_addr, AccessType type, int count)
/gem5/src/mem/probes/
H A Dmem_footprint.cc93 MemFootprintProbe::insertAddr(Addr addr, AddrSet *set, uint64_t limit)
105 const Addr cl_addr = (pi.addr >> cacheLineSizeLg2) << cacheLineSizeLg2;
106 const Addr page_addr = (pi.addr >> pageSizeLg2) << pageSizeLg2;

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