Lines Matching refs:Addr

157     GpuTLB::insert(Addr vpn, TlbEntry &entry)
183 GpuTLB::lookupIt(Addr va, bool update_lru)
213 GpuTLB::lookup(Addr va, bool update_lru)
264 GpuTLB::demapPage(Addr va, uint64_t asn)
280 Addr vaddr = req->getVaddr();
281 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
288 Addr regNum = 0;
612 Addr IOPort = vaddr & ~IntAddrPrefixMask;
623 Addr configAddress =
662 Addr vaddr = req->getVaddr();
716 Addr vaddr = req->getVaddr();
751 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
752 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
764 Addr offset = bits(vaddr - base, size - 1, 0);
765 Addr endOffset = offset + req->getSize() - 1;
816 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
865 Addr paddr = entry->paddr | (vaddr & (page_size - 1));
889 Addr baseAddr = localApicBase.base * PageBytes;
890 Addr paddr = req->getPaddr();
1038 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
1113 GpuTLB::TLBEvent::TLBEvent(GpuTLB* _tlb, Addr _addr, tlbOutcome tlb_outcome,
1159 GpuTLB::handleTranslationReturn(Addr virt_page_addr, tlbOutcome tlb_outcome,
1164 Addr vaddr = pkt->req->getVaddr();
1209 Addr paddr = local_entry->paddr | (vaddr & (page_size - 1));
1244 GpuTLB::translationReturn(Addr virtPageAddr, tlbOutcome outcome,
1323 Addr vaddr = pkt->req->getVaddr();
1325 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
1374 Addr
1417 Addr vaddr = pkt->req->getVaddr();
1438 Addr virt_page_addr = roundDown(vaddr, TheISA::PageBytes);
1468 Addr paddr = local_entry->paddr | (vaddr & (page_size - 1));
1488 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
1525 Addr vaddr = pkt->req->getVaddr();
1527 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
1617 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
1645 Addr cleanup_addr = cleanupQueue.front();
1666 GpuTLB::updatePageFootprint(Addr virt_page_addr)