/gem5/src/arch/alpha/ |
H A D | vtophys.cc | 49 kernel_pte_lookup(PortProxy &mem, Addr ptbr, VAddr vaddr) 51 Addr level1_pte = ptbr + vaddr.level1(); 58 Addr level2_pte = level1.paddr() + vaddr.level2(); 65 Addr level3_pte = level2.paddr() + vaddr.level3(); 74 Addr 75 vtophys(Addr vaddr) 77 Addr paddr = 0; 90 Addr 91 vtophys(ThreadContext *tc, Addr addr) 94 Addr ptb [all...] |
/gem5/src/cpu/o3/ |
H A D | store_set.hh | 76 void violation(Addr store_PC, Addr load_PC); 87 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 91 void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid); 97 InstSeqNum checkInst(Addr PC); 100 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 113 inline int calcIndex(Addr PC) 117 inline SSID calcSSID(Addr PC)
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/gem5/src/arch/mips/linux/ |
H A D | aligned.hh | 43 typedef Addr Addr_a __attribute__ ((aligned (8))) ; 47 #define Addr_a Addr __attribute__ ((aligned (8)))
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/gem5/src/arch/sparc/ |
H A D | stacktrace.hh | 47 std::vector<Addr> stack; 57 const std::vector<Addr> &getstack() const { return stack; }
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H A D | SparcSystem.py | 58 reset_addr = Param.Addr(_rom_base, "Address to load ROM at") 59 hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, 61 openboot_addr = Param.Addr(Addr('512kB') + _rom_base, 63 nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") 64 hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, 66 partition_desc_addr = Param.Addr(_partition_desc_base,
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/gem5/src/dev/storage/ |
H A D | simple_disk.hh | 61 void read(Addr addr, baddr_t block, int count) const; 62 void write(Addr addr, baddr_t block, int count);
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/gem5/src/cpu/testers/memtest/ |
H A D | memtest.hh | 138 std::set<Addr> outstandingAddrs; 141 std::unordered_map<Addr, uint8_t> referenceData; 145 const Addr blockAddrMask; 153 Addr blockAlign(Addr addr) const 158 Addr baseAddr1; 159 Addr baseAddr2; 160 Addr uncacheAddr;
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/gem5/src/cpu/testers/directedtest/ |
H A D | SeriesRequestGenerator.hh | 52 void performCallback(uint32_t proc, Addr address); 56 Addr m_address;
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H A D | InvalidateGenerator.hh | 52 void performCallback(uint32_t proc, Addr address); 56 Addr m_address;
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/gem5/src/arch/x86/ |
H A D | pagetable.hh | 62 typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie; 69 Addr paddr; 72 Addr vaddr; 97 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, 102 updateVaddr(Addr new_vaddr) 107 Addr pageStart() 159 Addr paddr() { return pte.base << PageShift; } 160 void paddr(Addr add [all...] |
H A D | stacktrace.cc | 53 Addr addr; 69 Addr 70 ProcessInfo::task(Addr ksp) const 72 Addr base = ksp & ~0x3fff; 76 Addr tsk; 79 tsk = vp.read<Addr>(base + task_off, GuestByteOrder); 85 ProcessInfo::pid(Addr ksp) const 87 Addr task = this->task(ksp); 100 ProcessInfo::name(Addr ksp) const 102 Addr tas [all...] |
/gem5/src/base/ |
H A D | chunk_generator.hh | 61 Addr curAddr; 63 Addr nextAddr; 69 const Addr startAddr; 81 ChunkGenerator(Addr _startAddr, unsigned totalSize, unsigned _chunkSize) 111 Addr addr() const { return curAddr; }
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | dram_rot_gen.hh | 91 Addr start_addr, Addr end_addr, 92 Addr _blocksize, Addr cacheline_size, 94 uint8_t read_percent, Addr data_limit,
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H A D | base_gen.cc | 61 BaseGen::getPacket(Addr addr, unsigned size, const MemCmd& cmd, 68 req->setPC(((Addr)masterID) << 2); 85 Addr start_addr, Addr end_addr, 86 Addr _blocksize, Addr cacheline_size, 88 uint8_t read_percent, Addr data_limit)
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/gem5/src/arch/x86/linux/ |
H A D | system.cc | 69 const Addr realModeData = 0x90200; 76 const Addr commandLineBuff = 0x90000; 78 const Addr commandLinePointer = realModeData + 0x228; 123 const Addr e820MapNrPointer = realModeData + 0x1e8; 126 const Addr e820MapPointer = realModeData + 0x2d0;
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/gem5/src/cpu/pred/ |
H A D | bi_mode.hh | 60 void uncondBranch(ThreadID tid, Addr pc, void * &bp_history); 62 bool lookup(ThreadID tid, Addr branch_addr, void * &bp_history); 63 void btbUpdate(ThreadID tid, Addr branch_addr, void * &bp_history); 64 void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, 65 bool squashed, const StaticInstPtr & inst, Addr corrTarget);
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H A D | multiperspective_perceptron_tage_8KB.hh | 62 int gPredictions(ThreadID tid, Addr branch_pc, 65 void getBiasLSUM(Addr branch_pc, 67 void gUpdates(ThreadID tid, Addr pc, bool taken, 69 void scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken, 70 StatisticalCorrector::BranchInfo *bi, Addr corrTarget) override;
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H A D | tage_sc_l_8KB.hh | 59 uint16_t gtag(ThreadID tid, Addr pc, int bank) const override; 65 Addr branch_pc, bool taken, TAGEBase::BranchInfo* bi) override; 93 unsigned getIndBiasBank( Addr branch_pc, BranchInfo* bi, int hitBank, 96 int gPredictions( ThreadID tid, Addr branch_pc, 102 Addr branch_pc, const StaticInstPtr &inst, bool taken, 103 BranchInfo * tage_bi, Addr corrTarget) override; 105 void gUpdates(ThreadID tid, Addr pc, bool taken, BranchInfo* bi,
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/gem5/src/mem/cache/prefetch/ |
H A D | irregular_stream_buffer.hh | 64 Addr lastAddress; 72 Addr address; 112 void addStructuralToPhysicalEntry(Addr structuralAddress, bool is_secure, 113 Addr physical_address); 123 AddressMapping& getPSMapping(Addr paddr, bool is_secure);
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H A D | associative_set.hh | 43 Addr tag; 80 Addr getTag() const 89 void setTag(Addr t) 123 * Each element is indexed by a key of type Addr, an additional 167 Entry* findEntry(Addr addr, bool is_secure) const; 181 Entry* findVictim(Addr addr); 189 std::vector<Entry *> getPossibleEntries(const Addr addr) const; 197 void insertEntry(Addr addr, bool is_secure, Entry* entry);
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H A D | indirect_memory.hh | 71 Addr address; 84 Addr baseAddr; 135 std::vector<std::vector<Addr>> baseAddr; 140 baseAddr(num_addresses, std::vector<Addr>(num_shifts)) 172 void trackMissIndex1(Addr miss_addr); 179 void trackMissIndex2(Addr miss_addr); 186 void checkAccessMatchOnActiveEntries(Addr addr);
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/gem5/src/dev/arm/ |
H A D | smmu_v3_transl.hh | 50 Addr addr; 61 static SMMUTranslRequest prefetch(Addr addr, uint32_t sid, uint32_t ssid); 71 Addr ttb0, ttb1, httb; 90 Addr addr; 91 Addr addrMask; 105 TranslResult bypass(Addr addr) const; 122 Addr addr, uint16_t asid, uint16_t vmid, 125 void walkCacheUpdate(Yield &yield, Addr va, Addr vaMask, Addr p [all...] |
/gem5/src/mem/cache/tags/ |
H A D | sector_blk.hh | 102 Addr getTag() const; 130 void insert(const Addr tag, const bool is_secure, const int src_master_ID, 151 Addr _tag; 194 void setTag(const Addr tag); 201 Addr getTag() const;
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | RubyRequest.cc | 70 Addr wBase = pkt->getAddr(); 71 Addr wTail = wBase + pkt->getSize(); 72 Addr mBase = m_PhysicalAddress; 73 Addr mTail = mBase + m_Size; 77 Addr cBase = std::max(wBase, mBase); 78 Addr cTail = std::min(wTail, mTail); 80 for (Addr i = cBase; i < cTail; ++i) {
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/gem5/src/mem/ruby/structures/ |
H A D | TBETable.hh | 46 bool isPresent(Addr address) const; 47 void allocate(Addr address); 48 void deallocate(Addr address); 55 ENTRY *lookup(Addr address); 66 std::unordered_map<Addr, ENTRY> m_map; 83 TBETable<ENTRY>::isPresent(Addr address) const 92 TBETable<ENTRY>::allocate(Addr address) 101 TBETable<ENTRY>::deallocate(Addr address) 111 TBETable<ENTRY>::lookup(Addr address)
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