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/gem5/tests/configs/
H A Dsimple-atomic-mp-ruby.py6870:5707ef3691b5 Mon Jan 25 12:51:00 EST 2010 Derek Hower <drh5@cs.wisc.edu> config: changed default ruby config file for regression
H A Do3-timing-ruby.py6870:5707ef3691b5 Mon Jan 25 12:51:00 EST 2010 Derek Hower <drh5@cs.wisc.edu> config: changed default ruby config file for regression
H A Do3-timing-mp-ruby.py6870:5707ef3691b5 Mon Jan 25 12:51:00 EST 2010 Derek Hower <drh5@cs.wisc.edu> config: changed default ruby config file for regression
H A Dsimple-timing-ruby.py6870:5707ef3691b5 Mon Jan 25 12:51:00 EST 2010 Derek Hower <drh5@cs.wisc.edu> config: changed default ruby config file for regression
H A Dsimple-timing-mp-ruby.py6870:5707ef3691b5 Mon Jan 25 12:51:00 EST 2010 Derek Hower <drh5@cs.wisc.edu> config: changed default ruby config file for regression
/gem5/src/arch/arm/isa/formats/
H A Dmisc.isa12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Daarch64.isa12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/arm/
H A DArmISA.py12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dmiscregs.cc12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Disa.hh12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Disa.cc12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

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