Searched hist:56 (Results 451 - 475 of 501) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | snoop_filter.cc | 12352:3bddc8785a99 Thu Sep 22 08:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Allow CMOs as snooping requests in the snoop filter The snoop filter performs sanity checks of the type of packets that are expected to snoop caches above. Cache maintenace operations are expected to perform a clean and or invalidate on all caches down to the specified point of reference and therefore could also generate snoops. Change-Id: I7f8fef246a85faa87ccd289c28b49686ed7caa08 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5052 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | coherent_xbar.cc | 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | port.cc | 4321:6f8b597ab244 Wed Apr 04 13:56:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter. In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather than creating a new one each time. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/cache_impl.hh: only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc) |
| /gem5/src/mem/ruby/profiler/ | ||
| H A D | Profiler.cc | 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass |
| /gem5/src/cpu/kvm/ | ||
| H A D | base.hh | 9688:cce7dd32aed3 Tue May 14 09:56:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> kvm: Fix the memory interface used by KVM The CpuPort class was removed before the KVM patches were committed, which means that the KVM interface currently doesn't compile. This changeset adds the BaseKvmCPU::KVMCpuPort class which derives from MasterPort. This class is used on the data and instruction ports instead of the old CpuPort. |
| /gem5/src/mem/cache/ | ||
| H A D | base.cc | 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 11486:f09bb73b3050 Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: fix headers include order in the cache related classes Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> 11484:08b33c52a16d Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: change NULL to nullptr in the cache related classes Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> 11483:d4c2e56d18b2 Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: fix the line length in the cache related classes Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | base.hh | 11483:d4c2e56d18b2 Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: fix the line length in the cache related classes Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> 5875:d82be3235ab4 Mon Feb 16 11:56:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Fixes to get prefetching working again. Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too. |
| /gem5/src/mem/ruby/slicc_interface/ | ||
| H A D | AbstractController.hh | 10837:ecbab2522757 Tue May 19 11:56:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Fix RubySystem warm-up and cool-down scope The processes of warming up and cooling down Ruby caches are simulation-wide processes, not just RubySystem instance-specific processes. Thus, the warm-up and cool-down variables should be globally visible to any Ruby components participating in either process. Make these variables static members and track the warm-up and cool-down processes as appropriate. This patch also has two side benefits: 1) It removes references to the RubySystem g_system_ptr, which are problematic for allowing multiple RubySystem instances in a single simulation. Warmup and cooldown variables being static (global) reduces the need for instance-specific dereferences through the RubySystem. 2) From the AbstractController, it removes local RubySystem pointers, which are used inconsistently with other uses of the RubySystem: 11 other uses reference the RubySystem with the g_system_ptr. Only sequencers have local pointers. |
| /gem5/src/sim/ | ||
| H A D | sim_object.hh | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
| H A D | serialize.hh | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
| /gem5/src/cpu/minor/ | ||
| H A D | exec_context.hh | 13900:d4bcfecd871e Sun Apr 28 04:56:00 EDT 2019 Gabe Black <gabeblack@google.com> cpu: Get rid of the (read|set)RegOtherThread methods. These are implemented by MIPS internally now. Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/cpu/simple/ | ||
| H A D | timing.cc | 8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason. 5728:9574f561dfa2 Mon Nov 10 00:56:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Make unaligned accesses work in the timing simple CPU. 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. 3297:f0855ab36ff5 Thu Oct 12 18:56:00 EDT 2006 Lisa Hsu <hsul@eecs.umich.edu> Merge zizzer:/bk/newmem into zed.eecs.umich.edu:/z/hsul/work/m5/newmem src/cpu/simple/timing.cc: hand merge |
| H A D | exec_context.hh | 13900:d4bcfecd871e Sun Apr 28 04:56:00 EDT 2019 Gabe Black <gabeblack@google.com> cpu: Get rid of the (read|set)RegOtherThread methods. These are implemented by MIPS internally now. Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | atomic.cc | 8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason. 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. 4940:23874ae87540 Sat Aug 04 18:56:00 EDT 2007 Nathan Binkert <nate@binkert.org> SimpleCPU: Add some DPRINTFs |
| /gem5/src/ | ||
| H A D | SConscript | 12363:8ca0fee7f9b3 Sun Dec 03 03:56:00 EST 2017 Gabe Black <gabeblack@google.com> scons: Several fixes having to do with tags and sets. There were a few places where tags weren't being converted to sets correctly which unfortunately only manifested when called in certain ways. This would be a pretty reasonable place to add some python unit tests... Change-Id: I87509369b4ec6f702b7521e52bf63701a87ec436 Reviewed-on: https://gem5-review.googlesource.com/6261 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> 11342:a4d19e7cd26d Wed Feb 17 03:56:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable building with the gcc/clang Address Sanitizer Allow the user to easily build gem5 with the Address Sanitizer, part of both gcc and clang these days. 9556:463684ff6fd1 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Unify the flags shared by gcc and clang This patch restructures and unifies the flags used by gcc and clang as they are largely the same. The common parts are now dealt with in a shared block of code, and the few bits and pieces that are specifically affecting either gcc or clang are done separately. 9555:9222d9e63ddb Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning delete with non-virtual destructor This patch enables a warning for deleting derived classes that do not have a virtual destructor. The patch merely adds additional checks, and there are currently no cases that had to be fixed. 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
| /gem5/src/cpu/o3/ | ||
| H A D | cpu.cc | 13546:6cd6d7b19498 Wed Dec 12 11:56:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu: Fix usage of setArchVecElem setArchVecElem should create a VecElemClass RegId, and not a VecRegClass. Initializing a VecRegClass with three arguments makes it panic Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15655 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation. 5804:34fe9bbc6705 Wed Jan 21 17:56:00 EST 2009 Nathan Binkert <nate@binkert.org> o3cpu: give a name to the activity recorder for better tracing 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. 4598:56adf2e778a8 Wed Jun 20 11:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Don't do checker stuff if the checker is not defined |
| H A D | fetch_impl.hh | 8462:80492ae5148e Sun Jul 10 01:56:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com O3: Fix up pipelining icache accesses in fetch stage to function properly Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to icache to work with recent changes to main repository. Also added in ability for fetch stage to delay issuing the fault carrying nop when a pipeline fetch causes a fault and no fetch bandwidth is available until the next cycle. 8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation. 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. 3376:ed8179dd13da Mon Oct 16 15:56:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into zeep.eecs.umich.edu:/home/gblack/m5/newmem 3014:b4309193255a Wed Aug 16 15:56:00 EDT 2006 Ron Dreslinski <rdreslin@umich.edu> Fixes for Kevins O3 model to work with the blocking caches. src/cpu/o3/fetch_impl.hh: Fix ordering so dereference works src/cpu/o3/lsq_impl.hh: Check to make sure we didn't squash already src/cpu/o3/lsq_unit.hh: Fix for counting squashed retrys in the WB count src/cpu/o3/lsq_unit_impl.hh: Make sure to set retryID for stores, and clear it appropriately |
| H A D | fetch.hh | 8462:80492ae5148e Sun Jul 10 01:56:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com O3: Fix up pipelining icache accesses in fetch stage to function properly Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to icache to work with recent changes to main repository. Also added in ability for fetch stage to delay issuing the fault carrying nop when a pipeline fetch causes a fault and no fetch bandwidth is available until the next cycle. 8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation. |
| H A D | thread_state.hh | 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. |
| H A D | dyn_inst.hh | 13900:d4bcfecd871e Sun Apr 28 04:56:00 EDT 2019 Gabe Black <gabeblack@google.com> cpu: Get rid of the (read|set)RegOtherThread methods. These are implemented by MIPS internally now. Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | cpu.hh | 8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation. 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. 4598:56adf2e778a8 Wed Jun 20 11:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Don't do checker stuff if the checker is not defined |
| /gem5/src/python/m5/ | ||
| H A D | SimObject.py | 8459:b8c3c20d0385 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Config: Add support for a Self.all proxy object 7500:b543b8e5fcbc Sat Jul 17 11:56:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> SimObject: transparently forward Python attribute refs to C++. This tidbit was pulled from a larger patch for Tim's sake, so the comment reflects functions that haven't been exported yet. I hope to commit them soon so it didn't seem worth cleaning up. |
| /gem5/src/arch/arm/ | ||
| H A D | tlb.cc | 14278:45892d0d3e98 Sun Sep 08 19:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1 Change-Id: I6df0cdcbadca17f30d3de3bed887f75c739b00f0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20979 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> 13795:e21c61d9efb8 Tue Mar 19 13:56:00 EDT 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> dev-arm: ambiguous use of getPort() The recent introduction of getPort() creates a conflict with the existing method used in arm MMU. This patch rename the old getPort() in getDMAPort() according to the returned value (DmaPort class type) Change-Id: Ief3d83650fd6b08490522341631244be06e380ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | utility.cc | 10103:af1ec649e251 Fri Mar 07 15:56:00 EST 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> arm: Fix uninitialised warning with gcc 4.8 Small fix for a warning that prevents compilation with gcc 4.8.1 due to detecting that a variable might be uninitialised. The fix is to assign a safe default. |
| /gem5/src/cpu/ | ||
| H A D | base_dyn_inst.hh | 10110:580b47334a97 Fri Mar 07 15:56:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> cpu: Make CPU and ThreadContext getters const This patch merely tidies up the CPU and ThreadContext getters by making them const where appropriate. 8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason. 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. |
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