Searched hist:56 (Results 326 - 350 of 501) sorted by relevance
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | AbstractController.cc | 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 10837:ecbab2522757 Tue May 19 11:56:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Fix RubySystem warm-up and cool-down scope The processes of warming up and cooling down Ruby caches are simulation-wide processes, not just RubySystem instance-specific processes. Thus, the warm-up and cool-down variables should be globally visible to any Ruby components participating in either process. Make these variables static members and track the warm-up and cool-down processes as appropriate. This patch also has two side benefits: 1) It removes references to the RubySystem g_system_ptr, which are problematic for allowing multiple RubySystem instances in a single simulation. Warmup and cooldown variables being static (global) reduces the need for instance-specific dereferences through the RubySystem. 2) From the AbstractController, it removes local RubySystem pointers, which are used inconsistently with other uses of the RubySystem: 11 other uses reference the RubySystem with the g_system_ptr. Only sequencers have local pointers. |
/gem5/src/dev/arm/ | ||
H A D | RealView.py | 14283:b02cde4661e1 Mon Aug 12 14:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add HDLcd DTB autogeneration A Display has been defined. Its sole purpose is to generate the device tree node to be referenced by the HDLcd device. The encoder parameters are based on the existing node defined in: system/arm/dt/armv8.dts Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> 12741:6d088ffe06b1 Fri Mar 24 09:56:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1 Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1 platform. Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2327 10780:46070443051e Wed Apr 08 16:56:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> config: Support full-system with SST's memory system This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories. 9806:3f262c18ad5d Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev/arm: get rid of AmbaDev namespace It was confusing having an AmbaDev namespace along with an AmbaDevice class. The namespace stuff is now moved in to a new base AmbaDevice class, which is a mixin for classes AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice to provide the readId function as an inherited member function. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 8461:7d0669201f80 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> IO: Handle case where ISA Fake device is being used as a fake memory. |
/gem5/ | ||
H A D | SConstruct | 11342:a4d19e7cd26d Wed Feb 17 03:56:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable building with the gcc/clang Address Sanitizer Allow the user to easily build gem5 with the Address Sanitizer, part of both gcc and clang these days. 11212:47e2adf7fb1a Sun Nov 15 17:56:00 EST 2015 Joe Gross <joseph.gross@amd.com> sim: support for distcc pump server settings 10106:b7e7533097b9 Fri Mar 07 15:56:00 EST 2014 Mitch Hayenga <Mitch.Hayenga@arm.com> scons: Fix clang version identification for OSX The version string may have additional trailing information 9900:19dc2b26eefa Tue Oct 01 09:56:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> scons, kvm: Check for the presence of POSIX timers The kvm-based CPU module requires support for POSIX timers. This changeset adds a check for POSIX timers and ensures that gem5 is linked with librt if necessary. KVM support is disabled if POSIX timers are not supported by the host. This fixes a compilation issue for some glibc versions where clock_nanosleep and timer_create are in different libraries. 9556:463684ff6fd1 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Unify the flags shared by gcc and clang This patch restructures and unifies the flags used by gcc and clang as they are largely the same. The common parts are now dealt with in a shared block of code, and the few bits and pieces that are specifically affecting either gcc or clang are done separately. 9552:460cf901acba Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions. 9551:f867e530f39b Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing field initializers This patch adds a warning for missing field initializers for both gcc and clang, and addresses the warnings that were generated. 9119:a8749b39f1f8 Thu Jul 12 00:56:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> scons: Add LIBRARY_PATH from the user environment to Scons This patch adds the LIBRARY_PATH from the users OS environment to Scons build environment. This path is used when linking to search for libraries, and this patch enables tcmalloc to be used during the build even if it is not placed in the default search paths. 8474:7f49e6a176b8 Tue Jul 19 05:56:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SCons: Only print all the SConsopts being read if verbose is turned on. 4949:302707329b7e Sun Aug 12 12:56:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: If IGNORE_STYLE=True is set on the scons command line, ignore style. Use this in the regress script to avoid issues with the checker. |
/gem5/src/arch/x86/isa/microops/ | ||
H A D | regop.isa | 6442:580a6fbc7585 Wed Aug 05 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix the carry flag for shr. 6441:801f1fc07a58 Wed Aug 05 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix the carry flag for shl. 4592:520664dfb26f Tue Jun 19 13:56:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make instructions that are illegal in 64 bit mode not do the wrong thing in 64 bit mode. Also add in more versions of PUSH and POP, and a version of near CALL. |
/gem5/src/arch/sparc/ | ||
H A D | ua2005.cc | 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. 4207:3ebd72381185 Mon Mar 12 13:56:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> move hver code to ua2005.cc src/arch/sparc/miscregfile.cc: this code should be in readFSreg src/arch/sparc/ua2005.cc: move code froh miscregfile to ua2005.cc 4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/arch/x86/utility.hh: add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi src/arch/sparc/isa/decoder.isa: handle writable bits of strandstatus register in miscregfile src/arch/sparc/miscregfile.hh: some constants for the strand status register src/arch/sparc/ua2005.cc: properly implement the strand status register src/dev/sparc/iob.cc: implement ipi generation properly src/sim/system.cc: call into the ISA to start the CPU (or not) |
/gem5/src/mem/ | ||
H A D | bridge.cc | 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 9549:95a536fae9ac Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Enforce strict use of busFirst- and busLastWordTime This patch adds a check to ensure that the delay incurred by the bus is not simply disregarded, but accounted for by someone. At this point, all the modules do is to zero it out, and no additional time is spent. This highlights where the bus timing is simply dropped instead of being paid for. As a follow up, the locations identified in this patch should add this additional time to the packets in one way or another. For now it simply acts as a sanity check and highlights where the delay is simply ignored. Since no time is added, all regressions remain the same. 9542:683991c46ac8 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add predecessor to SenderState base class This patch adds a predecessor field to the SenderState base class to make the process of linking them up more uniform, and enable a traversal of the stack without knowing the specific type of the subclasses. There are a number of simplifications done as part of changing the SenderState, particularly in the RubyTest. |
H A D | packet.cc | 12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 11256:65db40192591 Wed Dec 09 22:56:00 EST 2015 Tony Gutierrez <anthony.gutierrez@amd.com> mem: remove acq/rel cmds from packet and add mem fence req 9542:683991c46ac8 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add predecessor to SenderState base class This patch adds a predecessor field to the SenderState base class to make the process of linking them up more uniform, and enable a traversal of the stack without knowing the specific type of the subclasses. There are a number of simplifications done as part of changing the SenderState, particularly in the RubyTest. |
/gem5/src/mem/ruby/system/ | ||
H A D | RubyPort.cc | 9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6) This patch fixes the warnings that clang3.2svn emit due to the "-Wall" flag. There is one case of an uninitialised value in the ARM neon ISA description, and then a whole range of unused private fields that are pruned. 9542:683991c46ac8 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add predecessor to SenderState base class This patch adds a predecessor field to the SenderState base class to make the process of linking them up more uniform, and enable a traversal of the stack without knowing the specific type of the subclasses. There are a number of simplifications done as part of changing the SenderState, particularly in the RubyTest. 8505:442804117f95 Mon Aug 15 01:56:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Initialize some variables. |
/gem5/tests/configs/ | ||
H A D | tsunami-simple-atomic-dual.py | 9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests Keep it simple and use the SimpleMemory rather than the DRAM controller model for atomic full-system tests. |
H A D | tsunami-simple-atomic.py | 9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests Keep it simple and use the SimpleMemory rather than the DRAM controller model for atomic full-system tests. |
/gem5/src/arch/mips/isa/ | ||
H A D | includes.isa | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
/gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/src/arch/alpha/ | ||
H A D | interrupts.hh | 9550:e0e2c8f83d08 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix up numerous warnings about name shadowing This patch address the most important name shadowing warnings (as produced when using gcc/clang with -Wshadow). There are many locations where constructor parameters and function parameters shadow local variables, but these are left unchanged. |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/ | ||
H A D | stats.txt | 9962:7aef35367a21 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats after shifting to SimpleMemory Match stats with new regression configs. |
/gem5/src/mem/ruby/network/simple/ | ||
H A D | Throttle.cc | 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass |
H A D | Switch.cc | 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass |
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
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