1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194946 # Number of seconds simulated 4sim_ticks 5194946000500 # Number of ticks simulated 5final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 930999 # Simulator instruction rate (inst/s) 8host_op_rate 1794485 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37656529565 # Simulator tick rate (ticks/s) 10host_mem_usage 609616 # Number of bytes of host memory used 11host_seconds 137.96 # Real time elapsed on the host 12sim_insts 128436892 # Number of instructions simulated 13sim_ops 247560077 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9031168 # Number of bytes read from this memory 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 21system.physmem.bytes_read::total 9881152 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8151616 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8151616 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12832 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141112 # Number of read requests responded to by this memory 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 154393 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 127369 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 127369 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 158086 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 1738453 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 1902070 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 158086 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 158086 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1569144 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1569144 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1569144 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 158086 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 1738453 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 3471214 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 154393 # Number of read requests accepted 52system.physmem.writeReqs 127369 # Number of write requests accepted 53system.physmem.readBursts 154393 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 127369 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 9872000 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue 57system.physmem.bytesWritten 8149824 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 9881152 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 8151616 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 10087 # Per bank write bursts 64system.physmem.perBankRdBursts::1 9534 # Per bank write bursts 65system.physmem.perBankRdBursts::2 9814 # Per bank write bursts 66system.physmem.perBankRdBursts::3 9653 # Per bank write bursts 67system.physmem.perBankRdBursts::4 10130 # Per bank write bursts 68system.physmem.perBankRdBursts::5 9948 # Per bank write bursts 69system.physmem.perBankRdBursts::6 9317 # Per bank write bursts 70system.physmem.perBankRdBursts::7 9200 # Per bank write bursts 71system.physmem.perBankRdBursts::8 8918 # Per bank write bursts 72system.physmem.perBankRdBursts::9 9357 # Per bank write bursts 73system.physmem.perBankRdBursts::10 9071 # Per bank write bursts 74system.physmem.perBankRdBursts::11 9331 # Per bank write bursts 75system.physmem.perBankRdBursts::12 9713 # Per bank write bursts 76system.physmem.perBankRdBursts::13 9915 # Per bank write bursts 77system.physmem.perBankRdBursts::14 10131 # Per bank write bursts 78system.physmem.perBankRdBursts::15 10131 # Per bank write bursts 79system.physmem.perBankWrBursts::0 8252 # Per bank write bursts 80system.physmem.perBankWrBursts::1 7742 # Per bank write bursts 81system.physmem.perBankWrBursts::2 7578 # Per bank write bursts 82system.physmem.perBankWrBursts::3 7567 # Per bank write bursts 83system.physmem.perBankWrBursts::4 7987 # Per bank write bursts 84system.physmem.perBankWrBursts::5 8326 # Per bank write bursts 85system.physmem.perBankWrBursts::6 7984 # Per bank write bursts 86system.physmem.perBankWrBursts::7 7858 # Per bank write bursts 87system.physmem.perBankWrBursts::8 7447 # Per bank write bursts 88system.physmem.perBankWrBursts::9 8118 # Per bank write bursts 89system.physmem.perBankWrBursts::10 7706 # Per bank write bursts 90system.physmem.perBankWrBursts::11 7949 # Per bank write bursts 91system.physmem.perBankWrBursts::12 8417 # Per bank write bursts 92system.physmem.perBankWrBursts::13 8510 # Per bank write bursts 93system.physmem.perBankWrBursts::14 8023 # Per bank write bursts 94system.physmem.perBankWrBursts::15 7877 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 15 # Number of times write queue was full causing retry 97system.physmem.totGap 5194945939500 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 154393 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 127369 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 151022 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 2785 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 36 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 2198 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 3757 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 7707 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 6176 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 7371 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 6314 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 6198 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 6474 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 7322 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 6886 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 7581 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 8523 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 7744 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 9513 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 7269 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 6984 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 7148 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 1628 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 107 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 117 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 57 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 116 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 105 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 56869 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 316.898416 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 189.066814 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 329.232113 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 20064 35.28% 35.28% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 13820 24.30% 59.58% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 6395 11.25% 70.83% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 3441 6.05% 76.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2422 4.26% 81.14% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1595 2.80% 83.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1163 2.05% 85.99% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 983 1.73% 87.72% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 6986 12.28% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 56869 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 5701 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 27.056657 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 634.190971 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 5700 99.98% 99.98% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::total 5701 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 5700 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 22.339649 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 19.500075 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 17.394307 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 4849 85.07% 85.07% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 101 1.77% 86.84% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 44 0.77% 87.61% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 52 0.91% 88.53% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 17 0.30% 88.82% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 15 0.26% 89.09% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 60 1.05% 90.14% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 6 0.11% 90.25% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 207 3.63% 93.88% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 10 0.18% 94.05% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 6 0.11% 94.16% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 16 0.28% 94.44% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 91 1.60% 96.04% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 6 0.11% 96.14% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 3 0.05% 96.19% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 36 0.63% 96.82% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 144 2.53% 99.35% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::96-99 1 0.02% 99.37% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::104-107 1 0.02% 99.39% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-131 11 0.19% 99.58% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-139 1 0.02% 99.60% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::140-143 3 0.05% 99.65% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::144-147 9 0.16% 99.81% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::152-155 1 0.02% 99.82% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::156-159 1 0.02% 99.84% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::176-179 3 0.05% 99.96% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-211 2 0.04% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::total 5700 # Writes before turning the bus around for reads 261system.physmem.totQLat 1573374325 # Total ticks spent queuing 262system.physmem.totMemAccLat 4465561825 # Total ticks spent from burst creation until serviced by the DRAM 263system.physmem.totBusLat 771250000 # Total ticks spent in databus transfers 264system.physmem.avgQLat 10200.16 # Average queueing delay per DRAM burst 265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 266system.physmem.avgMemAccLat 28950.16 # Average memory access latency per DRAM burst 267system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s 268system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s 269system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s 270system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s 271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 272system.physmem.busUtil 0.03 # Data bus utilization in percentage 273system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 274system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 275system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 276system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing 277system.physmem.readRowHits 125550 # Number of row buffer hits during reads 278system.physmem.writeRowHits 99170 # Number of row buffer hits during writes 279system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads 280system.physmem.writeRowHitRate 77.86 # Row buffer hit rate for writes 281system.physmem.avgGap 18437354.72 # Average gap between requests 282system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined 283system.physmem_0.actEnergy 210916440 # Energy for activate commands per rank (pJ) 284system.physmem_0.preEnergy 115083375 # Energy for precharge commands per rank (pJ) 285system.physmem_0.readEnergy 605927400 # Energy for read commands per rank (pJ) 286system.physmem_0.writeEnergy 410119200 # Energy for write commands per rank (pJ) 287system.physmem_0.refreshEnergy 339308180640 # Energy for refresh commands per rank (pJ) 288system.physmem_0.actBackEnergy 137084456790 # Energy for active background per rank (pJ) 289system.physmem_0.preBackEnergy 2996714193750 # Energy for precharge background per rank (pJ) 290system.physmem_0.totalEnergy 3474448877595 # Total energy per rank (pJ) 291system.physmem_0.averagePower 668.814114 # Core power per rank (mW) 292system.physmem_0.memoryStateTime::IDLE 4985194974722 # Time in different power states 293system.physmem_0.memoryStateTime::REF 173470440000 # Time in different power states 294system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 295system.physmem_0.memoryStateTime::ACT 36280536278 # Time in different power states 296system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 297system.physmem_1.actEnergy 218998080 # Energy for activate commands per rank (pJ) 298system.physmem_1.preEnergy 119493000 # Energy for precharge commands per rank (pJ) 299system.physmem_1.readEnergy 597214800 # Energy for read commands per rank (pJ) 300system.physmem_1.writeEnergy 415018080 # Energy for write commands per rank (pJ) 301system.physmem_1.refreshEnergy 339308180640 # Energy for refresh commands per rank (pJ) 302system.physmem_1.actBackEnergy 137426526900 # Energy for active background per rank (pJ) 303system.physmem_1.preBackEnergy 2996414132250 # Energy for precharge background per rank (pJ) 304system.physmem_1.totalEnergy 3474499563750 # Total energy per rank (pJ) 305system.physmem_1.averagePower 668.823871 # Core power per rank (mW) 306system.physmem_1.memoryStateTime::IDLE 4984690777488 # Time in different power states 307system.physmem_1.memoryStateTime::REF 173470440000 # Time in different power states 308system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 309system.physmem_1.memoryStateTime::ACT 36784611512 # Time in different power states 310system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.cpu_clk_domain.clock 500 # Clock period in ticks 312system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 313system.cpu.numCycles 10389892001 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 316system.cpu.kern.inst.arm 0 # number of arm instructions executed 317system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 318system.cpu.committedInsts 128436892 # Number of instructions committed 319system.cpu.committedOps 247560077 # Number of ops (including micro ops) committed 320system.cpu.num_int_alu_accesses 232158810 # Number of integer alu accesses 321system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 322system.cpu.num_func_calls 2315811 # number of times a function call or return occured 323system.cpu.num_conditional_control_insts 23152999 # number of instructions that are conditional controls 324system.cpu.num_int_insts 232158810 # number of integer instructions 325system.cpu.num_fp_insts 48 # number of float instructions 326system.cpu.num_int_register_reads 434959716 # number of times the integer registers were read 327system.cpu.num_int_register_writes 197963277 # number of times the integer registers were written 328system.cpu.num_fp_register_reads 48 # number of times the floating registers were read 329system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 330system.cpu.num_cc_register_reads 132873102 # number of times the CC registers were read 331system.cpu.num_cc_register_writes 95461248 # number of times the CC registers were written 332system.cpu.num_mem_refs 22321002 # number of memory refs 333system.cpu.num_load_insts 13911426 # Number of load instructions 334system.cpu.num_store_insts 8409576 # Number of store instructions 335system.cpu.num_idle_cycles 9774021635.086119 # Number of idle cycles 336system.cpu.num_busy_cycles 615870365.913881 # Number of busy cycles 337system.cpu.not_idle_fraction 0.059276 # Percentage of non-idle cycles 338system.cpu.idle_fraction 0.940724 # Percentage of idle cycles 339system.cpu.Branches 26327440 # Number of branches fetched 340system.cpu.op_class::No_OpClass 172203 0.07% 0.07% # Class of executed instruction 341system.cpu.op_class::IntAlu 224810530 90.81% 90.88% # Class of executed instruction 342system.cpu.op_class::IntMult 140088 0.06% 90.94% # Class of executed instruction 343system.cpu.op_class::IntDiv 122745 0.05% 90.99% # Class of executed instruction 344system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction 345system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction 346system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction 347system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction 348system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction 349system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction 350system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction 351system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction 352system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction 353system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction 354system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction 355system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction 356system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction 357system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction 358system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction 359system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction 360system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction 361system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction 362system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction 363system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction 364system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction 365system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction 366system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction 367system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction 368system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction 369system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction 370system.cpu.op_class::MemRead 13906455 5.62% 96.60% # Class of executed instruction 371system.cpu.op_class::MemWrite 8409576 3.40% 100.00% # Class of executed instruction 372system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 373system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 374system.cpu.op_class::total 247561613 # Class of executed instruction 375system.cpu.dcache.tags.replacements 1623668 # number of replacements 376system.cpu.dcache.tags.tagsinuse 511.995482 # Cycle average of tags in use 377system.cpu.dcache.tags.total_refs 20139358 # Total number of references to valid blocks. 378system.cpu.dcache.tags.sampled_refs 1624180 # Sample count of references to valid blocks. 379system.cpu.dcache.tags.avg_refs 12.399708 # Average number of references to valid blocks. 380system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. 381system.cpu.dcache.tags.occ_blocks::cpu.data 511.995482 # Average occupied blocks per requestor 382system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 383system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy 384system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 385system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 386system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 387system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 388system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 389system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 390system.cpu.dcache.tags.tag_accesses 88717633 # Number of tag accesses 391system.cpu.dcache.tags.data_accesses 88717633 # Number of data accesses 392system.cpu.dcache.ReadReq_hits::cpu.data 12002599 # number of ReadReq hits 393system.cpu.dcache.ReadReq_hits::total 12002599 # number of ReadReq hits 394system.cpu.dcache.WriteReq_hits::cpu.data 8075450 # number of WriteReq hits 395system.cpu.dcache.WriteReq_hits::total 8075450 # number of WriteReq hits 396system.cpu.dcache.SoftPFReq_hits::cpu.data 59092 # number of SoftPFReq hits 397system.cpu.dcache.SoftPFReq_hits::total 59092 # number of SoftPFReq hits 398system.cpu.dcache.demand_hits::cpu.data 20078049 # number of demand (read+write) hits 399system.cpu.dcache.demand_hits::total 20078049 # number of demand (read+write) hits 400system.cpu.dcache.overall_hits::cpu.data 20137141 # number of overall hits 401system.cpu.dcache.overall_hits::total 20137141 # number of overall hits 402system.cpu.dcache.ReadReq_misses::cpu.data 907290 # number of ReadReq misses 403system.cpu.dcache.ReadReq_misses::total 907290 # number of ReadReq misses 404system.cpu.dcache.WriteReq_misses::cpu.data 326130 # number of WriteReq misses 405system.cpu.dcache.WriteReq_misses::total 326130 # number of WriteReq misses 406system.cpu.dcache.SoftPFReq_misses::cpu.data 402796 # number of SoftPFReq misses 407system.cpu.dcache.SoftPFReq_misses::total 402796 # number of SoftPFReq misses 408system.cpu.dcache.demand_misses::cpu.data 1233420 # number of demand (read+write) misses 409system.cpu.dcache.demand_misses::total 1233420 # number of demand (read+write) misses 410system.cpu.dcache.overall_misses::cpu.data 1636216 # number of overall misses 411system.cpu.dcache.overall_misses::total 1636216 # number of overall misses 412system.cpu.dcache.ReadReq_miss_latency::cpu.data 13559380500 # number of ReadReq miss cycles 413system.cpu.dcache.ReadReq_miss_latency::total 13559380500 # number of ReadReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::cpu.data 18441171467 # number of WriteReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::total 18441171467 # number of WriteReq miss cycles 416system.cpu.dcache.demand_miss_latency::cpu.data 32000551967 # number of demand (read+write) miss cycles 417system.cpu.dcache.demand_miss_latency::total 32000551967 # number of demand (read+write) miss cycles 418system.cpu.dcache.overall_miss_latency::cpu.data 32000551967 # number of overall miss cycles 419system.cpu.dcache.overall_miss_latency::total 32000551967 # number of overall miss cycles 420system.cpu.dcache.ReadReq_accesses::cpu.data 12909889 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.ReadReq_accesses::total 12909889 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.WriteReq_accesses::cpu.data 8401580 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::total 8401580 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.SoftPFReq_accesses::cpu.data 461888 # number of SoftPFReq accesses(hits+misses) 425system.cpu.dcache.SoftPFReq_accesses::total 461888 # number of SoftPFReq accesses(hits+misses) 426system.cpu.dcache.demand_accesses::cpu.data 21311469 # number of demand (read+write) accesses 427system.cpu.dcache.demand_accesses::total 21311469 # number of demand (read+write) accesses 428system.cpu.dcache.overall_accesses::cpu.data 21773357 # number of overall (read+write) accesses 429system.cpu.dcache.overall_accesses::total 21773357 # number of overall (read+write) accesses 430system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070279 # miss rate for ReadReq accesses 431system.cpu.dcache.ReadReq_miss_rate::total 0.070279 # miss rate for ReadReq accesses 432system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038818 # miss rate for WriteReq accesses 433system.cpu.dcache.WriteReq_miss_rate::total 0.038818 # miss rate for WriteReq accesses 434system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872064 # miss rate for SoftPFReq accesses 435system.cpu.dcache.SoftPFReq_miss_rate::total 0.872064 # miss rate for SoftPFReq accesses 436system.cpu.dcache.demand_miss_rate::cpu.data 0.057876 # miss rate for demand accesses 437system.cpu.dcache.demand_miss_rate::total 0.057876 # miss rate for demand accesses 438system.cpu.dcache.overall_miss_rate::cpu.data 0.075148 # miss rate for overall accesses 439system.cpu.dcache.overall_miss_rate::total 0.075148 # miss rate for overall accesses 440system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14944.924445 # average ReadReq miss latency 441system.cpu.dcache.ReadReq_avg_miss_latency::total 14944.924445 # average ReadReq miss latency 442system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56545.461831 # average WriteReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::total 56545.461831 # average WriteReq miss latency 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 25944.570355 # average overall miss latency 445system.cpu.dcache.demand_avg_miss_latency::total 25944.570355 # average overall miss latency 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 19557.657404 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::total 19557.657404 # average overall miss latency 448system.cpu.dcache.blocked_cycles::no_mshrs 19286 # number of cycles access was blocked 449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_mshrs 514 # number of cycles access was blocked 451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.521401 # average number of cycles each access was blocked 453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 454system.cpu.dcache.writebacks::writebacks 1540773 # number of writebacks 455system.cpu.dcache.writebacks::total 1540773 # number of writebacks 456system.cpu.dcache.ReadReq_mshr_hits::cpu.data 285 # number of ReadReq MSHR hits 457system.cpu.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits 458system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9475 # number of WriteReq MSHR hits 459system.cpu.dcache.WriteReq_mshr_hits::total 9475 # number of WriteReq MSHR hits 460system.cpu.dcache.demand_mshr_hits::cpu.data 9760 # number of demand (read+write) MSHR hits 461system.cpu.dcache.demand_mshr_hits::total 9760 # number of demand (read+write) MSHR hits 462system.cpu.dcache.overall_mshr_hits::cpu.data 9760 # number of overall MSHR hits 463system.cpu.dcache.overall_mshr_hits::total 9760 # number of overall MSHR hits 464system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907005 # number of ReadReq MSHR misses 465system.cpu.dcache.ReadReq_mshr_misses::total 907005 # number of ReadReq MSHR misses 466system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316655 # number of WriteReq MSHR misses 467system.cpu.dcache.WriteReq_mshr_misses::total 316655 # number of WriteReq MSHR misses 468system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402762 # number of SoftPFReq MSHR misses 469system.cpu.dcache.SoftPFReq_mshr_misses::total 402762 # number of SoftPFReq MSHR misses 470system.cpu.dcache.demand_mshr_misses::cpu.data 1223660 # number of demand (read+write) MSHR misses 471system.cpu.dcache.demand_mshr_misses::total 1223660 # number of demand (read+write) MSHR misses 472system.cpu.dcache.overall_mshr_misses::cpu.data 1626422 # number of overall MSHR misses 473system.cpu.dcache.overall_mshr_misses::total 1626422 # number of overall MSHR misses 474system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable 475system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable 476system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable 477system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable 478system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses 479system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses 480system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12650383500 # number of ReadReq MSHR miss cycles 481system.cpu.dcache.ReadReq_mshr_miss_latency::total 12650383500 # number of ReadReq MSHR miss cycles 482system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17142668967 # number of WriteReq MSHR miss cycles 483system.cpu.dcache.WriteReq_mshr_miss_latency::total 17142668967 # number of WriteReq MSHR miss cycles 484system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6518448000 # number of SoftPFReq MSHR miss cycles 485system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6518448000 # number of SoftPFReq MSHR miss cycles 486system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29793052467 # number of demand (read+write) MSHR miss cycles 487system.cpu.dcache.demand_mshr_miss_latency::total 29793052467 # number of demand (read+write) MSHR miss cycles 488system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36311500467 # number of overall MSHR miss cycles 489system.cpu.dcache.overall_mshr_miss_latency::total 36311500467 # number of overall MSHR miss cycles 490system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132085000 # number of ReadReq MSHR uncacheable cycles 491system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132085000 # number of ReadReq MSHR uncacheable cycles 492system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 95132085000 # number of overall MSHR uncacheable cycles 493system.cpu.dcache.overall_mshr_uncacheable_latency::total 95132085000 # number of overall MSHR uncacheable cycles 494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070257 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070257 # mshr miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037690 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037690 # mshr miss rate for WriteReq accesses 498system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses 499system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses 500system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057418 # mshr miss rate for demand accesses 501system.cpu.dcache.demand_mshr_miss_rate::total 0.057418 # mshr miss rate for demand accesses 502system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074698 # mshr miss rate for overall accesses 503system.cpu.dcache.overall_mshr_miss_rate::total 0.074698 # mshr miss rate for overall accesses 504system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13947.424215 # average ReadReq mshr miss latency 505system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13947.424215 # average ReadReq mshr miss latency 506system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54136.738618 # average WriteReq mshr miss latency 507system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54136.738618 # average WriteReq mshr miss latency 508system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16184.366946 # average SoftPFReq mshr miss latency 509system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16184.366946 # average SoftPFReq mshr miss latency 510system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24347.492332 # average overall mshr miss latency 511system.cpu.dcache.demand_avg_mshr_miss_latency::total 24347.492332 # average overall mshr miss latency 512system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780 # average overall mshr miss latency 513system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780 # average overall mshr miss latency 514system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442 # average ReadReq mshr uncacheable latency 515system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442 # average ReadReq mshr uncacheable latency 516system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131 # average overall mshr uncacheable latency 517system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131 # average overall mshr uncacheable latency 518system.cpu.dtb_walker_cache.tags.replacements 7581 # number of replacements 519system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use 520system.cpu.dtb_walker_cache.tags.total_refs 13343 # Total number of references to valid blocks. 521system.cpu.dtb_walker_cache.tags.sampled_refs 7597 # Sample count of references to valid blocks. 522system.cpu.dtb_walker_cache.tags.avg_refs 1.756351 # Average number of references to valid blocks. 523system.cpu.dtb_walker_cache.tags.warmup_cycle 5163352546000 # Cycle when the warmup percentage was hit. 524system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor 525system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy 526system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy 527system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id 528system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 529system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 530system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 531system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 532system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 533system.cpu.dtb_walker_cache.tags.tag_accesses 53059 # Number of tag accesses 534system.cpu.dtb_walker_cache.tags.data_accesses 53059 # Number of data accesses 535system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13343 # number of ReadReq hits 536system.cpu.dtb_walker_cache.ReadReq_hits::total 13343 # number of ReadReq hits 537system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13343 # number of demand (read+write) hits 538system.cpu.dtb_walker_cache.demand_hits::total 13343 # number of demand (read+write) hits 539system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13343 # number of overall hits 540system.cpu.dtb_walker_cache.overall_hits::total 13343 # number of overall hits 541system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses 542system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses 543system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses 544system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses 545system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses 546system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses 547system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 96450500 # number of ReadReq miss cycles 548system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 96450500 # number of ReadReq miss cycles 549system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 96450500 # number of demand (read+write) miss cycles 550system.cpu.dtb_walker_cache.demand_miss_latency::total 96450500 # number of demand (read+write) miss cycles 551system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 96450500 # number of overall miss cycles 552system.cpu.dtb_walker_cache.overall_miss_latency::total 96450500 # number of overall miss cycles 553system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22134 # number of ReadReq accesses(hits+misses) 554system.cpu.dtb_walker_cache.ReadReq_accesses::total 22134 # number of ReadReq accesses(hits+misses) 555system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22134 # number of demand (read+write) accesses 556system.cpu.dtb_walker_cache.demand_accesses::total 22134 # number of demand (read+write) accesses 557system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22134 # number of overall (read+write) accesses 558system.cpu.dtb_walker_cache.overall_accesses::total 22134 # number of overall (read+write) accesses 559system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397172 # miss rate for ReadReq accesses 560system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397172 # miss rate for ReadReq accesses 561system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397172 # miss rate for demand accesses 562system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397172 # miss rate for demand accesses 563system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397172 # miss rate for overall accesses 564system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397172 # miss rate for overall accesses 565system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10971.504948 # average ReadReq miss latency 566system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10971.504948 # average ReadReq miss latency 567system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency 568system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10971.504948 # average overall miss latency 569system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency 570system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10971.504948 # average overall miss latency 571system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 572system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 573system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 574system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 575system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 576system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 577system.cpu.dtb_walker_cache.writebacks::writebacks 2983 # number of writebacks 578system.cpu.dtb_walker_cache.writebacks::total 2983 # number of writebacks 579system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8791 # number of ReadReq MSHR misses 580system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8791 # number of ReadReq MSHR misses 581system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8791 # number of demand (read+write) MSHR misses 582system.cpu.dtb_walker_cache.demand_mshr_misses::total 8791 # number of demand (read+write) MSHR misses 583system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8791 # number of overall MSHR misses 584system.cpu.dtb_walker_cache.overall_mshr_misses::total 8791 # number of overall MSHR misses 585system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 87659500 # number of ReadReq MSHR miss cycles 586system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87659500 # number of ReadReq MSHR miss cycles 587system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87659500 # number of demand (read+write) MSHR miss cycles 588system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87659500 # number of demand (read+write) MSHR miss cycles 589system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87659500 # number of overall MSHR miss cycles 590system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87659500 # number of overall MSHR miss cycles 591system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for ReadReq accesses 592system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397172 # mshr miss rate for ReadReq accesses 593system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for demand accesses 594system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397172 # mshr miss rate for demand accesses 595system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for overall accesses 596system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397172 # mshr miss rate for overall accesses 597system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average ReadReq mshr miss latency 598system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9971.504948 # average ReadReq mshr miss latency 599system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency 600system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency 601system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency 602system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency 603system.cpu.icache.tags.replacements 790489 # number of replacements 604system.cpu.icache.tags.tagsinuse 510.213579 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 144635934 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 791001 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 182.851771 # Average number of references to valid blocks. 608system.cpu.icache.tags.warmup_cycle 164551519500 # Cycle when the warmup percentage was hit. 609system.cpu.icache.tags.occ_blocks::cpu.inst 510.213579 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.996511 # Average percentage of cache occupancy 611system.cpu.icache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy 612system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id 616system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 617system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 618system.cpu.icache.tags.tag_accesses 146217950 # Number of tag accesses 619system.cpu.icache.tags.data_accesses 146217950 # Number of data accesses 620system.cpu.icache.ReadReq_hits::cpu.inst 144635934 # number of ReadReq hits 621system.cpu.icache.ReadReq_hits::total 144635934 # number of ReadReq hits 622system.cpu.icache.demand_hits::cpu.inst 144635934 # number of demand (read+write) hits 623system.cpu.icache.demand_hits::total 144635934 # number of demand (read+write) hits 624system.cpu.icache.overall_hits::cpu.inst 144635934 # number of overall hits 625system.cpu.icache.overall_hits::total 144635934 # number of overall hits 626system.cpu.icache.ReadReq_misses::cpu.inst 791008 # number of ReadReq misses 627system.cpu.icache.ReadReq_misses::total 791008 # number of ReadReq misses 628system.cpu.icache.demand_misses::cpu.inst 791008 # number of demand (read+write) misses 629system.cpu.icache.demand_misses::total 791008 # number of demand (read+write) misses 630system.cpu.icache.overall_misses::cpu.inst 791008 # number of overall misses 631system.cpu.icache.overall_misses::total 791008 # number of overall misses 632system.cpu.icache.ReadReq_miss_latency::cpu.inst 11846341000 # number of ReadReq miss cycles 633system.cpu.icache.ReadReq_miss_latency::total 11846341000 # number of ReadReq miss cycles 634system.cpu.icache.demand_miss_latency::cpu.inst 11846341000 # number of demand (read+write) miss cycles 635system.cpu.icache.demand_miss_latency::total 11846341000 # number of demand (read+write) miss cycles 636system.cpu.icache.overall_miss_latency::cpu.inst 11846341000 # number of overall miss cycles 637system.cpu.icache.overall_miss_latency::total 11846341000 # number of overall miss cycles 638system.cpu.icache.ReadReq_accesses::cpu.inst 145426942 # number of ReadReq accesses(hits+misses) 639system.cpu.icache.ReadReq_accesses::total 145426942 # number of ReadReq accesses(hits+misses) 640system.cpu.icache.demand_accesses::cpu.inst 145426942 # number of demand (read+write) accesses 641system.cpu.icache.demand_accesses::total 145426942 # number of demand (read+write) accesses 642system.cpu.icache.overall_accesses::cpu.inst 145426942 # number of overall (read+write) accesses 643system.cpu.icache.overall_accesses::total 145426942 # number of overall (read+write) accesses 644system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005439 # miss rate for ReadReq accesses 645system.cpu.icache.ReadReq_miss_rate::total 0.005439 # miss rate for ReadReq accesses 646system.cpu.icache.demand_miss_rate::cpu.inst 0.005439 # miss rate for demand accesses 647system.cpu.icache.demand_miss_rate::total 0.005439 # miss rate for demand accesses 648system.cpu.icache.overall_miss_rate::cpu.inst 0.005439 # miss rate for overall accesses 649system.cpu.icache.overall_miss_rate::total 0.005439 # miss rate for overall accesses 650system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14976.259406 # average ReadReq miss latency 651system.cpu.icache.ReadReq_avg_miss_latency::total 14976.259406 # average ReadReq miss latency 652system.cpu.icache.demand_avg_miss_latency::cpu.inst 14976.259406 # average overall miss latency 653system.cpu.icache.demand_avg_miss_latency::total 14976.259406 # average overall miss latency 654system.cpu.icache.overall_avg_miss_latency::cpu.inst 14976.259406 # average overall miss latency 655system.cpu.icache.overall_avg_miss_latency::total 14976.259406 # average overall miss latency 656system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 662system.cpu.icache.writebacks::writebacks 790489 # number of writebacks 663system.cpu.icache.writebacks::total 790489 # number of writebacks 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791008 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 791008 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 791008 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 791008 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 791008 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 791008 # number of overall MSHR misses 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055333000 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 11055333000 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055333000 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 11055333000 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055333000 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 11055333000 # number of overall MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005439 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.005439 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.005439 # mshr miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13976.259406 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13976.259406 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency 688system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements 689system.cpu.itb_walker_cache.tags.tagsinuse 3.069456 # Cycle average of tags in use 690system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. 691system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks. 692system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks. 693system.cpu.itb_walker_cache.tags.warmup_cycle 5168951189500 # Cycle when the warmup percentage was hit. 694system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069456 # Average occupied blocks per requestor 695system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191841 # Average percentage of cache occupancy 696system.cpu.itb_walker_cache.tags.occ_percent::total 0.191841 # Average percentage of cache occupancy 697system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 698system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 699system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 700system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 701system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 702system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 703system.cpu.itb_walker_cache.tags.tag_accesses 28685 # Number of tag accesses 704system.cpu.itb_walker_cache.tags.data_accesses 28685 # Number of data accesses 705system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7970 # number of ReadReq hits 706system.cpu.itb_walker_cache.ReadReq_hits::total 7970 # number of ReadReq hits 707system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 708system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 709system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7972 # number of demand (read+write) hits 710system.cpu.itb_walker_cache.demand_hits::total 7972 # number of demand (read+write) hits 711system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7972 # number of overall hits 712system.cpu.itb_walker_cache.overall_hits::total 7972 # number of overall hits 713system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4247 # number of ReadReq misses 714system.cpu.itb_walker_cache.ReadReq_misses::total 4247 # number of ReadReq misses 715system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4247 # number of demand (read+write) misses 716system.cpu.itb_walker_cache.demand_misses::total 4247 # number of demand (read+write) misses 717system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4247 # number of overall misses 718system.cpu.itb_walker_cache.overall_misses::total 4247 # number of overall misses 719system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44856000 # number of ReadReq miss cycles 720system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44856000 # number of ReadReq miss cycles 721system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44856000 # number of demand (read+write) miss cycles 722system.cpu.itb_walker_cache.demand_miss_latency::total 44856000 # number of demand (read+write) miss cycles 723system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44856000 # number of overall miss cycles 724system.cpu.itb_walker_cache.overall_miss_latency::total 44856000 # number of overall miss cycles 725system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses) 726system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses) 727system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 728system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 729system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses 730system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses 731system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses 732system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses 733system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.347630 # miss rate for ReadReq accesses 734system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.347630 # miss rate for ReadReq accesses 735system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.347573 # miss rate for demand accesses 736system.cpu.itb_walker_cache.demand_miss_rate::total 0.347573 # miss rate for demand accesses 737system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.347573 # miss rate for overall accesses 738system.cpu.itb_walker_cache.overall_miss_rate::total 0.347573 # miss rate for overall accesses 739system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10561.808335 # average ReadReq miss latency 740system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10561.808335 # average ReadReq miss latency 741system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10561.808335 # average overall miss latency 742system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10561.808335 # average overall miss latency 743system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10561.808335 # average overall miss latency 744system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10561.808335 # average overall miss latency 745system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 746system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 747system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 748system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 749system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 750system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 751system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks 752system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks 753system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses 754system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4247 # number of ReadReq MSHR misses 755system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4247 # number of demand (read+write) MSHR misses 756system.cpu.itb_walker_cache.demand_mshr_misses::total 4247 # number of demand (read+write) MSHR misses 757system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4247 # number of overall MSHR misses 758system.cpu.itb_walker_cache.overall_mshr_misses::total 4247 # number of overall MSHR misses 759system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 40609000 # number of ReadReq MSHR miss cycles 760system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 40609000 # number of ReadReq MSHR miss cycles 761system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 40609000 # number of demand (read+write) MSHR miss cycles 762system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 40609000 # number of demand (read+write) MSHR miss cycles 763system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 40609000 # number of overall MSHR miss cycles 764system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 40609000 # number of overall MSHR miss cycles 765system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.347630 # mshr miss rate for ReadReq accesses 766system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.347630 # mshr miss rate for ReadReq accesses 767system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for demand accesses 768system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.347573 # mshr miss rate for demand accesses 769system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for overall accesses 770system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.347573 # mshr miss rate for overall accesses 771system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average ReadReq mshr miss latency 772system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9561.808335 # average ReadReq mshr miss latency 773system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency 774system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency 775system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency 776system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency 777system.cpu.l2cache.tags.replacements 87287 # number of replacements 778system.cpu.l2cache.tags.tagsinuse 64590.438483 # Cycle average of tags in use 779system.cpu.l2cache.tags.total_refs 4366272 # Total number of references to valid blocks. 780system.cpu.l2cache.tags.sampled_refs 151983 # Sample count of references to valid blocks. 781system.cpu.l2cache.tags.avg_refs 28.728687 # Average number of references to valid blocks. 782system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 783system.cpu.l2cache.tags.occ_blocks::writebacks 50117.131899 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006347 # Average occupied blocks per requestor 785system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146883 # Average occupied blocks per requestor 786system.cpu.l2cache.tags.occ_blocks::cpu.inst 3409.599295 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.554060 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_percent::writebacks 0.764727 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052026 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::cpu.data 0.168816 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_percent::total 0.985572 # Average percentage of cache occupancy 794system.cpu.l2cache.tags.occ_task_id_blocks::1024 64696 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 796system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 797system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2801 # Occupied blocks per task id 798system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5467 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56270 # Occupied blocks per task id 800system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987183 # Percentage of cache occupancy per task id 801system.cpu.l2cache.tags.tag_accesses 39228445 # Number of tag accesses 802system.cpu.l2cache.tags.data_accesses 39228445 # Number of data accesses 803system.cpu.l2cache.WritebackDirty_hits::writebacks 1544529 # number of WritebackDirty hits 804system.cpu.l2cache.WritebackDirty_hits::total 1544529 # number of WritebackDirty hits 805system.cpu.l2cache.WritebackClean_hits::writebacks 790476 # number of WritebackClean hits 806system.cpu.l2cache.WritebackClean_hits::total 790476 # number of WritebackClean hits 807system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits 808system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits 809system.cpu.l2cache.ReadExReq_hits::cpu.data 200921 # number of ReadExReq hits 810system.cpu.l2cache.ReadExReq_hits::total 200921 # number of ReadExReq hits 811system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 778162 # number of ReadCleanReq hits 812system.cpu.l2cache.ReadCleanReq_hits::total 778162 # number of ReadCleanReq hits 813system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6471 # number of ReadSharedReq hits 814system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2853 # number of ReadSharedReq hits 815system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280522 # number of ReadSharedReq hits 816system.cpu.l2cache.ReadSharedReq_hits::total 1289846 # number of ReadSharedReq hits 817system.cpu.l2cache.demand_hits::cpu.dtb.walker 6471 # number of demand (read+write) hits 818system.cpu.l2cache.demand_hits::cpu.itb.walker 2853 # number of demand (read+write) hits 819system.cpu.l2cache.demand_hits::cpu.inst 778162 # number of demand (read+write) hits 820system.cpu.l2cache.demand_hits::cpu.data 1481443 # number of demand (read+write) hits 821system.cpu.l2cache.demand_hits::total 2268929 # number of demand (read+write) hits 822system.cpu.l2cache.overall_hits::cpu.dtb.walker 6471 # number of overall hits 823system.cpu.l2cache.overall_hits::cpu.itb.walker 2853 # number of overall hits 824system.cpu.l2cache.overall_hits::cpu.inst 778162 # number of overall hits 825system.cpu.l2cache.overall_hits::cpu.data 1481443 # number of overall hits 826system.cpu.l2cache.overall_hits::total 2268929 # number of overall hits 827system.cpu.l2cache.UpgradeReq_misses::cpu.data 1406 # number of UpgradeReq misses 828system.cpu.l2cache.UpgradeReq_misses::total 1406 # number of UpgradeReq misses 829system.cpu.l2cache.ReadExReq_misses::cpu.data 113511 # number of ReadExReq misses 830system.cpu.l2cache.ReadExReq_misses::total 113511 # number of ReadExReq misses 831system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12833 # number of ReadCleanReq misses 832system.cpu.l2cache.ReadCleanReq_misses::total 12833 # number of ReadCleanReq misses 833system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses 834system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses 835system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28496 # number of ReadSharedReq misses 836system.cpu.l2cache.ReadSharedReq_misses::total 28502 # number of ReadSharedReq misses 837system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 838system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 839system.cpu.l2cache.demand_misses::cpu.inst 12833 # number of demand (read+write) misses 840system.cpu.l2cache.demand_misses::cpu.data 142007 # number of demand (read+write) misses 841system.cpu.l2cache.demand_misses::total 154846 # number of demand (read+write) misses 842system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 843system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 844system.cpu.l2cache.overall_misses::cpu.inst 12833 # number of overall misses 845system.cpu.l2cache.overall_misses::cpu.data 142007 # number of overall misses 846system.cpu.l2cache.overall_misses::total 154846 # number of overall misses 847system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 52182500 # number of UpgradeReq miss cycles 848system.cpu.l2cache.UpgradeReq_miss_latency::total 52182500 # number of UpgradeReq miss cycles 849system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14440315000 # number of ReadExReq miss cycles 850system.cpu.l2cache.ReadExReq_miss_latency::total 14440315000 # number of ReadExReq miss cycles 851system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1688067000 # number of ReadCleanReq miss cycles 852system.cpu.l2cache.ReadCleanReq_miss_latency::total 1688067000 # number of ReadCleanReq miss cycles 853system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 119000 # number of ReadSharedReq miss cycles 854system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 637500 # number of ReadSharedReq miss cycles 855system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3748293500 # number of ReadSharedReq miss cycles 856system.cpu.l2cache.ReadSharedReq_miss_latency::total 3749050000 # number of ReadSharedReq miss cycles 857system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 119000 # number of demand (read+write) miss cycles 858system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 637500 # number of demand (read+write) miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 1688067000 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 18188608500 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 19877432000 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 119000 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 637500 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::cpu.inst 1688067000 # number of overall miss cycles 865system.cpu.l2cache.overall_miss_latency::cpu.data 18188608500 # number of overall miss cycles 866system.cpu.l2cache.overall_miss_latency::total 19877432000 # number of overall miss cycles 867system.cpu.l2cache.WritebackDirty_accesses::writebacks 1544529 # number of WritebackDirty accesses(hits+misses) 868system.cpu.l2cache.WritebackDirty_accesses::total 1544529 # number of WritebackDirty accesses(hits+misses) 869system.cpu.l2cache.WritebackClean_accesses::writebacks 790476 # number of WritebackClean accesses(hits+misses) 870system.cpu.l2cache.WritebackClean_accesses::total 790476 # number of WritebackClean accesses(hits+misses) 871system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1726 # number of UpgradeReq accesses(hits+misses) 872system.cpu.l2cache.UpgradeReq_accesses::total 1726 # number of UpgradeReq accesses(hits+misses) 873system.cpu.l2cache.ReadExReq_accesses::cpu.data 314432 # number of ReadExReq accesses(hits+misses) 874system.cpu.l2cache.ReadExReq_accesses::total 314432 # number of ReadExReq accesses(hits+misses) 875system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 790995 # number of ReadCleanReq accesses(hits+misses) 876system.cpu.l2cache.ReadCleanReq_accesses::total 790995 # number of ReadCleanReq accesses(hits+misses) 877system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6472 # number of ReadSharedReq accesses(hits+misses) 878system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2858 # number of ReadSharedReq accesses(hits+misses) 879system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309018 # number of ReadSharedReq accesses(hits+misses) 880system.cpu.l2cache.ReadSharedReq_accesses::total 1318348 # number of ReadSharedReq accesses(hits+misses) 881system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6472 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::cpu.itb.walker 2858 # number of demand (read+write) accesses 883system.cpu.l2cache.demand_accesses::cpu.inst 790995 # number of demand (read+write) accesses 884system.cpu.l2cache.demand_accesses::cpu.data 1623450 # number of demand (read+write) accesses 885system.cpu.l2cache.demand_accesses::total 2423775 # number of demand (read+write) accesses 886system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6472 # number of overall (read+write) accesses 887system.cpu.l2cache.overall_accesses::cpu.itb.walker 2858 # number of overall (read+write) accesses 888system.cpu.l2cache.overall_accesses::cpu.inst 790995 # number of overall (read+write) accesses 889system.cpu.l2cache.overall_accesses::cpu.data 1623450 # number of overall (read+write) accesses 890system.cpu.l2cache.overall_accesses::total 2423775 # number of overall (read+write) accesses 891system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814600 # miss rate for UpgradeReq accesses 892system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814600 # miss rate for UpgradeReq accesses 893system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361003 # miss rate for ReadExReq accesses 894system.cpu.l2cache.ReadExReq_miss_rate::total 0.361003 # miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016224 # miss rate for ReadCleanReq accesses 896system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016224 # miss rate for ReadCleanReq accesses 897system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000155 # miss rate for ReadSharedReq accesses 898system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001749 # miss rate for ReadSharedReq accesses 899system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021769 # miss rate for ReadSharedReq accesses 900system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021619 # miss rate for ReadSharedReq accesses 901system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000155 # miss rate for demand accesses 902system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001749 # miss rate for demand accesses 903system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016224 # miss rate for demand accesses 904system.cpu.l2cache.demand_miss_rate::cpu.data 0.087472 # miss rate for demand accesses 905system.cpu.l2cache.demand_miss_rate::total 0.063886 # miss rate for demand accesses 906system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000155 # miss rate for overall accesses 907system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001749 # miss rate for overall accesses 908system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016224 # miss rate for overall accesses 909system.cpu.l2cache.overall_miss_rate::cpu.data 0.087472 # miss rate for overall accesses 910system.cpu.l2cache.overall_miss_rate::total 0.063886 # miss rate for overall accesses 911system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 37114.153627 # average UpgradeReq miss latency 912system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 37114.153627 # average UpgradeReq miss latency 913system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127215.115716 # average ReadExReq miss latency 914system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127215.115716 # average ReadExReq miss latency 915system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131541.104964 # average ReadCleanReq miss latency 916system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131541.104964 # average ReadCleanReq miss latency 917system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 119000 # average ReadSharedReq miss latency 918system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 127500 # average ReadSharedReq miss latency 919system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131537.531583 # average ReadSharedReq miss latency 920system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131536.383412 # average ReadSharedReq miss latency 921system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 119000 # average overall miss latency 922system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency 923system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131541.104964 # average overall miss latency 924system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128082.478329 # average overall miss latency 925system.cpu.l2cache.demand_avg_miss_latency::total 128369.037624 # average overall miss latency 926system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 119000 # average overall miss latency 927system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency 928system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131541.104964 # average overall miss latency 929system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128082.478329 # average overall miss latency 930system.cpu.l2cache.overall_avg_miss_latency::total 128369.037624 # average overall miss latency 931system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 932system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 933system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 934system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 935system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 936system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 937system.cpu.l2cache.writebacks::writebacks 80702 # number of writebacks 938system.cpu.l2cache.writebacks::total 80702 # number of writebacks 939system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 940system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 941system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1406 # number of UpgradeReq MSHR misses 942system.cpu.l2cache.UpgradeReq_mshr_misses::total 1406 # number of UpgradeReq MSHR misses 943system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113511 # number of ReadExReq MSHR misses 944system.cpu.l2cache.ReadExReq_mshr_misses::total 113511 # number of ReadExReq MSHR misses 945system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12833 # number of ReadCleanReq MSHR misses 946system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12833 # number of ReadCleanReq MSHR misses 947system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 1 # number of ReadSharedReq MSHR misses 948system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses 949system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28496 # number of ReadSharedReq MSHR misses 950system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28502 # number of ReadSharedReq MSHR misses 951system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses 952system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 953system.cpu.l2cache.demand_mshr_misses::cpu.inst 12833 # number of demand (read+write) MSHR misses 954system.cpu.l2cache.demand_mshr_misses::cpu.data 142007 # number of demand (read+write) MSHR misses 955system.cpu.l2cache.demand_mshr_misses::total 154846 # number of demand (read+write) MSHR misses 956system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses 957system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 958system.cpu.l2cache.overall_mshr_misses::cpu.inst 12833 # number of overall MSHR misses 959system.cpu.l2cache.overall_mshr_misses::cpu.data 142007 # number of overall MSHR misses 960system.cpu.l2cache.overall_mshr_misses::total 154846 # number of overall MSHR misses 961system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable 962system.cpu.l2cache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable 963system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable 964system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable 965system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses 966system.cpu.l2cache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses 967system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 96565500 # number of UpgradeReq MSHR miss cycles 968system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 96565500 # number of UpgradeReq MSHR miss cycles 969system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13305205000 # number of ReadExReq MSHR miss cycles 970system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13305205000 # number of ReadExReq MSHR miss cycles 971system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1559737000 # number of ReadCleanReq MSHR miss cycles 972system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1559737000 # number of ReadCleanReq MSHR miss cycles 973system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 109000 # number of ReadSharedReq MSHR miss cycles 974system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 587500 # number of ReadSharedReq MSHR miss cycles 975system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3463333500 # number of ReadSharedReq MSHR miss cycles 976system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3464030000 # number of ReadSharedReq MSHR miss cycles 977system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 109000 # number of demand (read+write) MSHR miss cycles 978system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles 979system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1559737000 # number of demand (read+write) MSHR miss cycles 980system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16768538500 # number of demand (read+write) MSHR miss cycles 981system.cpu.l2cache.demand_mshr_miss_latency::total 18328972000 # number of demand (read+write) MSHR miss cycles 982system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 109000 # number of overall MSHR miss cycles 983system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles 984system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1559737000 # number of overall MSHR miss cycles 985system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16768538500 # number of overall MSHR miss cycles 986system.cpu.l2cache.overall_mshr_miss_latency::total 18328972000 # number of overall MSHR miss cycles 987system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302755000 # number of ReadReq MSHR uncacheable cycles 988system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302755000 # number of ReadReq MSHR uncacheable cycles 989system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88302755000 # number of overall MSHR uncacheable cycles 990system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88302755000 # number of overall MSHR uncacheable cycles 991system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 992system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 993system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses 994system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses 995system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361003 # mshr miss rate for ReadExReq accesses 996system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361003 # mshr miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for ReadCleanReq accesses 998system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016224 # mshr miss rate for ReadCleanReq accesses 999system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for ReadSharedReq accesses 1000system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for ReadSharedReq accesses 1001system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021769 # mshr miss rate for ReadSharedReq accesses 1002system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021619 # mshr miss rate for ReadSharedReq accesses 1003system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for demand accesses 1004system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for demand accesses 1005system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for demand accesses 1006system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087472 # mshr miss rate for demand accesses 1007system.cpu.l2cache.demand_mshr_miss_rate::total 0.063886 # mshr miss rate for demand accesses 1008system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for overall accesses 1009system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for overall accesses 1010system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for overall accesses 1011system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087472 # mshr miss rate for overall accesses 1012system.cpu.l2cache.overall_mshr_miss_rate::total 0.063886 # mshr miss rate for overall accesses 1013system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68681.009957 # average UpgradeReq mshr miss latency 1014system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68681.009957 # average UpgradeReq mshr miss latency 1015system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117215.115716 # average ReadExReq mshr miss latency 1016system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117215.115716 # average ReadExReq mshr miss latency 1017system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121541.104964 # average ReadCleanReq mshr miss latency 1018system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121541.104964 # average ReadCleanReq mshr miss latency 1019system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average ReadSharedReq mshr miss latency 1020system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency 1021system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121537.531583 # average ReadSharedReq mshr miss latency 1022system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121536.383412 # average ReadSharedReq mshr miss latency 1023system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency 1024system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency 1025system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency 1026system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency 1027system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency 1028system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency 1029system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency 1030system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency 1031system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency 1032system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency 1033system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290 # average ReadReq mshr uncacheable latency 1034system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290 # average ReadReq mshr uncacheable latency 1035system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974 # average overall mshr uncacheable latency 1036system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974 # average overall mshr uncacheable latency 1037system.cpu.toL2Bus.snoop_filter.tot_requests 4855602 # Total number of requests made to the snoop filter. 1038system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425060 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1039system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1040system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. 1041system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1042system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1043system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution 1044system.cpu.toL2Bus.trans_dist::ReadResp 2660470 # Transaction distribution 1045system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution 1046system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution 1047system.cpu.toL2Bus.trans_dist::WritebackDirty 1671913 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::WritebackClean 790489 # Transaction distribution 1049system.cpu.toL2Bus.trans_dist::CleanEvict 97528 # Transaction distribution 1050system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution 1051system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution 1052system.cpu.toL2Bus.trans_dist::ReadExReq 314438 # Transaction distribution 1053system.cpu.toL2Bus.trans_dist::ReadExResp 314438 # Transaction distribution 1054system.cpu.toL2Bus.trans_dist::ReadCleanReq 791008 # Transaction distribution 1055system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323647 # Transaction distribution 1056system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution 1057system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution 1058system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372492 # Packet count per connected master and slave (bytes) 1059system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5996122 # Packet count per connected master and slave (bytes) 1060system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10488 # Packet count per connected master and slave (bytes) 1061system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22844 # Packet count per connected master and slave (bytes) 1062system.cpu.toL2Bus.pkt_count::total 8401946 # Packet count per connected master and slave (bytes) 1063system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101214976 # Cumulative packet size per connected master and slave (bytes) 1064system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204098920 # Cumulative packet size per connected master and slave (bytes) 1065system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232384 # Cumulative packet size per connected master and slave (bytes) 1066system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605120 # Cumulative packet size per connected master and slave (bytes) 1067system.cpu.toL2Bus.pkt_size::total 306151400 # Cumulative packet size per connected master and slave (bytes) 1068system.cpu.toL2Bus.snoops 189316 # Total snoops (count) 1069system.cpu.toL2Bus.snoop_fanout::samples 3174772 # Request fanout histogram 1070system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram 1071system.cpu.toL2Bus.snoop_fanout::stdev 0.077876 # Request fanout histogram 1072system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1073system.cpu.toL2Bus.snoop_fanout::0 3163038 99.63% 99.63% # Request fanout histogram 1074system.cpu.toL2Bus.snoop_fanout::1 9206 0.29% 99.92% # Request fanout histogram 1075system.cpu.toL2Bus.snoop_fanout::2 2528 0.08% 100.00% # Request fanout histogram 1076system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram 1077system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1078system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1079system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1080system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1081system.cpu.toL2Bus.snoop_fanout::total 3174772 # Request fanout histogram 1082system.cpu.toL2Bus.reqLayer0.occupancy 5049912000 # Layer occupancy (ticks) 1083system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1084system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks) 1085system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1086system.cpu.toL2Bus.respLayer0.occupancy 1186512000 # Layer occupancy (ticks) 1087system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1088system.cpu.toL2Bus.respLayer1.occupancy 2990732492 # Layer occupancy (ticks) 1089system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1090system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks) 1091system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1092system.cpu.toL2Bus.respLayer3.occupancy 13186500 # Layer occupancy (ticks) 1093system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1094system.iobus.trans_dist::ReadReq 216035 # Transaction distribution 1095system.iobus.trans_dist::ReadResp 216035 # Transaction distribution 1096system.iobus.trans_dist::WriteReq 57726 # Transaction distribution 1097system.iobus.trans_dist::WriteResp 57726 # Transaction distribution 1098system.iobus.trans_dist::MessageReq 1654 # Transaction distribution 1099system.iobus.trans_dist::MessageResp 1654 # Transaction distribution 1100system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1104system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1105system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1106system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1107system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 408166 # Packet count per connected master and slave (bytes) 1108system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1109system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1110system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1111system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1112system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1113system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1114system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1115system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1116system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) 1117system.iobus.pkt_count_system.bridge.master::total 452398 # Packet count per connected master and slave (bytes) 1118system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) 1119system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) 1120system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) 1121system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) 1122system.iobus.pkt_count::total 550830 # Packet count per connected master and slave (bytes) 1123system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 204083 # Cumulative packet size per connected master and slave (bytes) 1131system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1132system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1133system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1134system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1135system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1136system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1137system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1138system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1139system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) 1140system.iobus.pkt_size_system.bridge.master::total 232479 # Cumulative packet size per connected master and slave (bytes) 1141system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) 1142system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) 1143system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) 1145system.iobus.pkt_size::total 3266375 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.reqLayer0.occupancy 4014316 # Layer occupancy (ticks) 1147system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1148system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1149system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1150system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1151system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1152system.iobus.reqLayer3.occupancy 10060500 # Layer occupancy (ticks) 1153system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1154system.iobus.reqLayer4.occupancy 1094500 # Layer occupancy (ticks) 1155system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1156system.iobus.reqLayer5.occupancy 79000 # Layer occupancy (ticks) 1157system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1158system.iobus.reqLayer6.occupancy 50500 # Layer occupancy (ticks) 1159system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1160system.iobus.reqLayer7.occupancy 26000 # Layer occupancy (ticks) 1161system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1162system.iobus.reqLayer8.occupancy 306124500 # Layer occupancy (ticks) 1163system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1164system.iobus.reqLayer9.occupancy 1113000 # Layer occupancy (ticks) 1165system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1166system.iobus.reqLayer10.occupancy 177500 # Layer occupancy (ticks) 1167system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1168system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 1169system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1170system.iobus.reqLayer13.occupancy 24285000 # Layer occupancy (ticks) 1171system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1172system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 1173system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1174system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 1175system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1176system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) 1177system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1178system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1179system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1180system.iobus.reqLayer18.occupancy 241923874 # Layer occupancy (ticks) 1181system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1182system.iobus.reqLayer19.occupancy 1216500 # Layer occupancy (ticks) 1183system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1184system.iobus.respLayer0.occupancy 441392000 # Layer occupancy (ticks) 1185system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1186system.iobus.respLayer1.occupancy 50036000 # Layer occupancy (ticks) 1187system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1188system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) 1189system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1190system.iocache.tags.replacements 47507 # number of replacements 1191system.iocache.tags.tagsinuse 0.108260 # Cycle average of tags in use 1192system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1193system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. 1194system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1195system.iocache.tags.warmup_cycle 5048330957000 # Cycle when the warmup percentage was hit. 1196system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108260 # Average occupied blocks per requestor 1197system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy 1198system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy 1199system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1200system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1201system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1202system.iocache.tags.tag_accesses 428058 # Number of tag accesses 1203system.iocache.tags.data_accesses 428058 # Number of data accesses 1204system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses 1205system.iocache.ReadReq_misses::total 842 # number of ReadReq misses 1206system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1207system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses 1208system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses 1209system.iocache.demand_misses::total 47562 # number of demand (read+write) misses 1210system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses 1211system.iocache.overall_misses::total 47562 # number of overall misses 1212system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138525690 # number of ReadReq miss cycles 1213system.iocache.ReadReq_miss_latency::total 138525690 # number of ReadReq miss cycles 1214system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867864184 # number of WriteLineReq miss cycles 1215system.iocache.WriteLineReq_miss_latency::total 5867864184 # number of WriteLineReq miss cycles 1216system.iocache.demand_miss_latency::pc.south_bridge.ide 6006389874 # number of demand (read+write) miss cycles 1217system.iocache.demand_miss_latency::total 6006389874 # number of demand (read+write) miss cycles 1218system.iocache.overall_miss_latency::pc.south_bridge.ide 6006389874 # number of overall miss cycles 1219system.iocache.overall_miss_latency::total 6006389874 # number of overall miss cycles 1220system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) 1221system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) 1222system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1223system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) 1224system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses 1225system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses 1226system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses 1227system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses 1228system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1229system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1230system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1231system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1232system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1233system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1234system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1235system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1236system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average ReadReq miss latency 1237system.iocache.ReadReq_avg_miss_latency::total 164519.821853 # average ReadReq miss latency 1238system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048 # average WriteLineReq miss latency 1239system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048 # average WriteLineReq miss latency 1240system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency 1241system.iocache.demand_avg_miss_latency::total 126285.477356 # average overall miss latency 1242system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency 1243system.iocache.overall_avg_miss_latency::total 126285.477356 # average overall miss latency 1244system.iocache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked 1245system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1246system.iocache.blocked::no_mshrs 33 # number of cycles access was blocked 1247system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1248system.iocache.avg_blocked_cycles::no_mshrs 12.969697 # average number of cycles each access was blocked 1249system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1250system.iocache.writebacks::writebacks 46667 # number of writebacks 1251system.iocache.writebacks::total 46667 # number of writebacks 1252system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses 1253system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses 1254system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1255system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses 1256system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses 1257system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses 1258system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses 1259system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses 1260system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of ReadReq MSHR miss cycles 1261system.iocache.ReadReq_mshr_miss_latency::total 96425690 # number of ReadReq MSHR miss cycles 1262system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530059456 # number of WriteLineReq MSHR miss cycles 1263system.iocache.WriteLineReq_mshr_miss_latency::total 3530059456 # number of WriteLineReq MSHR miss cycles 1264system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of demand (read+write) MSHR miss cycles 1265system.iocache.demand_mshr_miss_latency::total 3626485146 # number of demand (read+write) MSHR miss cycles 1266system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of overall MSHR miss cycles 1267system.iocache.overall_mshr_miss_latency::total 3626485146 # number of overall MSHR miss cycles 1268system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1269system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1270system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1271system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1272system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1273system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1274system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1275system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1276system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average ReadReq mshr miss latency 1277system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853 # average ReadReq mshr miss latency 1278system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452 # average WriteLineReq mshr miss latency 1279system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452 # average WriteLineReq mshr miss latency 1280system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency 1281system.iocache.demand_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency 1282system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency 1283system.iocache.overall_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency 1284system.membus.trans_dist::ReadReq 546346 # Transaction distribution 1285system.membus.trans_dist::ReadResp 588523 # Transaction distribution 1286system.membus.trans_dist::WriteReq 13920 # Transaction distribution 1287system.membus.trans_dist::WriteResp 13920 # Transaction distribution 1288system.membus.trans_dist::WritebackDirty 127369 # Transaction distribution 1289system.membus.trans_dist::CleanEvict 7403 # Transaction distribution 1290system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution 1291system.membus.trans_dist::UpgradeResp 18 # Transaction distribution 1292system.membus.trans_dist::ReadExReq 113265 # Transaction distribution 1293system.membus.trans_dist::ReadExResp 113265 # Transaction distribution 1294system.membus.trans_dist::ReadSharedReq 42177 # Transaction distribution 1295system.membus.trans_dist::MessageReq 1654 # Transaction distribution 1296system.membus.trans_dist::MessageResp 1654 # Transaction distribution 1297system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 1298system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) 1299system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) 1300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 452398 # Packet count per connected master and slave (bytes) 1301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 668134 # Packet count per connected master and slave (bytes) 1302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397971 # Packet count per connected master and slave (bytes) 1303system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1518503 # Packet count per connected master and slave (bytes) 1304system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95512 # Packet count per connected master and slave (bytes) 1305system.membus.pkt_count_system.iocache.mem_side::total 95512 # Packet count per connected master and slave (bytes) 1306system.membus.pkt_count::total 1617323 # Packet count per connected master and slave (bytes) 1307system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) 1308system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) 1309system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 232479 # Cumulative packet size per connected master and slave (bytes) 1310system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1336265 # Cumulative packet size per connected master and slave (bytes) 1311system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017728 # Cumulative packet size per connected master and slave (bytes) 1312system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586472 # Cumulative packet size per connected master and slave (bytes) 1313system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) 1314system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) 1315system.membus.pkt_size::total 19608128 # Cumulative packet size per connected master and slave (bytes) 1316system.membus.snoops 1571 # Total snoops (count) 1317system.membus.snoop_fanout::samples 901025 # Request fanout histogram 1318system.membus.snoop_fanout::mean 1.001836 # Request fanout histogram 1319system.membus.snoop_fanout::stdev 0.042806 # Request fanout histogram 1320system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1321system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1322system.membus.snoop_fanout::1 899371 99.82% 99.82% # Request fanout histogram 1323system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram 1324system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1325system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1326system.membus.snoop_fanout::max_value 2 # Request fanout histogram 1327system.membus.snoop_fanout::total 901025 # Request fanout histogram 1328system.membus.reqLayer0.occupancy 344310500 # Layer occupancy (ticks) 1329system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1330system.membus.reqLayer1.occupancy 503566000 # Layer occupancy (ticks) 1331system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1332system.membus.reqLayer2.occupancy 4013684 # Layer occupancy (ticks) 1333system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1334system.membus.reqLayer3.occupancy 852733442 # Layer occupancy (ticks) 1335system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1336system.membus.respLayer0.occupancy 2359684 # Layer occupancy (ticks) 1337system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1338system.membus.respLayer2.occupancy 1924956500 # Layer occupancy (ticks) 1339system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1340system.membus.respLayer4.occupancy 4280140 # Layer occupancy (ticks) 1341system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1342system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1343system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1344system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1345system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1346system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1347system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1348system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1349system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1350system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1351system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1352system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1353system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1354 1355---------- End Simulation Statistics ---------- 1356