15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 1.865014 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 1865014104500 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 1865014104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 231832 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 231832 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 8163594872 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 339292 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 228.46 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 52963270 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 52963270 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 962304 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory 1910352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25843264 # Number of bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 962304 # Number of instructions bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 962304 # Number of instructions bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7514304 # Number of bytes written to this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7514304 # Number of bytes written to this memory 2511860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15036 # Number of read requests responded to by this memory 2611860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory 2710352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2811860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 403801 # Number of read requests responded to by this memory 2911860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117411 # Number of write requests responded to by this memory 3011860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117411 # Number of write requests responded to by this memory 3111860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 515977 # Total read bandwidth from this memory (bytes/s) 3211860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13340382 # Total read bandwidth from this memory (bytes/s) 3311680SCurtis.Dunham@arm.comsystem.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) 3411860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13856873 # Total read bandwidth from this memory (bytes/s) 3511860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 515977 # Instruction read bandwidth from this memory (bytes/s) 3611860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 515977 # Instruction read bandwidth from this memory (bytes/s) 3711860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4029087 # Write bandwidth from this memory (bytes/s) 3811860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4029087 # Write bandwidth from this memory (bytes/s) 3911860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4029087 # Total bandwidth to/from this memory (bytes/s) 4011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 515977 # Total bandwidth to/from this memory (bytes/s) 4111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13340382 # Total bandwidth to/from this memory (bytes/s) 4211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) 4311860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17885960 # Total bandwidth to/from this memory (bytes/s) 4411860Sandreas.hansson@arm.comsystem.physmem.readReqs 403801 # Number of read requests accepted 4511860Sandreas.hansson@arm.comsystem.physmem.writeReqs 117411 # Number of write requests accepted 4611860Sandreas.hansson@arm.comsystem.physmem.readBursts 403801 # Number of DRAM read bursts, including those serviced by the write queue 4711860Sandreas.hansson@arm.comsystem.physmem.writeBursts 117411 # Number of DRAM write bursts, including those merged in the write queue 4811860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25836480 # Total number of bytes read from DRAM 4911860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue 5011860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7512704 # Total number of bytes written to DRAM 5111860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25843264 # Total read bytes from the system interface side 5211860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7514304 # Total written bytes from the system interface side 5311860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue 5410892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 25442 # Per bank write bursts 5711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25616 # Per bank write bursts 5811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25500 # Per bank write bursts 5911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25612 # Per bank write bursts 6011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25113 # Per bank write bursts 6111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 25182 # Per bank write bursts 6211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 24743 # Per bank write bursts 6311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 24567 # Per bank write bursts 6411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 25026 # Per bank write bursts 6511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25298 # Per bank write bursts 6611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25283 # Per bank write bursts 6711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25011 # Per bank write bursts 6811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 24384 # Per bank write bursts 6911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25424 # Per bank write bursts 7011754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25804 # Per bank write bursts 7111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25690 # Per bank write bursts 7211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7803 # Per bank write bursts 7311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7588 # Per bank write bursts 7411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7778 # Per bank write bursts 7511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7603 # Per bank write bursts 7611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7231 # Per bank write bursts 7711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 7190 # Per bank write bursts 7811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6745 # Per bank write bursts 7911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6418 # Per bank write bursts 8011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7146 # Per bank write bursts 8111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6920 # Per bank write bursts 8211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7197 # Per bank write bursts 8311754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 7005 # Per bank write bursts 8411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 6963 # Per bank write bursts 8511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7878 # Per bank write bursts 8611754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8018 # Per bank write bursts 8711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7903 # Per bank write bursts 889978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8911860Sandreas.hansson@arm.comsystem.physmem.numWrRetry 61 # Number of times write queue was full causing retry 9011860Sandreas.hansson@arm.comsystem.physmem.totGap 1865008869500 # Total gap between requests 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9711860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 403801 # Read request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10411860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117411 # Write request sizes (log2) 10511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 314099 # What read queue length does an incoming req see 10611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 36538 # What read queue length does an incoming req see 10711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 28723 # What read queue length does an incoming req see 10811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 24204 # What read queue length does an incoming req see 10911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 112 # What read queue length does an incoming req see 11011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see 11111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 11210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1279978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1448 # What write queue length does an incoming req see 15311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2637 # What write queue length does an incoming req see 15411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 3274 # What write queue length does an incoming req see 15511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4234 # What write queue length does an incoming req see 15611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5587 # What write queue length does an incoming req see 15711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6330 # What write queue length does an incoming req see 15811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 7129 # What write queue length does an incoming req see 15911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 8248 # What write queue length does an incoming req see 16011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 6711 # What write queue length does an incoming req see 16111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 7309 # What write queue length does an incoming req see 16211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 7904 # What write queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 7622 # What write queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 6934 # What write queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 6969 # What write queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 6828 # What write queue length does an incoming req see 16711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7215 # What write queue length does an incoming req see 16811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6061 # What write queue length does an incoming req see 16911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 6274 # What write queue length does an incoming req see 17011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 775 # What write queue length does an incoming req see 17111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see 17211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see 17311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see 17411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 248 # What write queue length does an incoming req see 17511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 294 # What write queue length does an incoming req see 17611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 279 # What write queue length does an incoming req see 17711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 270 # What write queue length does an incoming req see 17811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 240 # What write queue length does an incoming req see 17911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 260 # What write queue length does an incoming req see 18011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 347 # What write queue length does an incoming req see 18111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 358 # What write queue length does an incoming req see 18211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see 18311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see 18411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see 18511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see 18611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 355 # What write queue length does an incoming req see 18711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see 18811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see 18911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see 19011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 196 # What write queue length does an incoming req see 19111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see 19211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see 19311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 291 # What write queue length does an incoming req see 19411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 216 # What write queue length does an incoming req see 19511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see 19611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 341 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 267 # What write queue length does an incoming req see 19811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 194 # What write queue length does an incoming req see 19911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see 20011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 139 # What write queue length does an incoming req see 20111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 61269 # Bytes accessed per row activation 20211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 544.301360 # Bytes accessed per row activation 20311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 334.095290 # Bytes accessed per row activation 20411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 417.294475 # Bytes accessed per row activation 20511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13441 21.94% 21.94% # Bytes accessed per row activation 20611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 10649 17.38% 39.32% # Bytes accessed per row activation 20711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4420 7.21% 46.53% # Bytes accessed per row activation 20811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2704 4.41% 50.95% # Bytes accessed per row activation 20911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2252 3.68% 54.62% # Bytes accessed per row activation 21011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1833 2.99% 57.61% # Bytes accessed per row activation 21111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1848 3.02% 60.63% # Bytes accessed per row activation 21211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1534 2.50% 63.13% # Bytes accessed per row activation 21311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 22588 36.87% 100.00% # Bytes accessed per row activation 21411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 61269 # Bytes accessed per row activation 21511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5165 # Reads before turning the bus around for writes 21611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 78.156438 # Reads before turning the bus around for writes 21711860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2937.375866 # Reads before turning the bus around for writes 21811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5162 99.94% 99.94% # Reads before turning the bus around for writes 21911441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 22011441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 22111441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 22211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5165 # Reads before turning the bus around for writes 22311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5165 # Writes before turning the bus around for reads 22411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.727202 # Writes before turning the bus around for reads 22511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.973066 # Writes before turning the bus around for reads 22611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 23.761118 # Writes before turning the bus around for reads 22711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 4630 89.64% 89.64% # Writes before turning the bus around for reads 22811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 34 0.66% 90.30% # Writes before turning the bus around for reads 22911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 183 3.54% 93.84% # Writes before turning the bus around for reads 23011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 6 0.12% 93.96% # Writes before turning the bus around for reads 23111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 3 0.06% 94.02% # Writes before turning the bus around for reads 23211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 17 0.33% 94.35% # Writes before turning the bus around for reads 23311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 10 0.19% 94.54% # Writes before turning the bus around for reads 23411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 3 0.06% 94.60% # Writes before turning the bus around for reads 23511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 30 0.58% 95.18% # Writes before turning the bus around for reads 23611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 4 0.08% 95.26% # Writes before turning the bus around for reads 23711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 158 3.06% 98.32% # Writes before turning the bus around for reads 23811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 16 0.31% 98.63% # Writes before turning the bus around for reads 23911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 13 0.25% 98.88% # Writes before turning the bus around for reads 24011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 4 0.08% 98.95% # Writes before turning the bus around for reads 24111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 6 0.12% 99.07% # Writes before turning the bus around for reads 24211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 2 0.04% 99.11% # Writes before turning the bus around for reads 24311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 1 0.02% 99.13% # Writes before turning the bus around for reads 24411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 2 0.04% 99.17% # Writes before turning the bus around for reads 24511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 3 0.06% 99.23% # Writes before turning the bus around for reads 24611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 6 0.12% 99.34% # Writes before turning the bus around for reads 24711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 6 0.12% 99.46% # Writes before turning the bus around for reads 24811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 9 0.17% 99.63% # Writes before turning the bus around for reads 24911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 8 0.15% 99.79% # Writes before turning the bus around for reads 25011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads 25111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 5 0.10% 99.92% # Writes before turning the bus around for reads 25211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads 25311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::232-239 1 0.02% 99.98% # Writes before turning the bus around for reads 25411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 25511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5165 # Writes before turning the bus around for reads 25611860Sandreas.hansson@arm.comsystem.physmem.totQLat 7762770500 # Total ticks spent queuing 25711860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 15332051750 # Total ticks spent from burst creation until serviced by the DRAM 25811860Sandreas.hansson@arm.comsystem.physmem.totBusLat 2018475000 # Total ticks spent in databus transfers 25911860Sandreas.hansson@arm.comsystem.physmem.avgQLat 19229.30 # Average queueing delay per DRAM burst 2609978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 26111860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 37979.30 # Average memory access latency per DRAM burst 26211680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s 26311680SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s 26411680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s 26511680SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s 2669978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 26710726Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 26810352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 26910892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 27011860Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing 27111860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing 27211860Sandreas.hansson@arm.comsystem.physmem.readRowHits 364450 # Number of row buffer hits during reads 27311860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95361 # Number of row buffer hits during writes 27411754Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads 27511860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.22 # Row buffer hit rate for writes 27611860Sandreas.hansson@arm.comsystem.physmem.avgGap 3578215.52 # Average gap between requests 27711860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined 27811860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 215406660 # Energy for activate commands per rank (pJ) 27911860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 114491355 # Energy for precharge commands per rank (pJ) 28011860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1440673500 # Energy for read commands per rank (pJ) 28111860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 304618320 # Energy for write commands per rank (pJ) 28211860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3636824880.000001 # Energy for refresh commands per rank (pJ) 28311860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 4141323030 # Energy for active background per rank (pJ) 28411860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 240547200 # Energy for precharge background per rank (pJ) 28511860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 8014976340 # Energy for active power-down per rank (pJ) 28611860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 4268063520 # Energy for precharge power-down per rank (pJ) 28711860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 438971983965 # Energy for self refresh per rank (pJ) 28811860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 461349368400 # Total energy per rank (pJ) 28911860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 247.370445 # Core power per rank (mW) 29011860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 1855266278000 # Total Idle time Per DRAM Rank 29111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 380549250 # Time in different power states 29211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1544966000 # Time in different power states 29311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 1826613361750 # Time in different power states 29411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 11114845500 # Time in different power states 29511860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 7783583250 # Time in different power states 29611860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 17576798750 # Time in different power states 29711860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 222061140 # Energy for activate commands per rank (pJ) 29811860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 118024500 # Energy for precharge commands per rank (pJ) 29911860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1441708800 # Energy for read commands per rank (pJ) 30011860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 308136600 # Energy for write commands per rank (pJ) 30111860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3631907760.000001 # Energy for refresh commands per rank (pJ) 30211860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 4166934840 # Energy for active background per rank (pJ) 30311860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 235115520 # Energy for precharge background per rank (pJ) 30411860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 8062896810 # Energy for active power-down per rank (pJ) 30511860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 4253243040 # Energy for precharge power-down per rank (pJ) 30611860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 438933503490 # Energy for self refresh per rank (pJ) 30711860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 461375149740 # Total energy per rank (pJ) 30811860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 247.384267 # Core power per rank (mW) 30911860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 1855254817500 # Total Idle time Per DRAM Rank 31011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 370314000 # Time in different power states 31111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1542730000 # Time in different power states 31211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 1826502260750 # Time in different power states 31311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 11076094000 # Time in different power states 31411860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 7841044250 # Time in different power states 31511860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 17681661500 # Time in different power states 31611860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 31711860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 31811860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 19565204 # Number of BP lookups 31911860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 16626727 # Number of conditional branches predicted 32011860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 606351 # Number of conditional branches incorrect 32111860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 12911299 # Number of BTB lookups 32211860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5422453 # Number of BTB hits 3239481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 32411860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 41.997734 # BTB Hit Percentage 32511860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 1125914 # Number of times the RAS was used to get a target. 32611860Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 42947 # Number of incorrect RAS predictions. 32711860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 6343232 # Number of indirect predictor lookups. 32811860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 564019 # Number of indirect target hits. 32911860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 5779213 # Number of indirect misses. 33011860Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 264491 # Number of mispredicted indirect branches. 33110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3328464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3338464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3348464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3358464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 33611860Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 11109232 # DTB read hits 33711860Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 50748 # DTB read misses 33811860Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 615 # DTB read access violations 33911860Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 993788 # DTB read accesses 34011860Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6757496 # DTB write hits 34111860Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 12693 # DTB write misses 34211860Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 420 # DTB write access violations 34311860Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 345501 # DTB write accesses 34411860Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 17866728 # DTB hits 34511860Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 63441 # DTB misses 34611860Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 1035 # DTB access violations 34711860Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1339289 # DTB accesses 34811860Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1817930 # ITB hits 34911860Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 10423 # ITB misses 35011860Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 754 # ITB acv 35111860Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1828353 # ITB accesses 3528464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3538464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3548464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3558464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3568464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3578464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3588464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3598464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3608464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3618464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3628464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3638464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 36411860Sandreas.hansson@arm.comsystem.cpu.numPwrStateTransitions 12882 # Number of power state transitions 36511860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::samples 6441 # Distribution of time spent in the clock gated state 36611860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::mean 279499621.875485 # Distribution of time spent in the clock gated state 36711860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::stdev 438940062.434372 # Distribution of time spent in the clock gated state 36811860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 6441 100.00% 100.00% # Distribution of time spent in the clock gated state 36911860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::min_value 80500 # Distribution of time spent in the clock gated state 37011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 37111860Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::total 6441 # Distribution of time spent in the clock gated state 37211860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 64757040000 # Cumulative time (in ticks) in various power states 37311860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 1800257064500 # Cumulative time (in ticks) in various power states 37411860Sandreas.hansson@arm.comsystem.cpu.numCycles 129520522 # number of cpu cycles simulated 3758464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3768464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37711860Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 30117726 # Number of cycles fetch is stalled on an Icache miss 37811860Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 85842784 # Number of instructions fetch has processed 37911860Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 19565204 # Number of branches that fetch encountered 38011860Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 7112386 # Number of branches that fetch has predicted taken 38111860Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 91831627 # Number of cycles fetch has run and was not squashing or blocked 38211860Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1707334 # Number of cycles fetch has spent squashing 38311860Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 94 # Number of cycles fetch has spent waiting for tlb 38411860Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 30324 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 38511860Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 206515 # Number of stall cycles due to pending traps 38611860Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 432806 # Number of stall cycles due to pending quiesce instructions 38711860Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR 38811860Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 9953050 # Number of cache lines fetched 38911860Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 416768 # Number of outstanding Icache misses that were squashed 39011860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 123473258 # Number of instructions fetched each cycle (Total) 39111860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.695234 # Number of instructions fetched each cycle (Total) 39211860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.025215 # Number of instructions fetched each cycle (Total) 3938464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 39411860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 107617936 87.16% 87.16% # Number of instructions fetched each cycle (Total) 39511860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 1029887 0.83% 87.99% # Number of instructions fetched each cycle (Total) 39611860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 2106014 1.71% 89.70% # Number of instructions fetched each cycle (Total) 39711860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 969195 0.78% 90.48% # Number of instructions fetched each cycle (Total) 39811860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2907839 2.36% 92.84% # Number of instructions fetched each cycle (Total) 39911860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 668408 0.54% 93.38% # Number of instructions fetched each cycle (Total) 40011860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 818971 0.66% 94.04% # Number of instructions fetched each cycle (Total) 40111860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1034002 0.84% 94.88% # Number of instructions fetched each cycle (Total) 40211860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 6321006 5.12% 100.00% # Number of instructions fetched each cycle (Total) 4038464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4048464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 4058464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 40611860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 123473258 # Number of instructions fetched each cycle (Total) 40711860Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.151059 # Number of branch fetches per cycle 40811860Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.662774 # Number of inst fetches per cycle 40911860Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 24152038 # Number of cycles decode is idle 41011860Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 86201336 # Number of cycles decode is blocked 41111860Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 10258063 # Number of cycles decode is running 41211860Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 2042752 # Number of cycles decode is unblocking 41311860Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 819068 # Number of cycles decode is squashing 41411860Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 5235547 # Number of times decode resolved a branch 41511860Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 36008 # Number of times decode detected a branch misprediction 41611860Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 74118733 # Number of instructions handled by decode 41711860Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 112337 # Number of squashed instructions handled by decode 41811860Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 819068 # Number of cycles rename is squashing 41911860Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 25161583 # Number of cycles rename is idle 42011860Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 56623083 # Number of cycles rename is blocking 42111860Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 20020475 # count of cycles rename stalled for serializing inst 42211860Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11228852 # Number of cycles rename is running 42311860Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 9620195 # Number of cycles rename is unblocking 42411860Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 71027053 # Number of instructions processed by rename 42511860Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 203339 # Number of times rename has blocked due to ROB full 42611860Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2122213 # Number of times rename has blocked due to IQ full 42711860Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 263594 # Number of times rename has blocked due to LQ full 42811860Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 5326402 # Number of times rename has blocked due to SQ full 42911860Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 47839712 # Number of destination operands rename has renamed 43011860Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 85552570 # Number of register rename lookups that rename has made 43111860Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 85371726 # Number of integer rename lookups 43211860Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 168391 # Number of floating rename lookups 43311860Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38166163 # Number of HB maps that are committed 43411860Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 9673541 # Number of HB maps that are undone due to squashing 43511860Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1731851 # count of serializing insts renamed 43611860Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 279206 # count of temporary serializing insts renamed 43711860Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 13863805 # count of insts added to the skid buffer 43811860Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 11669742 # Number of loads inserted to the mem dependence unit. 43911860Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 7218714 # Number of stores inserted to the mem dependence unit. 44011860Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1729922 # Number of conflicting loads. 44111860Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1107908 # Number of conflicting stores. 44211860Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 62661067 # Number of instructions added to the IQ (excludes non-spec) 44311860Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2212545 # Number of non-speculative instructions added to the IQ 44411860Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 60426230 # Number of instructions issued 44511860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 90696 # Number of squashed instructions issued 44611860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 11910337 # Number of squashed instructions iterated over during squash; mainly for profiling 44711860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 5399466 # Number of squashed operands that are examined and possibly removed from graph 44811860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1551308 # Number of squashed non-spec instructions that were removed 44911860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 123473258 # Number of insts issued each cycle 45011860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.489387 # Number of insts issued each cycle 45111860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.234720 # Number of insts issued each cycle 4528464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 45311860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 98959132 80.15% 80.15% # Number of insts issued each cycle 45411860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10414953 8.43% 88.58% # Number of insts issued each cycle 45511860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 4418122 3.58% 92.16% # Number of insts issued each cycle 45611860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3174360 2.57% 94.73% # Number of insts issued each cycle 45711860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 3248671 2.63% 97.36% # Number of insts issued each cycle 45811860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1596633 1.29% 98.65% # Number of insts issued each cycle 45911860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 1092968 0.89% 99.54% # Number of insts issued each cycle 46011860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 431056 0.35% 99.89% # Number of insts issued each cycle 46111860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 137363 0.11% 100.00% # Number of insts issued each cycle 4628464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4638464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4648464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 46511860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 123473258 # Number of insts issued each cycle 4668464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 46711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 204093 16.54% 16.54% # attempts to use FU when none available 46811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 16.54% # attempts to use FU when none available 46911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 16.54% # attempts to use FU when none available 47011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 16.54% # attempts to use FU when none available 47111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 16.54% # attempts to use FU when none available 47211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 16.54% # attempts to use FU when none available 47311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 16.54% # attempts to use FU when none available 47411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available 47511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 16.54% # attempts to use FU when none available 47611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMisc 0 0.00% 16.54% # attempts to use FU when none available 47711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.54% # attempts to use FU when none available 47811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 16.54% # attempts to use FU when none available 47911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.54% # attempts to use FU when none available 48011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 16.54% # attempts to use FU when none available 48111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 16.54% # attempts to use FU when none available 48211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 16.54% # attempts to use FU when none available 48311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 16.54% # attempts to use FU when none available 48411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 16.54% # attempts to use FU when none available 48511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.54% # attempts to use FU when none available 48611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 16.54% # attempts to use FU when none available 48711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.54% # attempts to use FU when none available 48811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.54% # attempts to use FU when none available 48911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.54% # attempts to use FU when none available 49011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.54% # attempts to use FU when none available 49111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.54% # attempts to use FU when none available 49211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.54% # attempts to use FU when none available 49311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.54% # attempts to use FU when none available 49411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.54% # attempts to use FU when none available 49511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.54% # attempts to use FU when none available 49611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available 49711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.54% # attempts to use FU when none available 49811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 604376 48.98% 65.52% # attempts to use FU when none available 49911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 366984 29.74% 95.26% # attempts to use FU when none available 50011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemRead 31970 2.59% 97.85% # attempts to use FU when none available 50111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemWrite 26536 2.15% 100.00% # attempts to use FU when none available 5028464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5038464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 50411754Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued 50511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 40835249 67.58% 67.59% # Type of FU issued 50611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 62139 0.10% 67.69% # Type of FU issued 50711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued 50811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 38557 0.06% 67.76% # Type of FU issued 50911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 51011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 51111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 51211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued 51311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.76% # Type of FU issued 51411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.76% # Type of FU issued 51511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 51611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 51711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 51811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 51911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 52011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 52111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 52211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 52311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 52411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 52511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 52611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 52711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 52811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 52911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 53011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 53111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 53211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued 53311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 53411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 53511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 53611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 11506324 19.04% 86.81% # Type of FU issued 53711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6726484 11.13% 97.94% # Type of FU issued 53811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemRead 156184 0.26% 98.20% # Type of FU issued 53911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemWrite 141292 0.23% 98.43% # Type of FU issued 54011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949086 1.57% 100.00% # Type of FU issued 5418464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 54211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 60426230 # Type of FU issued 54311860Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.466538 # Inst issue rate 54411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 1233959 # FU busy when requested 54511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.020421 # FU busy rate (busy events/executed inst) 54611860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 244910582 # Number of integer instruction queue reads 54711860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 76445733 # Number of integer instruction queue writes 54811860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 58177679 # Number of integer instruction queue wakeup accesses 54911860Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 739790 # Number of floating instruction queue reads 55011860Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 359586 # Number of floating instruction queue writes 55111860Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 336759 # Number of floating instruction queue wakeup accesses 55211860Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 61254735 # Number of integer alu accesses 55311860Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 398175 # Number of floating point alu accesses 55411860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 690768 # Number of loads that had data forwarded from stores 5558464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55611860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 2579745 # Number of loads squashed 55711860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 4605 # Number of memory responses ignored because the instruction is squashed 55811860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 21941 # Number of memory ordering violations 55911860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 842112 # Number of stores squashed 5608464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5618464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 56211860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 18009 # Number of loads that were rescheduled 56311860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 459546 # Number of times an access to memory failed due to the cache being blocked 5648464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56511860Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 819068 # Number of cycles IEW is squashing 56611860Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 52732826 # Number of cycles IEW is blocking 56711860Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 1310921 # Number of cycles IEW is unblocking 56811860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 68860028 # Number of instructions dispatched to IQ 56911860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 210874 # Number of squashed instructions skipped by dispatch 57011860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 11669742 # Number of dispatched load instructions 57111860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 7218714 # Number of dispatched store instructions 57211860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1962223 # Number of dispatched non-speculative instructions 57311860Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 46667 # Number of times the IQ has become full, causing a stall 57411860Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 1061185 # Number of times the LSQ has become full, causing a stall 57511860Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 21941 # Number of memory order violations 57611860Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 239076 # Number of branches that were predicted taken incorrectly 57711860Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 633747 # Number of branches that were predicted not taken incorrectly 57811860Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 872823 # Number of branch mispredicts detected at execute 57911860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 59548676 # Number of executed instructions 58011860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 11192398 # Number of load instructions executed 58111860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 877553 # Number of squashed instructions skipped in execute 5828464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 58311860Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3986416 # number of nop insts executed 58411860Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 17982691 # number of memory reference insts executed 58511860Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 9367788 # Number of branches executed 58611860Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6790293 # Number of stores executed 58711860Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.459762 # Inst execution rate 58811860Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 58762094 # cumulative count of insts sent to commit 58911860Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 58514438 # cumulative count of insts written-back 59011860Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 29700638 # num instructions producing a value 59111860Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 41179298 # num instructions consuming a value 59211860Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.451777 # insts written-back per cycle 59311860Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.721252 # average fanout of values written-back 59411860Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 12514858 # The number of squashed insts skipped by commit 59511860Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 661237 # The number of times commit has been forced to stall to communicate backwards 59611860Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 782772 # The number of times a branch was mispredicted 59711860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 121281996 # Number of insts commited each cycle 59811860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.462997 # Number of insts commited each cycle 59911860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.395862 # Number of insts commited each cycle 6008241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 60111860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 101434078 83.63% 83.63% # Number of insts commited each cycle 60211860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 7974018 6.57% 90.21% # Number of insts commited each cycle 60311860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4186796 3.45% 93.66% # Number of insts commited each cycle 60411860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2256770 1.86% 95.52% # Number of insts commited each cycle 60511860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1754187 1.45% 96.97% # Number of insts commited each cycle 60611860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 639315 0.53% 97.50% # Number of insts commited each cycle 60711860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 479528 0.40% 97.89% # Number of insts commited each cycle 60811860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 513600 0.42% 98.31% # Number of insts commited each cycle 60911860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 2043704 1.69% 100.00% # Number of insts commited each cycle 6108241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6118241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6128241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61311860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 121281996 # Number of insts commited each cycle 61411860Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56153243 # Number of instructions committed 61511860Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56153243 # Number of ops (including micro ops) committed 6168464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 61711860Sandreas.hansson@arm.comsystem.cpu.commit.refs 15466599 # Number of memory references committed 61811860Sandreas.hansson@arm.comsystem.cpu.commit.loads 9089997 # Number of loads committed 61911860Sandreas.hansson@arm.comsystem.cpu.commit.membars 226363 # Number of memory barriers committed 62011860Sandreas.hansson@arm.comsystem.cpu.commit.branches 8438860 # Number of branches committed 62110892Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 62211860Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52003390 # Number of committed integer instructions. 62311860Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740372 # Number of function calls committed. 62411860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3197246 5.69% 5.69% # Class of committed instruction 62511860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 36205593 64.48% 70.17% # Class of committed instruction 62611860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 60678 0.11% 70.28% # Class of committed instruction 62710892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 62810892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 62910892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 63010892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 63110892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 63211687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction 63311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 63411687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction 63511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 63611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 63711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 63811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 63911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 64011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 64111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 64211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 64311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 64411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 64511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 64611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 64711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 64811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 64911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 65011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 65111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 65211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 65311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 65411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 65511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 65611860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 9171764 16.33% 86.69% # Class of committed instruction 65711860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 6244492 11.12% 97.81% # Class of committed instruction 65811687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction 65911687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction 66011860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 949086 1.69% 100.00% # Class of committed instruction 66110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 66211860Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 56153243 # Class of committed instruction 66311860Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 2043704 # number cycles where commit BW limit reached 66411860Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 187656858 # The number of ROB reads 66511860Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 139533948 # The number of ROB writes 66611860Sandreas.hansson@arm.comsystem.cpu.timesIdled 550447 # Number of times that the entire CPU went into an idle state and unscheduled itself 66711860Sandreas.hansson@arm.comsystem.cpu.idleCycles 6047264 # Total number of cycles that the CPU has spent unscheduled due to idling 66811860Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3600507688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 66911860Sandreas.hansson@arm.comsystem.cpu.committedInsts 52963270 # Number of Instructions Simulated 67011860Sandreas.hansson@arm.comsystem.cpu.committedOps 52963270 # Number of Ops (including micro ops) Simulated 67111860Sandreas.hansson@arm.comsystem.cpu.cpi 2.445478 # CPI: Cycles Per Instruction 67211860Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.445478 # CPI: Total CPI of All Threads 67311860Sandreas.hansson@arm.comsystem.cpu.ipc 0.408918 # IPC: Instructions Per Cycle 67411860Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.408918 # IPC: Total IPC of All Threads 67511860Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 77682847 # number of integer regfile reads 67611860Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 42491451 # number of integer regfile writes 67711860Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166573 # number of floating regfile reads 67811860Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 175777 # number of floating regfile writes 67911860Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2001872 # number of misc regfile reads 68011860Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 939479 # number of misc regfile writes 68111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 68211860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1405824 # number of replacements 68311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994108 # Cycle average of tags in use 68411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 12609719 # Total number of references to valid blocks. 68511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1406336 # Sample count of references to valid blocks. 68611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.966363 # Average number of references to valid blocks. 68711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. 68811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994108 # Average occupied blocks per requestor 68911680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy 69011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy 69110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 69211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id 69311680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 69411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 69510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 69611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 67057386 # Number of tag accesses 69711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 67057386 # Number of data accesses 69811860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 69911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 8001397 # number of ReadReq hits 70011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 8001397 # number of ReadReq hits 70111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4179263 # number of WriteReq hits 70211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4179263 # number of WriteReq hits 70311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 213150 # number of LoadLockedReq hits 70411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 213150 # number of LoadLockedReq hits 70511860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215702 # number of StoreCondReq hits 70611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215702 # number of StoreCondReq hits 70711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 12180660 # number of demand (read+write) hits 70811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 12180660 # number of demand (read+write) hits 70911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 12180660 # number of overall hits 71011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 12180660 # number of overall hits 71111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1813374 # number of ReadReq misses 71211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1813374 # number of ReadReq misses 71311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1966870 # number of WriteReq misses 71411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1966870 # number of WriteReq misses 71511860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 22944 # number of LoadLockedReq misses 71611860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 22944 # number of LoadLockedReq misses 71711860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 62 # number of StoreCondReq misses 71811860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 62 # number of StoreCondReq misses 71911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3780244 # number of demand (read+write) misses 72011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3780244 # number of demand (read+write) misses 72111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3780244 # number of overall misses 72211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3780244 # number of overall misses 72311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 45111482000 # number of ReadReq miss cycles 72411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 45111482000 # number of ReadReq miss cycles 72511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 92228872060 # number of WriteReq miss cycles 72611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 92228872060 # number of WriteReq miss cycles 72711860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 421566000 # number of LoadLockedReq miss cycles 72811860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 421566000 # number of LoadLockedReq miss cycles 72911860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 865000 # number of StoreCondReq miss cycles 73011860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 865000 # number of StoreCondReq miss cycles 73111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 137340354060 # number of demand (read+write) miss cycles 73211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 137340354060 # number of demand (read+write) miss cycles 73311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 137340354060 # number of overall miss cycles 73411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 137340354060 # number of overall miss cycles 73511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9814771 # number of ReadReq accesses(hits+misses) 73611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9814771 # number of ReadReq accesses(hits+misses) 73711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6146133 # number of WriteReq accesses(hits+misses) 73811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6146133 # number of WriteReq accesses(hits+misses) 73911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 236094 # number of LoadLockedReq accesses(hits+misses) 74011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 236094 # number of LoadLockedReq accesses(hits+misses) 74111860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215764 # number of StoreCondReq accesses(hits+misses) 74211860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215764 # number of StoreCondReq accesses(hits+misses) 74311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15960904 # number of demand (read+write) accesses 74411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15960904 # number of demand (read+write) accesses 74511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15960904 # number of overall (read+write) accesses 74611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15960904 # number of overall (read+write) accesses 74711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184760 # miss rate for ReadReq accesses 74811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.184760 # miss rate for ReadReq accesses 74911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320017 # miss rate for WriteReq accesses 75011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.320017 # miss rate for WriteReq accesses 75111860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.097182 # miss rate for LoadLockedReq accesses 75211860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.097182 # miss rate for LoadLockedReq accesses 75311860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000287 # miss rate for StoreCondReq accesses 75411860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000287 # miss rate for StoreCondReq accesses 75511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.236844 # miss rate for demand accesses 75611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.236844 # miss rate for demand accesses 75711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.236844 # miss rate for overall accesses 75811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.236844 # miss rate for overall accesses 75911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24877.097609 # average ReadReq miss latency 76011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 24877.097609 # average ReadReq miss latency 76111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46891.188569 # average WriteReq miss latency 76211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 46891.188569 # average WriteReq miss latency 76311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18373.692469 # average LoadLockedReq miss latency 76411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18373.692469 # average LoadLockedReq miss latency 76511860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13951.612903 # average StoreCondReq miss latency 76611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13951.612903 # average StoreCondReq miss latency 76711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency 76811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 36331.081819 # average overall miss latency 76911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency 77011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 36331.081819 # average overall miss latency 77111860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 4936405 # number of cycles access was blocked 77211860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 4609 # number of cycles access was blocked 77311860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 132646 # number of cycles access was blocked 77411860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 30 # number of cycles access was blocked 77511860Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 37.214880 # average number of cycles each access was blocked 77611860Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 153.633333 # average number of cycles each access was blocked 77711860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 843338 # number of writebacks 77811860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 843338 # number of writebacks 77911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 712674 # number of ReadReq MSHR hits 78011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 712674 # number of ReadReq MSHR hits 78111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677487 # number of WriteReq MSHR hits 78211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1677487 # number of WriteReq MSHR hits 78311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6576 # number of LoadLockedReq MSHR hits 78411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 6576 # number of LoadLockedReq MSHR hits 78511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2390161 # number of demand (read+write) MSHR hits 78611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2390161 # number of demand (read+write) MSHR hits 78711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2390161 # number of overall MSHR hits 78811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2390161 # number of overall MSHR hits 78911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100700 # number of ReadReq MSHR misses 79011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1100700 # number of ReadReq MSHR misses 79111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 289383 # number of WriteReq MSHR misses 79211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 289383 # number of WriteReq MSHR misses 79311860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16368 # number of LoadLockedReq MSHR misses 79411860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 16368 # number of LoadLockedReq MSHR misses 79511860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 62 # number of StoreCondReq MSHR misses 79611860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 62 # number of StoreCondReq MSHR misses 79711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1390083 # number of demand (read+write) MSHR misses 79811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1390083 # number of demand (read+write) MSHR misses 79911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1390083 # number of overall MSHR misses 80011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1390083 # number of overall MSHR misses 80110827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 80210827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 80311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 80411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 80511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 80611680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses 80711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33019179500 # number of ReadReq MSHR miss cycles 80811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 33019179500 # number of ReadReq MSHR miss cycles 80911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14332081529 # number of WriteReq MSHR miss cycles 81011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 14332081529 # number of WriteReq MSHR miss cycles 81111860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205108500 # number of LoadLockedReq MSHR miss cycles 81211860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205108500 # number of LoadLockedReq MSHR miss cycles 81311860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 803000 # number of StoreCondReq MSHR miss cycles 81411860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 803000 # number of StoreCondReq MSHR miss cycles 81511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 47351261029 # number of demand (read+write) MSHR miss cycles 81611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 47351261029 # number of demand (read+write) MSHR miss cycles 81711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 47351261029 # number of overall MSHR miss cycles 81811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 47351261029 # number of overall MSHR miss cycles 81911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535277500 # number of ReadReq MSHR uncacheable cycles 82011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535277500 # number of ReadReq MSHR uncacheable cycles 82111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535277500 # number of overall MSHR uncacheable cycles 82211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 1535277500 # number of overall MSHR uncacheable cycles 82311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.112147 # mshr miss rate for ReadReq accesses 82411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.112147 # mshr miss rate for ReadReq accesses 82511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047084 # mshr miss rate for WriteReq accesses 82611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047084 # mshr miss rate for WriteReq accesses 82711860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.069328 # mshr miss rate for LoadLockedReq accesses 82811860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.069328 # mshr miss rate for LoadLockedReq accesses 82911860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000287 # mshr miss rate for StoreCondReq accesses 83011860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000287 # mshr miss rate for StoreCondReq accesses 83111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for demand accesses 83211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.087093 # mshr miss rate for demand accesses 83311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for overall accesses 83411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.087093 # mshr miss rate for overall accesses 83511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29998.346053 # average ReadReq mshr miss latency 83611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29998.346053 # average ReadReq mshr miss latency 83711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49526.342353 # average WriteReq mshr miss latency 83811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49526.342353 # average WriteReq mshr miss latency 83911860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12531.066716 # average LoadLockedReq mshr miss latency 84011860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12531.066716 # average LoadLockedReq mshr miss latency 84111860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12951.612903 # average StoreCondReq mshr miss latency 84211860Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12951.612903 # average StoreCondReq mshr miss latency 84311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency 84411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency 84511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency 84611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency 84711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221540.764791 # average ReadReq mshr uncacheable latency 84811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221540.764791 # average ReadReq mshr uncacheable latency 84911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92883.870773 # average overall mshr uncacheable latency 85011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92883.870773 # average overall mshr uncacheable latency 85111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 85211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1070370 # number of replacements 85311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 509.026702 # Cycle average of tags in use 85411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 8813001 # Total number of references to valid blocks. 85511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1070878 # Sample count of references to valid blocks. 85611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 8.229697 # Average number of references to valid blocks. 85711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 30284278500 # Cycle when the warmup percentage was hit. 85811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 509.026702 # Average occupied blocks per requestor 85911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.994193 # Average percentage of cache occupancy 86011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.994193 # Average percentage of cache occupancy 86110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 86211754Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 86311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 86411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id 86510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 86611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 11024191 # Number of tag accesses 86711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 11024191 # Number of data accesses 86811860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 86911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 8813002 # number of ReadReq hits 87011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 8813002 # number of ReadReq hits 87111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 8813002 # number of demand (read+write) hits 87211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 8813002 # number of demand (read+write) hits 87311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 8813002 # number of overall hits 87411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 8813002 # number of overall hits 87511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1140039 # number of ReadReq misses 87611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1140039 # number of ReadReq misses 87711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1140039 # number of demand (read+write) misses 87811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1140039 # number of demand (read+write) misses 87911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1140039 # number of overall misses 88011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1140039 # number of overall misses 88111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16263731493 # number of ReadReq miss cycles 88211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 16263731493 # number of ReadReq miss cycles 88311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16263731493 # number of demand (read+write) miss cycles 88411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 16263731493 # number of demand (read+write) miss cycles 88511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16263731493 # number of overall miss cycles 88611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 16263731493 # number of overall miss cycles 88711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 9953041 # number of ReadReq accesses(hits+misses) 88811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 9953041 # number of ReadReq accesses(hits+misses) 88911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 9953041 # number of demand (read+write) accesses 89011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 9953041 # number of demand (read+write) accesses 89111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 9953041 # number of overall (read+write) accesses 89211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 9953041 # number of overall (read+write) accesses 89311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.114542 # miss rate for ReadReq accesses 89411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.114542 # miss rate for ReadReq accesses 89511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.114542 # miss rate for demand accesses 89611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.114542 # miss rate for demand accesses 89711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.114542 # miss rate for overall accesses 89811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.114542 # miss rate for overall accesses 89911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14265.943089 # average ReadReq miss latency 90011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 14265.943089 # average ReadReq miss latency 90111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 14265.943089 # average overall miss latency 90211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 14265.943089 # average overall miss latency 90311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 14265.943089 # average overall miss latency 90411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 14265.943089 # average overall miss latency 90511860Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 8433 # number of cycles access was blocked 90610585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 90711860Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked 90810585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 90911860Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 28.880137 # average number of cycles each access was blocked 91010585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91111860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 1070370 # number of writebacks 91211860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 1070370 # number of writebacks 91311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 68889 # number of ReadReq MSHR hits 91411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 68889 # number of ReadReq MSHR hits 91511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 68889 # number of demand (read+write) MSHR hits 91611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 68889 # number of demand (read+write) MSHR hits 91711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 68889 # number of overall MSHR hits 91811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 68889 # number of overall MSHR hits 91911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071150 # number of ReadReq MSHR misses 92011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1071150 # number of ReadReq MSHR misses 92111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1071150 # number of demand (read+write) MSHR misses 92211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1071150 # number of demand (read+write) MSHR misses 92311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1071150 # number of overall MSHR misses 92411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1071150 # number of overall MSHR misses 92511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14349436996 # number of ReadReq MSHR miss cycles 92611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14349436996 # number of ReadReq MSHR miss cycles 92711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14349436996 # number of demand (read+write) MSHR miss cycles 92811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 14349436996 # number of demand (read+write) MSHR miss cycles 92911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14349436996 # number of overall MSHR miss cycles 93011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 14349436996 # number of overall MSHR miss cycles 93111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for ReadReq accesses 93211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.107620 # mshr miss rate for ReadReq accesses 93311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for demand accesses 93411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.107620 # mshr miss rate for demand accesses 93511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for overall accesses 93611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.107620 # mshr miss rate for overall accesses 93711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13396.290899 # average ReadReq mshr miss latency 93811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13396.290899 # average ReadReq mshr miss latency 93911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency 94011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency 94111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency 94211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency 94311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 94411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338611 # number of replacements 94511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65420.352754 # Cycle average of tags in use 94611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4547118 # Total number of references to valid blocks. 94711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 404133 # Sample count of references to valid blocks. 94811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 11.251538 # Average number of references to valid blocks. 94911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 6414124000 # Cycle when the warmup percentage was hit. 95011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 256.173828 # Average occupied blocks per requestor 95111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5307.615094 # Average occupied blocks per requestor 95211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 59856.563832 # Average occupied blocks per requestor 95311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.003909 # Average percentage of cache occupancy 95411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.080988 # Average percentage of cache occupancy 95511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.913339 # Average percentage of cache occupancy 95611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy 95711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 95811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 95911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id 96011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id 96111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5606 # Occupied blocks per task id 96211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 58575 # Occupied blocks per task id 96311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 96411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 40018321 # Number of tag accesses 96511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 40018321 # Number of data accesses 96611860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 96711860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 843338 # number of WritebackDirty hits 96811860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 843338 # number of WritebackDirty hits 96911860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1069837 # number of WritebackClean hits 97011860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1069837 # number of WritebackClean hits 97111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 60 # number of UpgradeReq hits 97211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 60 # number of UpgradeReq hits 97311860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 62 # number of SCUpgradeReq hits 97411860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 62 # number of SCUpgradeReq hits 97511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185066 # number of ReadExReq hits 97611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185066 # number of ReadExReq hits 97711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1055887 # number of ReadCleanReq hits 97811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1055887 # number of ReadCleanReq hits 97911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 832119 # number of ReadSharedReq hits 98011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 832119 # number of ReadSharedReq hits 98111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1055887 # number of demand (read+write) hits 98211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1017185 # number of demand (read+write) hits 98311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2073072 # number of demand (read+write) hits 98411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1055887 # number of overall hits 98511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1017185 # number of overall hits 98611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2073072 # number of overall hits 98711860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses 98811860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses 98911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 114704 # number of ReadExReq misses 99011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 114704 # number of ReadExReq misses 99111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15037 # number of ReadCleanReq misses 99211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 15037 # number of ReadCleanReq misses 99311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 274496 # number of ReadSharedReq misses 99411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 274496 # number of ReadSharedReq misses 99511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15037 # number of demand (read+write) misses 99611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389200 # number of demand (read+write) misses 99711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404237 # number of demand (read+write) misses 99811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15037 # number of overall misses 99911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389200 # number of overall misses 100011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404237 # number of overall misses 100111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 448000 # number of UpgradeReq miss cycles 100211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 448000 # number of UpgradeReq miss cycles 100311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12012512000 # number of ReadExReq miss cycles 100411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 12012512000 # number of ReadExReq miss cycles 100511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519237500 # number of ReadCleanReq miss cycles 100611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 1519237500 # number of ReadCleanReq miss cycles 100711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22383517000 # number of ReadSharedReq miss cycles 100811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 22383517000 # number of ReadSharedReq miss cycles 100911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1519237500 # number of demand (read+write) miss cycles 101011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 34396029000 # number of demand (read+write) miss cycles 101111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 35915266500 # number of demand (read+write) miss cycles 101211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1519237500 # number of overall miss cycles 101311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 34396029000 # number of overall miss cycles 101411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 35915266500 # number of overall miss cycles 101511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 843338 # number of WritebackDirty accesses(hits+misses) 101611860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 843338 # number of WritebackDirty accesses(hits+misses) 101711860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1069837 # number of WritebackClean accesses(hits+misses) 101811860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1069837 # number of WritebackClean accesses(hits+misses) 101911860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 70 # number of UpgradeReq accesses(hits+misses) 102011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 70 # number of UpgradeReq accesses(hits+misses) 102111860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 62 # number of SCUpgradeReq accesses(hits+misses) 102211860Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 62 # number of SCUpgradeReq accesses(hits+misses) 102311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 299770 # number of ReadExReq accesses(hits+misses) 102411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 299770 # number of ReadExReq accesses(hits+misses) 102511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1070924 # number of ReadCleanReq accesses(hits+misses) 102611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1070924 # number of ReadCleanReq accesses(hits+misses) 102711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106615 # number of ReadSharedReq accesses(hits+misses) 102811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1106615 # number of ReadSharedReq accesses(hits+misses) 102911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1070924 # number of demand (read+write) accesses 103011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1406385 # number of demand (read+write) accesses 103111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2477309 # number of demand (read+write) accesses 103211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1070924 # number of overall (read+write) accesses 103311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1406385 # number of overall (read+write) accesses 103411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2477309 # number of overall (read+write) accesses 103511860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.142857 # miss rate for UpgradeReq accesses 103611860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.142857 # miss rate for UpgradeReq accesses 103711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382640 # miss rate for ReadExReq accesses 103811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.382640 # miss rate for ReadExReq accesses 103911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014041 # miss rate for ReadCleanReq accesses 104011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014041 # miss rate for ReadCleanReq accesses 104111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248050 # miss rate for ReadSharedReq accesses 104211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248050 # miss rate for ReadSharedReq accesses 104311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014041 # miss rate for demand accesses 104411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.276738 # miss rate for demand accesses 104511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.163176 # miss rate for demand accesses 104611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014041 # miss rate for overall accesses 104711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.276738 # miss rate for overall accesses 104811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.163176 # miss rate for overall accesses 104911860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 44800 # average UpgradeReq miss latency 105011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 44800 # average UpgradeReq miss latency 105111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104726.182173 # average ReadExReq miss latency 105211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 104726.182173 # average ReadExReq miss latency 105311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101033.284565 # average ReadCleanReq miss latency 105411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101033.284565 # average ReadCleanReq miss latency 105511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81544.055287 # average ReadSharedReq miss latency 105611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81544.055287 # average ReadSharedReq miss latency 105711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency 105811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 88376.230730 # average overall miss latency 105911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 88847.053832 # average overall miss latency 106011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency 106111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 88376.230730 # average overall miss latency 106211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 88847.053832 # average overall miss latency 106310585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106410585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 106510585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 106610585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 106710585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 106810585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 106911860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 75899 # number of writebacks 107011860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 75899 # number of writebacks 107111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses 107211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses 107311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114704 # number of ReadExReq MSHR misses 107411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 114704 # number of ReadExReq MSHR misses 107511754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses 107611754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses 107711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274496 # number of ReadSharedReq MSHR misses 107811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 274496 # number of ReadSharedReq MSHR misses 107911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15037 # number of demand (read+write) MSHR misses 108011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389200 # number of demand (read+write) MSHR misses 108111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404237 # number of demand (read+write) MSHR misses 108211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15037 # number of overall MSHR misses 108311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389200 # number of overall MSHR misses 108411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404237 # number of overall MSHR misses 108510827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 108610827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 108711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 108811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 108911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 109011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses 109111860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 348000 # number of UpgradeReq MSHR miss cycles 109211860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 348000 # number of UpgradeReq MSHR miss cycles 109311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10865472000 # number of ReadExReq MSHR miss cycles 109411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10865472000 # number of ReadExReq MSHR miss cycles 109511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1368867500 # number of ReadCleanReq MSHR miss cycles 109611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1368867500 # number of ReadCleanReq MSHR miss cycles 109711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19644703500 # number of ReadSharedReq MSHR miss cycles 109811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19644703500 # number of ReadSharedReq MSHR miss cycles 109911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1368867500 # number of demand (read+write) MSHR miss cycles 110011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30510175500 # number of demand (read+write) MSHR miss cycles 110111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 31879043000 # number of demand (read+write) MSHR miss cycles 110211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1368867500 # number of overall MSHR miss cycles 110311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30510175500 # number of overall MSHR miss cycles 110411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 31879043000 # number of overall MSHR miss cycles 110511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448637000 # number of ReadReq MSHR uncacheable cycles 110611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448637000 # number of ReadReq MSHR uncacheable cycles 110711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448637000 # number of overall MSHR uncacheable cycles 110811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448637000 # number of overall MSHR uncacheable cycles 110911860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for UpgradeReq accesses 111011860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.142857 # mshr miss rate for UpgradeReq accesses 111111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382640 # mshr miss rate for ReadExReq accesses 111211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382640 # mshr miss rate for ReadExReq accesses 111311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for ReadCleanReq accesses 111411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014041 # mshr miss rate for ReadCleanReq accesses 111511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248050 # mshr miss rate for ReadSharedReq accesses 111611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248050 # mshr miss rate for ReadSharedReq accesses 111711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for demand accesses 111811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for demand accesses 111911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.163176 # mshr miss rate for demand accesses 112011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for overall accesses 112111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for overall accesses 112211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.163176 # mshr miss rate for overall accesses 112311860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 34800 # average UpgradeReq mshr miss latency 112411860Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34800 # average UpgradeReq mshr miss latency 112511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94726.182173 # average ReadExReq mshr miss latency 112611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94726.182173 # average ReadExReq mshr miss latency 112711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91033.284565 # average ReadCleanReq mshr miss latency 112811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91033.284565 # average ReadCleanReq mshr miss latency 112911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71566.447234 # average ReadSharedReq mshr miss latency 113011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71566.447234 # average ReadSharedReq mshr miss latency 113111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency 113211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency 113311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency 113411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency 113511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency 113611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency 113711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209038.528139 # average ReadReq mshr uncacheable latency 113811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209038.528139 # average ReadReq mshr uncacheable latency 113911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87642.144110 # average overall mshr uncacheable latency 114011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87642.144110 # average overall mshr uncacheable latency 114111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4953861 # Total number of requests made to the snoop filter. 114211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2476312 # Number of requests hitting in the snoop filter with a single holder of the requested data. 114311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4344 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 114411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 953 # Total number of snoops made to the snoop filter. 114511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 114611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 114711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 114810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 114911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2184804 # Transaction distribution 115011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution 115111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution 115211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 919237 # Transaction distribution 115311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1070370 # Transaction distribution 115411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 825198 # Transaction distribution 115511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 70 # Transaction distribution 115611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 62 # Transaction distribution 115711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution 115811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 299770 # Transaction distribution 115911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 299770 # Transaction distribution 116011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1071150 # Transaction distribution 116111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1106776 # Transaction distribution 116211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution 116311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution 116411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution 116511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3212444 # Packet count per connected master and slave (bytes) 116611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252074 # Packet count per connected master and slave (bytes) 116711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 7464518 # Packet count per connected master and slave (bytes) 116811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137042816 # Cumulative packet size per connected master and slave (bytes) 116911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144033404 # Cumulative packet size per connected master and slave (bytes) 117011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 281076220 # Cumulative packet size per connected master and slave (bytes) 117111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 339392 # Total snoops (count) 117211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 4881984 # Total snoop traffic (bytes) 117311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2833204 # Request fanout histogram 117411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001872 # Request fanout histogram 117511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.043223 # Request fanout histogram 117610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 117711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2827901 99.81% 99.81% # Request fanout histogram 117811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 5303 0.19% 100.00% # Request fanout histogram 117911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 118010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 118111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 118211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 118311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2833204 # Request fanout histogram 118411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4403702500 # Layer occupancy (ticks) 118510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 118611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) 118710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 118811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1607637172 # Layer occupancy (ticks) 118910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 119011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2121526099 # Layer occupancy (ticks) 119110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 119210585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 119310585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 119410585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 119510585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 119610585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 119710585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 119810585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 119910585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 120010585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 120110585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 120210585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 120310585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 120411860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 12059729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 12069729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 120711680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 51151 # Transaction distribution 120811680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 51151 # Transaction distribution 120911680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) 121011245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 12119729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 12129729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 12139729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 12149729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 12159729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 12169729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 12179729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 121811680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) 12199729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 12209729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 122111680SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) 122211680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) 122311245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 122410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 122510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 122610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 122710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 122810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 122910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 123010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 123111680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) 123210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 123310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 123411680SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) 123511860Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) 12369729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 123711860Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 815500 # Layer occupancy (ticks) 12389729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 123911860Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 12409729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 124111860Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 12429729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 124311860Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) 12449729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 124511860Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 14072500 # Layer occupancy (ticks) 12469729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 124711860Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2178500 # Layer occupancy (ticks) 12489729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 124911860Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 6063000 # Layer occupancy (ticks) 12509729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 125111860Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 93500 # Layer occupancy (ticks) 12529729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 125311860Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 216225034 # Layer occupancy (ticks) 12549729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 125511680SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) 12569729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 125710892Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 12589729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 125911860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 126010585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 126111860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.265440 # Cycle average of tags in use 126210585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 126310585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 126410585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 126511860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1714255689000 # Cycle when the warmup percentage was hit. 126611860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.265440 # Average occupied blocks per requestor 126711860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.079090 # Average percentage of cache occupancy 126811860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.079090 # Average percentage of cache occupancy 126910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 127010585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 127110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 127210585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 127310585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 127411860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 127510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 127610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 127710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 127810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 127911456Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 128011456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 128111456Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 128211456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 41725 # number of overall misses 128311860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21944883 # number of ReadReq miss cycles 128411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21944883 # number of ReadReq miss cycles 128511860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 4931807151 # number of WriteLineReq miss cycles 128611860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 4931807151 # number of WriteLineReq miss cycles 128711860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 4953752034 # number of demand (read+write) miss cycles 128811860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 4953752034 # number of demand (read+write) miss cycles 128911860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 4953752034 # number of overall miss cycles 129011860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 4953752034 # number of overall miss cycles 129110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 129210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 129310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 129410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 129511456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 129611456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 129711456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 129811456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 129910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 130010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 130110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 130210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 130310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 130410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 130510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 130610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 130711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 126849.034682 # average ReadReq miss latency 130811860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 126849.034682 # average ReadReq miss latency 130911860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118690.006522 # average WriteLineReq miss latency 131011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 118690.006522 # average WriteLineReq miss latency 131111860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency 131211860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 118723.835446 # average overall miss latency 131311860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency 131411860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 118723.835446 # average overall miss latency 131511860Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 1219 # number of cycles access was blocked 131610585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 131711860Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 12 # number of cycles access was blocked 131810585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 131911860Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 101.583333 # average number of cycles each access was blocked 132010585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 132110585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 132210585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 132310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 132410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 132510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 132610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 132711456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 132811456Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 132911456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 133011456Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 133111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294883 # number of ReadReq MSHR miss cycles 133211860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13294883 # number of ReadReq MSHR miss cycles 133311860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851781783 # number of WriteLineReq MSHR miss cycles 133411860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 2851781783 # number of WriteLineReq MSHR miss cycles 133511860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 2865076666 # number of demand (read+write) MSHR miss cycles 133611860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 2865076666 # number of demand (read+write) MSHR miss cycles 133711860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 2865076666 # number of overall MSHR miss cycles 133811860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 2865076666 # number of overall MSHR miss cycles 133910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 134010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 134110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 134210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 134310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 134410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 134510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 134610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 134711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76849.034682 # average ReadReq mshr miss latency 134811860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 76849.034682 # average ReadReq mshr miss latency 134911860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68631.637057 # average WriteLineReq mshr miss latency 135011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68631.637057 # average WriteLineReq mshr miss latency 135111860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency 135211860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency 135311860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency 135411860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency 135511860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 825536 # Total number of requests made to the snoop filter. 135611860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 380380 # Number of requests hitting in the snoop filter with a single holder of the requested data. 135711860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 527 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 135811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 135911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 136011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 136111860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 136210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6930 # Transaction distribution 136311860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 296589 # Transaction distribution 136411680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 9599 # Transaction distribution 136511680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 9599 # Transaction distribution 136611860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 117411 # Transaction distribution 136711860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 262092 # Transaction distribution 136811680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 137 # Transaction distribution 136911336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 137011860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 114577 # Transaction distribution 137111860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 114577 # Transaction distribution 137211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 289706 # Transaction distribution 137311754Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 47 # Transaction distribution 137410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 137511754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 124 # Transaction distribution 137611680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) 137711860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145804 # Packet count per connected master and slave (bytes) 137811754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) 137911860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178956 # Packet count per connected master and slave (bytes) 138011336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 138111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 138211860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1262381 # Packet count per connected master and slave (bytes) 138311680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) 138411860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699840 # Cumulative packet size per connected master and slave (bytes) 138511860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 30743996 # Cumulative packet size per connected master and slave (bytes) 138610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 138710892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 138811860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 33401724 # Cumulative packet size per connected master and slave (bytes) 138911860Sandreas.hansson@arm.comsystem.membus.snoops 562 # Total snoops (count) 139011860Sandreas.hansson@arm.comsystem.membus.snoopTraffic 27840 # Total snoop traffic (bytes) 139111860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 462501 # Request fanout histogram 139211860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.001464 # Request fanout histogram 139311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.038231 # Request fanout histogram 139410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 139511860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 461824 99.85% 99.85% # Request fanout histogram 139611860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram 139710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 139810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 139911606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 140010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 140111860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 462501 # Request fanout histogram 140211860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 28785000 # Layer occupancy (ticks) 140310585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 140411860Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1313532070 # Layer occupancy (ticks) 140510585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 140611860Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) 140710585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 140811860Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2137876500 # Layer occupancy (ticks) 140910726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 141011860Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 1057021 # Layer occupancy (ticks) 141110585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 141211860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 141311860Sandreas.hansson@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 141411860Sandreas.hansson@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 141511860Sandreas.hansson@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 141611860Sandreas.hansson@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 141710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 141810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 141910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 142010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 142110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 142210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 142310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 142410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 142510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 142610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 142710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 142810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 142910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 143010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 143110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 143210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 143310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 143410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 143510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 143610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 143710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 143810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 143910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 144010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 144110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 144210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 144310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 144410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 144510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 144610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 144710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 144811860Sandreas.hansson@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 144911860Sandreas.hansson@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145011860Sandreas.hansson@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145111860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145211860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145311860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145411860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145511860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145611860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145711860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145811860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 145911860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146011860Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146111860Sandreas.hansson@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146211860Sandreas.hansson@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146311860Sandreas.hansson@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146411860Sandreas.hansson@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146511860Sandreas.hansson@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146611860Sandreas.hansson@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146711860Sandreas.hansson@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146811860Sandreas.hansson@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 146911860Sandreas.hansson@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 147011860Sandreas.hansson@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states 14715703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 147211860Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed 147311860Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed 147411860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl 14759285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 147611680SCurtis.Dunham@arm.comsystem.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl 147711860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl 147811860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182250 # number of times we switched to this ipl 147911860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl 14809285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 148111680SCurtis.Dunham@arm.comsystem.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl 148211860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl 148311860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl 148411860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1819143935000 97.54% 97.54% # number of cycles we spent at this ipl 148511860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 67422000 0.00% 97.54% # number of cycles we spent at this ipl 148611860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 565966500 0.03% 97.57% # number of cycles we spent at this ipl 148711860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 45235960500 2.43% 100.00% # number of cycles we spent at this ipl 148811860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1865013284000 # number of cycles we spent at this ipl 148911860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl 14906127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 14916127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 149211860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694287 # fraction of swpipl calls that actually changed the ipl 149311860Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815407 # fraction of swpipl calls that actually changed the ipl 14948464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 14958464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 14968464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 14978464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 149810892Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 14999285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 15009199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 150111860Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175131 91.22% 93.43% # number of callpals executed 150211680SCurtis.Dunham@arm.comsystem.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed 15039285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 15049199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 15059285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 15069285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 150711680SCurtis.Dunham@arm.comsystem.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed 15088464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 15098464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 151011860Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191978 # number of callpals executed 151111754Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 151211680SCurtis.Dunham@arm.comsystem.cpu.kern.mode_switch::user 1738 # number of protection mode switches 151311754Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 151411680SCurtis.Dunham@arm.comsystem.cpu.kern.mode_good::kernel 1908 151511680SCurtis.Dunham@arm.comsystem.cpu.kern.mode_good::user 1738 15168517SN/Asystem.cpu.kern.mode_good::idle 170 151711754Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326098 # fraction of useful protection mode switches 15188464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 151911754Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 152011680SCurtis.Dunham@arm.comsystem.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches 152111860Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29665976500 1.59% 1.59% # number of ticks spent at the given mode 152211860Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2757716000 0.15% 1.74% # number of ticks spent at the given mode 152311860Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1832589583500 98.26% 100.00% # number of ticks spent at the given mode 152410892Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 15255703SN/A 15265703SN/A---------- End Simulation Statistics ---------- 1527