Searched hist:56 (Results 301 - 325 of 501) sorted by relevance

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/gem5/src/gpu-compute/
H A Dgpu_tlb.cc12717:2e2c211644d2 Fri Apr 27 14:56:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry

GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It
wrapped the class and included an extra member "valid". This member was
intended to report on the validity of the entry, however it introduced
bugs when folks forgot to set field properly in the code. So, instead of
keeping the extra field which we might forget to set, we track validity by
using nullptr for invalid tlb entries (as the tlb entries are dynamically
allocated). This saves on the extra class definition and prevents bugs
creeping into the code since the checks are intrinsically tied into
accessing any of the X86ISA::TlbEntry members.

This changeset fixes the issues introduced by a8d030522, a4e722725, and
2a15bfd79.

Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2
Reviewed-on: https://gem5-review.googlesource.com/10481
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
H A Dcompute_unit.cc12717:2e2c211644d2 Fri Apr 27 14:56:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry

GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It
wrapped the class and included an extra member "valid". This member was
intended to report on the validity of the entry, however it introduced
bugs when folks forgot to set field properly in the code. So, instead of
keeping the extra field which we might forget to set, we track validity by
using nullptr for invalid tlb entries (as the tlb entries are dynamically
allocated). This saves on the extra class definition and prevents bugs
creeping into the code since the checks are intrinsically tied into
accessing any of the X86ISA::TlbEntry members.

This changeset fixes the issues introduced by a8d030522, a4e722725, and
2a15bfd79.

Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2
Reviewed-on: https://gem5-review.googlesource.com/10481
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
/gem5/src/arch/alpha/linux/
H A Dsystem.hh9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
/gem5/src/arch/arm/isa/insts/
H A Dneon.isa9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
H A Ddata64.isa10205:3ca67d0e0e7e Thu Apr 17 17:56:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm: Make sure UndefinedInstructions are properly initialized
/gem5/src/cpu/pred/
H A Dtournament.cc8463:7a48916a32a8 Sun Jul 10 01:56:00 EDT 2011 Mrinmoy Ghosh <Mrinmoy.Ghosh@arm.com> Branch predictor: Fixes the tournament branch predictor.

Branch predictor could not predict a branch in a nested loop because:
1. The global history was not updated after a mispredict squash.
2. The global history was updated in the fetch stage. The choice predictors
that were updated used the changed global history. This is incorrect, as
it incorporates the state of global history after the branch in
encountered. Fixed update to choice predictor using the global history
state before the branch happened.
3. The global predictor table was also updated using the global history state
before the branch happened as above.

Additionally, parameters to initialize ctr and history size were reversed.
/gem5/src/mem/cache/prefetch/
H A DSConscript13700:56fa28e6fab4 Thu Jan 31 10:24:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Slim AMPM Prefetcher

Reference:
Towards Bandwidth-Efficient Prefetching with Slim AMPM.
Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.

Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).

Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/
H A Ddram_ctrl.cc12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
10247:0ad233f0a77d Mon Jun 30 13:56:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: DRAMPower trace output

This patch adds a DRAMPower flag to enable off-line DRAM power
analysis using the DRAMPower tool. A new DRAMPower flag is added
and a follow-on patch adds a Python script to post-process the output
and order it based on time stamps.

The long-term goal is to link DRAMPower as a library and provide the
commands through function calls to the model rather than first
printing and then parsing the commands. At the moment it is also up to
the user to ensure that the same DRAM configuration is used by the
gem5 controller model and DRAMPower.
10246:e0e3efe3b1d5 Mon Jun 30 13:56:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add bank and rank indices as fields to the DRAM bank

This patch adds the index of the bank and rank as a field so that we can
determine the identity of a given bank (reference or pointer) for the
power tracing. We also grab the opportunity of cleaning up the
arguments used for identifying the bank when activating.
10245:70333502b9b5 Mon Jun 30 13:56:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Extend DRAM row bits from 16 to 32 for larger densities

This patch extends the DRAM row bits to 32 to support larger density
memories. Additional checks are also added to ensure the row fits in
the 32 bits.
H A Ddramsim2.cc12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dnoncoherent_xbar.cc12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dqport.hh12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dsimple_mem.hh9120:48eeef8a0997 Thu Jul 12 00:56:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Mem: Make SimpleMemory single ported

This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
H A Dfs_translating_port_proxy.cc8861:56d011130987 Wed Feb 29 04:47:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Make all the port proxy members const

This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.
H A Dxbar.cc12776:410b60d8a397 Wed Apr 18 06:56:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> base, mem: Disambiguate if an addr range is contained or overlaps

We need to determined whether an address range is fully contained or
it overlaps with an address range in the address range in the mmap. As
an example, we use address range maps to associate ports to address
ranges and we determine which port we will forward the request based
on which address range contains the addresses accessed by the
request. We also need to make sure that when we add a new port to the
address range map, its address range does not overlap with any of the
existing ports.

This patch splits the function find() into two functions contains()
and intersects() to implement this distinct functionality. It also
changes the xbar and the physical memory to use the right function.

Change-Id: If3fd3f774a16b27db2df76dc04f1d61824938008
Reviewed-on: https://gem5-review.googlesource.com/11115
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dcomm_monitor.hh9542:683991c46ac8 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add predecessor to SenderState base class

This patch adds a predecessor field to the SenderState base class to
make the process of linking them up more uniform, and enable a
traversal of the stack without knowing the specific type of the
subclasses.

There are a number of simplifications done as part of changing the
SenderState, particularly in the RubyTest.
/gem5/src/cpu/minor/
H A Dcpu.hh13966:3189413c5894 Fri Mar 01 08:56:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> Revert "cpu: fix how a thread starts up in MinorCPU"

This reverts commit 02dafc5498750d9734ba8f2a1608a846f90b71d1.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I0a8098fc71abe5838014e587dbe372b258d8aa9f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18604
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/mem/ruby/system/
H A DDMASequencer.hh9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
/gem5/src/dev/
H A DDevice.py8461:7d0669201f80 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> IO: Handle case where ISA Fake device is being used as a fake memory.
/gem5/src/arch/x86/isa/decoder/
H A Done_byte_opcodes.isa9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
4592:520664dfb26f Tue Jun 19 13:56:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make instructions that are illegal in 64 bit mode not do the wrong thing in 64 bit mode. Also add in more versions of PUSH and POP, and a version of near CALL.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/
H A Dstats.txt11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes

This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/
H A Dstats.txt11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes

This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
/gem5/src/mem/cache/tags/
H A Dbase.cc12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
11486:f09bb73b3050 Thu May 26 06:56:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: fix headers include order in the cache related classes

Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/sim/
H A DSystem.py10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation.
/gem5/src/arch/arm/
H A Dfaults.hh12176:4282f755a69a Fri Jun 23 08:56:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> arch-arm: Add missing override keywords in fault.hh

Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4284
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
10205:3ca67d0e0e7e Thu Apr 17 17:56:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm: Make sure UndefinedInstructions are properly initialized
/gem5/src/cpu/
H A Dthread_state.cc5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
3280:91bfa4f79c53 Mon Oct 16 15:56:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Fix up microcode support.

src/arch/sparc/isa/formats/blockmem.isa:
Several small and medium bug fixes.
src/cpu/simple/base.cc:
Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
Made sure the microPC and nextMicroPC are initialized properly.

Completed in 214 milliseconds

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