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/gem5/src/arch/arm/insts/
H A Dmacromem.cc10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
/gem5/src/arch/arm/isa/formats/
H A Dmem.isa6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/x86/
H A Disa.cc12692:1eaaa1d75080 Fri May 04 01:53:00 EDT 2018 Matt Sinclair <mattdsinclair@gmail.com> arch-x86, arch-power: fix calls to bits and insertBits

The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit. This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.

Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Reviewed-on: https://gem5-review.googlesource.com/10241
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dtypes.hh10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly.

Instead of counting the number of opcode bytes in an instruction and recording
each byte before the actual opcode, we can represent the path we took to get to
the actual opcode byte by using a type code. That has a couple of advantages.
First, we can disambiguate the properties of opcodes of the same length which
have different properties. Second, it reduces the amount of data stored in an
ExtMachInst, making them slightly easier/faster to create and process. This
also adds some flexibility as far as how different types of opcodes are
handled, which might come in handy if we decide to support VEX or XOP
instructions.

This change also adds tables to support properly decoding 3 byte opcodes.
Before we would fall off the end of some arrays, on top of the ambiguity
described above.

This change doesn't measureably affect performance on the twolf benchmark.
4147:df3e79e21b34 Mon Mar 05 09:53:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Added in a missing include.
/gem5/src/cpu/o3/
H A Drename_map.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
/gem5/src/sim/
H A Dinsttracer.hh12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A DProcess.py10496:0a5a8ecd0ec6 Wed Oct 22 18:53:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: add EmulatedDriver object

Fake SE-mode device drivers can now be added by
deriving from this abstract object.
/gem5/tests/configs/
H A Do3-timing-mp-ruby.py13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3

Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15999
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dtwosys-tsunami-simple-atomic.py13916:efa5b9e899e3 Wed May 01 16:53:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> tests: Add missing kernels to system creation

Change 149c1fc2d070a8ce073263880ecf2ccf7535e569 removed the
default value of the kernels, and fs tests rely on those.

Change-Id: I6d83420af5881ab59c2d223a9915f363dd8a1c69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18528
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/tests/
H A Drun.py13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3

Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15999
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/arch/power/linux/
H A Dprocess.cc13986:39ebcc8ea82a Fri May 03 01:53:00 EDT 2019 Gabe Black <gabeblack@google.com> power: Add an object file loader for linux.

Change-Id: I64ce81e98a6dc96754554d0fdcd7d16b8a2752d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18587
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
/gem5/src/arch/riscv/linux/
H A Dprocess.cc13987:0b79ddd399a4 Fri May 03 01:53:00 EDT 2019 Gabe Black <gabeblack@google.com> riscv: Add an object file loader for linux.

Change-Id: I3accca91cc4e02fa8e3a1169590cbe6696cf05e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18628
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
/gem5/configs/ruby/
H A DMESI_Three_Level.py12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/arm/isa/
H A Dincludes.isa6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/sparc/linux/
H A Dsyscalls.cc4264:2f156126a50d Tue Mar 20 23:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Ignore "time" and "times" syscalls.
/gem5/src/cpu/minor/
H A Dfetch2.cc10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
/gem5/src/mem/
H A Dabstract_mem.hh9707:1305bec2733f Thu May 30 00:53:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Avoid explicitly zeroing the memory backing store

This patch removes the explicit memset as it is redundant and causes
the simulator to touch the entire space, forcing the host system to
allocate the pages.

Anonymous pages are mapped on the first access, and the page-fault
handler is responsible for zeroing them. Thus, the pages are still
zeroed, but we avoid touching the entire allocated space which enables
us to use much larger memory sizes as long as not all the memory is
actually used.
H A Dport_proxy.hh14196:ce364f5517f3 Thu Aug 15 19:53:00 EDT 2019 Gabe Black <gabeblack@google.com> mem: Make PortProxy use a delegate for a sendFunctional function.

The only part of the MaserPort the PortProxy uses is the sendFunctional
function which is part of the functional protocol. Rather than require
a MasterPort which comes along with a lot of other mechanisms, this
change slightly adjusts the PortProxy to only require that function
through the use of a delegate. That allows lots of flexibility in how
the actual packet gets sent and what sends it.

In cases where code constructs a PortProxy and passes its constructor
an unbound MasterPort, the PortProxy will create a delegate to the
sendFunctional method on its own.

This should also make it easier for objects which don't have
traditional gem5 style ports, for instance systemc models, to implement
just the little bit of the protocol they need, rather than having to
stub out a whole port class, most of which will be ignored.

Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dport_proxy.cc14196:ce364f5517f3 Thu Aug 15 19:53:00 EDT 2019 Gabe Black <gabeblack@google.com> mem: Make PortProxy use a delegate for a sendFunctional function.

The only part of the MaserPort the PortProxy uses is the sendFunctional
function which is part of the functional protocol. Rather than require
a MasterPort which comes along with a lot of other mechanisms, this
change slightly adjusts the PortProxy to only require that function
through the use of a delegate. That allows lots of flexibility in how
the actual packet gets sent and what sends it.

In cases where code constructs a PortProxy and passes its constructor
an unbound MasterPort, the PortProxy will create a delegate to the
sendFunctional method on its own.

This should also make it easier for objects which don't have
traditional gem5 style ports, for instance systemc models, to implement
just the little bit of the protocol they need, rather than having to
stub out a whole port class, most of which will be ignored.

Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dfs_translating_port_proxy.cc14196:ce364f5517f3 Thu Aug 15 19:53:00 EDT 2019 Gabe Black <gabeblack@google.com> mem: Make PortProxy use a delegate for a sendFunctional function.

The only part of the MaserPort the PortProxy uses is the sendFunctional
function which is part of the functional protocol. Rather than require
a MasterPort which comes along with a lot of other mechanisms, this
change slightly adjusts the PortProxy to only require that function
through the use of a delegate. That allows lots of flexibility in how
the actual packet gets sent and what sends it.

In cases where code constructs a PortProxy and passes its constructor
an unbound MasterPort, the PortProxy will create a delegate to the
sendFunctional method on its own.

This should also make it easier for objects which don't have
traditional gem5 style ports, for instance systemc models, to implement
just the little bit of the protocol they need, rather than having to
stub out a whole port class, most of which will be ignored.

Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/arch/arm/
H A Dpmu.cc10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
H A Dremote_gdb.hh6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
H A Dtypes.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/generic/
H A Dtypes.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
/gem5/src/mem/slicc/symbols/
H A DStateMachine.py10972:53d63eeee46f Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> slicc: support for arbitrary DPRINTF flags (not just RubySlicc)

This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5. Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.
9597:f9b731fc6064 Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> slicc: remove check if the L1Cache has a sequencer
9596:aa73a81cf92c Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: move stall and wakeup functions to AbstractController
These functions are currently implemented in one of the files related to Slicc.
Since these are purely C++ functions, they are better suited to be in the base
class.
9595:470016acf37d Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.

Completed in 192 milliseconds

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