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/gem5/src/systemc/core/
H A Dsc_main.cc13097:6efbd43ab80e Sun Aug 26 18:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Handle sc_stop called from sc_main correctly.

When in sc_main, sc_is_running will return true but we're not going
to run any gem5 events since we're currently in the sc_main Fiber. In
that case, we need to do the sc_stop work inline.

If we're actually running and not just paused, then we do still want to
schedule the work of sc_stop to happen as its own event since that will
happen before returning to sc_main, and actually will likely be the
mechanism by which sc_main starts executing again.

Change-Id: If9ffafc4f240af0f3d9c726b36a0950b5219dc00
Reviewed-on: https://gem5-review.googlesource.com/12269
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
12956:264cdc9261e6 Mon Jul 16 18:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Hook up sc_time_stamp sc_delta_count.

sc_time_stamp reports the current simulation time. sc_delta_count was
hooked up to a dummy value. This change hooks it up to the scheduler so
that it returns the real value.

Change-Id: I354c4be32161eabeea86af653f5cb0a5d384645b
Reviewed-on: https://gem5-review.googlesource.com/11712
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/tests/configs/
H A Dbase_config.py13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3

Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15999
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dsimple-atomic-mp-ruby.py13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3

Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15999
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/ruby/profiler/
H A DProfiler.hh9599:e95479c2926f Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove unsued profile functions
9598:a58b28c17d7f Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: keep histogram of outstanding requests in seq
The histogram for tracking outstanding counts per cycle is maintained
in the profiler. For a parallel implementation of the memory system, we
need that this histogram is maintained locally. Hence it will now be
kept in the sequencer itself. The resulting histograms will be merged
when the stats are printed.
/gem5/src/arch/arm/
H A Dremote_gdb.cc10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA.
H A Dstage2_mmu.cc10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
H A DArmTLB.py6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/
H A DREADME5587:664630aaf316 Tue Oct 07 00:53:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Update the README and RELEASE_NOTES files to prepare for beta 6.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/
H A Dstats.txt10419:28b31101d9e6 Sun Sep 28 16:53:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect ARM fixes

As a result of the fixes, the full-system dual-core ARM regressions
are slightly changed. Hopefully this also means there will no longer
be any discrepancies between the results observed on different hosts.
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/
H A Dstats.txt9183:8ee71266699b Wed Sep 05 21:53:00 EDT 2012 Joel Hestness <hestness@cs.wisc.edu> stats: Update Ruby regressions for memory controller fix
/gem5/src/cpu/kvm/
H A Dvm.hh10605:8fc6e7a835d1 Wed Dec 10 00:53:00 EST 2014 Gabe Black <gabeblack@google.com> Let other objects set up memory like regions in a KVM VM.
/gem5/src/dev/arm/
H A Drealview.cc10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
/gem5/src/arch/x86/isa/microops/
H A Dbase.isa4524:f051dcff22b3 Mon Jun 04 15:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make limm (load immediate) microop
/gem5/src/arch/arm/isa/formats/
H A Dbranch.isa6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/arm/isa/insts/
H A Dmisc64.isa10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
/gem5/src/arch/power/
H A Dtlb.hh6972:b6482c4c89e3 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
/gem5/src/arch/sparc/isa/formats/mem/
H A Dbasicmem.isa3950:19a99edda63b Sun Dec 17 10:53:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Compilation fix after messy merge.
/gem5/src/base/
H A Dbitunion.hh5136:53c8a5da3d65 Sun Oct 07 21:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> BitUnion: Fix some types in the bitunion classes.
/gem5/src/mem/slicc/ast/
H A DFuncCallExprAST.py10972:53d63eeee46f Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> slicc: support for arbitrary DPRINTF flags (not just RubySlicc)

This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5. Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.
/gem5/configs/ruby/
H A DMESI_Two_Level.py12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A DMOESI_AMD_Base.py12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/sim/
H A Dinit.hh7502:3ef7ff12c788 Wed Jul 21 18:53:00 EDT 2010 Nathan Binkert <nate@binkert.org> python: Add mechanism to override code compiled into the exectuable
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to
True, then imports that would normally find python code compiled into
the executable will instead first check in the absolute location where
the code was found during the build of the executable. This only
works for files in the src (or extras) directories, not automatically
generated files.

This is a developer feature!
/gem5/src/mem/cache/
H A Dnoncoherent_cache.cc13948:f8666d4d5855 Thu Apr 18 09:53:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Remove writebacks packet list

Previously all atomic writebacks concerned a single block,
therefore, when a block was evicted, no other block would be
pending eviction. With sector tags (and compression),
however, a single replacement can generate many evictions.

This can cause problems, since a writeback that evicts a block
may evict blocks in the lower cache. If one of these conflict
with one of the blocks pending eviction in the higher level, the
snoop must inform it to the lower level. Since atomic mode does
not have a writebuffer, this kind of conflict wouldn't be noticed.

Therefore, instead of evicting multiple blocks at once, we
do it one by one.

Change-Id: I2fc2f9eb0f26248ddf91adbe987d158f5a2e592b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18209
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/ruby/slicc_interface/
H A DController.py9595:470016acf37d Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.
/gem5/src/mem/
H A Dfs_translating_port_proxy.hh14196:ce364f5517f3 Thu Aug 15 19:53:00 EDT 2019 Gabe Black <gabeblack@google.com> mem: Make PortProxy use a delegate for a sendFunctional function.

The only part of the MaserPort the PortProxy uses is the sendFunctional
function which is part of the functional protocol. Rather than require
a MasterPort which comes along with a lot of other mechanisms, this
change slightly adjusts the PortProxy to only require that function
through the use of a delegate. That allows lots of flexibility in how
the actual packet gets sent and what sends it.

In cases where code constructs a PortProxy and passes its constructor
an unbound MasterPort, the PortProxy will create a delegate to the
sendFunctional method on its own.

This should also make it easier for objects which don't have
traditional gem5 style ports, for instance systemc models, to implement
just the little bit of the protocol they need, rather than having to
stub out a whole port class, most of which will be ignored.

Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

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