1// -*- mode:c++ -*- 2 3// Copyright (c) 2011-2013, 2016-2018 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 svcCode = ''' 42 fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5)); 43 ''' 44 45 svcIop = InstObjParams("svc", "Svc64", "ImmOp64", 46 svcCode, ["IsSyscall", "IsNonSpeculative", 47 "IsSerializeAfter"]) 48 header_output = ImmOp64Declare.subst(svcIop) 49 decoder_output = ImmOp64Constructor.subst(svcIop) 50 exec_output = BasicExecute.subst(svcIop) 51 52 hvcCode = ''' 53 SCR scr = Scr64; 54 HCR hcr = Hcr64; 55 CPSR cpsr = Cpsr; 56 57 auto tc = xc->tcBase(); 58 ExceptionLevel pstate_EL = (ExceptionLevel)(uint8_t)(cpsr.el); 59 60 bool unalloc_encod = !ArmSystem::haveEL(tc, EL2) || pstate_EL == EL0 || 61 (pstate_EL == EL1 && inSecureState(tc)); 62 63 bool hvc_enable = ArmSystem::haveEL(tc, EL3) ? 64 scr.hce : !hcr.hcd; 65 66 if (unalloc_encod || !hvc_enable) { 67 fault = undefinedFault64(tc, pstate_EL); 68 } else { 69 fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5)); 70 } 71 ''' 72 73 hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64", 74 hvcCode, ["IsSyscall", "IsNonSpeculative", 75 "IsSerializeAfter"]) 76 header_output += ImmOp64Declare.subst(hvcIop) 77 decoder_output += ImmOp64Constructor.subst(hvcIop) 78 exec_output += BasicExecute.subst(hvcIop) 79 80 # @todo: extend to take into account Virtualization. 81 smcCode = ''' 82 SCR scr = Scr64; 83 CPSR cpsr = Cpsr; 84 85 if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) { 86 fault = disabledFault(); 87 } else { 88 fault = std::make_shared<SecureMonitorCall>(machInst); 89 } 90 ''' 91 92 smcIop = InstObjParams("smc", "Smc64", "ImmOp64", 93 smcCode, ["IsNonSpeculative", "IsSerializeAfter"]) 94 header_output += ImmOp64Declare.subst(smcIop) 95 decoder_output += ImmOp64Constructor.subst(smcIop) 96 exec_output += BasicExecute.subst(smcIop) 97 98 def subst(templateBase, iop): 99 global header_output, decoder_output, exec_output 100 header_output += eval(templateBase + "Declare").subst(iop) 101 decoder_output += eval(templateBase + "Constructor").subst(iop) 102 exec_output += BasicExecute.subst(iop) 103 104 bfmMaskCode = ''' 105 uint64_t bitMask; 106 int diff = imm2 - imm1; 107 if (imm1 <= imm2) { 108 bitMask = mask(diff + 1); 109 } else { 110 bitMask = mask(imm2 + 1); 111 bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1)); 112 diff += intWidth; 113 } 114 uint64_t topBits M5_VAR_USED = ~mask(diff+1); 115 uint64_t result = imm1 == 0 ? Op164 : 116 (Op164 >> imm1) | (Op164 << (intWidth - imm1)); 117 result &= bitMask; 118 ''' 119 120 bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);' 121 bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode); 122 subst("RegRegImmImmOp64", bfmIop) 123 124 ubfmCode = bfmMaskCode + 'Dest64 = result;' 125 ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode); 126 subst("RegRegImmImmOp64", ubfmIop) 127 128 sbfmCode = bfmMaskCode + \ 129 'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);' 130 sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode); 131 subst("RegRegImmImmOp64", sbfmIop) 132 133 extrCode = ''' 134 if (imm == 0) { 135 Dest64 = Op264; 136 } else { 137 Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm); 138 } 139 ''' 140 extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode); 141 subst("RegRegRegImmOp64", extrIop); 142 143 unknownCode = ''' 144 return std::make_shared<UndefinedInstruction>(machInst, true); 145 ''' 146 unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64", 147 unknownCode) 148 header_output += BasicDeclare.subst(unknown64Iop) 149 decoder_output += BasicConstructor64.subst(unknown64Iop) 150 exec_output += BasicExecute.subst(unknown64Iop) 151 152 isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "", 153 ['IsSquashAfter']) 154 header_output += BasicDeclare.subst(isbIop) 155 decoder_output += BasicConstructor64.subst(isbIop) 156 exec_output += BasicExecute.subst(isbIop) 157 158 dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "", 159 ['IsMemBarrier', 'IsSerializeAfter']) 160 header_output += BasicDeclare.subst(dsbIop) 161 decoder_output += BasicConstructor64.subst(dsbIop) 162 exec_output += BasicExecute.subst(dsbIop) 163 164 dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "", 165 ['IsMemBarrier']) 166 header_output += BasicDeclare.subst(dmbIop) 167 decoder_output += BasicConstructor64.subst(dmbIop) 168 exec_output += BasicExecute.subst(dmbIop) 169 170 clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst", 171 "LLSCLock = 0;") 172 header_output += BasicDeclare.subst(clrexIop) 173 decoder_output += BasicConstructor64.subst(clrexIop) 174 exec_output += BasicExecute.subst(clrexIop) 175 176 177 brkCode = ''' 178 fault = std::make_shared<SoftwareBreakpoint>(machInst, 179 bits(machInst, 20, 5)); 180 ''' 181 182 brkIop = InstObjParams("brk", "Brk64", "ImmOp64", 183 brkCode, ["IsSerializeAfter"]) 184 header_output += ImmOp64Declare.subst(brkIop) 185 decoder_output += ImmOp64Constructor.subst(brkIop) 186 exec_output += BasicExecute.subst(brkIop) 187 188 hltCode = ''' 189 ThreadContext *tc = xc->tcBase(); 190 if (ArmSystem::haveSemihosting(tc) && imm == 0xF000) { 191 X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1); 192 } else { 193 // HLT instructions aren't implemented, so treat them as undefined 194 // instructions. 195 fault = std::make_shared<UndefinedInstruction>( 196 machInst, false, mnemonic); 197 } 198 199 ''' 200 201 hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64", 202 hltCode, ["IsNonSpeculative"]) 203 header_output += ImmOp64Declare.subst(hltIop) 204 decoder_output += SemihostConstructor64.subst(hltIop) 205 exec_output += BasicExecute.subst(hltIop) 206}}; 207