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13354:c1bdac713ae5 |
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19-Sep-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
arm: update hint instruction decoding to match ARMv8.5
This fixes:
- unallocated hints that have since been allocated - unallocated and unimplemented hint instructions being treated as Unknown instead of the correct NOP - missing encoding for DBG on A32
Unallocated and unimplemented hints give a warning if executed.
The most important fix was for the CSDB Spectre mitigation instruction, which was added recently and previously unallocated and treated as Unknown.
The Linux kernel v4.18 ARMv7 uses CSDB it and boot would fail with "undefined instruction" since Linux commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613
Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13475 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12248:858685d552f6 |
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01-Nov-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Corrected encoding for T32 HVC instruction
This patch corrects the encoding of the HVC (Hypervisor Call) for the T32 instruction set.
Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5541 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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8909:7fa0a081f12f |
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21-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Clean up condCodes in IT blocks.
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7613:62159049ca81 |
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23-Aug-2010 |
Gene Wu <Gene.Wu@arm.com> |
ARM: Implement DBG instruction that doesn't do much for now.
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7605:94b2f78894ca |
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23-Aug-2010 |
Gene Wu <Gene.Wu@arm.com> |
ARM: Implement DSB, DMB, ISB
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7603:66d853e566d2 |
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23-Aug-2010 |
Gene Wu <Gene.Wu@arm.com> |
ARM: Implement CLREX
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7602:cd1930acae4e |
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23-Aug-2010 |
Gene Wu <Gene.Wu@arm.com> |
ARM: BX instruction can be contitional if last instruction in a IT block
Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond.
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7419:10e7f0f18461 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Hook the misc instructions into the thumb decoder.
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7344:82a4e24e7fad |
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02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: BXJ should be BX when there is no J support
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7316:bb190cb8ee69 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Decode the CPS instruction.
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7290:ea9189fbb84f |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Make sure some undefined thumb32 instructions fault.
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7284:cff2ad25550e |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Decode the enterx and leavex instructions.
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7281:e67b0c646268 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: When an instruction is intentionally undefined, fault on it.
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7252:bba68021edca |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Decode the clz instruction.
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7248:f5563135de40 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Decode the nop instruction.
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7204:8ed494406e30 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Decode MRS and MSR for thumb.
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7200:64bc968a1d10 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Hook SVC into the thumb decoder.
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7188:1310866e4ed5 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add support for "SUBS PC, LR and related instructions".
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7155:4c96244f0b8a |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Hook the new branch instructions into the 32 bit thumb decoder.
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7154:1fa6d1db1f32 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Hook the new branch instructions into the 16 bit thumb decoder.
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7153:6ce0bf0ddaf3 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Eliminate the old style branch instructions.
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7152:a1308654b445 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Hook the new branch instructions into the ARM decoder.
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7144:097e00bcf084 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Get rid of the unused Jump format.
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6724:70129fdded75 |
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08-Nov-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to control the behavior of the processor.
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6259:71dd4e07e626 |
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25-Jun-2009 |
Jack Whitman <jack-m5ml2@cs.york.ac.uk> |
ARM: Link register is trashed by non-executed branch and link operations.
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6253:988a001820f8 |
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21-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Simplify the ISA desc by pulling some classes out of it.
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6243:3a1698fbbc9f |
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21-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Make the isa parser aware that CPSR is being used.
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6242:1cee707c1228 |
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21-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Pull some static code out of the isa desc and create miscregs.hh.
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6019:76890d8b28f5 |
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05-Apr-2009 |
Stephen Hines <hines@cs.fsu.edu> |
arm: add ARM support to M5
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