16167SN/A
26167SN/A---------- Begin Simulation Statistics ----------
311680SCurtis.Dunham@arm.comsim_seconds                                  0.000112                       # Number of seconds simulated
411680SCurtis.Dunham@arm.comsim_ticks                                      112490                       # Number of ticks simulated
511680SCurtis.Dunham@arm.comfinal_tick                                     112490                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68721SN/Asim_freq                                   1000000000                       # Frequency of simulated ticks
711860Sandreas.hansson@arm.comhost_inst_rate                                 109524                       # Simulator instruction rate (inst/s)
811860Sandreas.hansson@arm.comhost_op_rate                                   109501                       # Simulator op (including micro ops) rate (op/s)
911860Sandreas.hansson@arm.comhost_tick_rate                                1923375                       # Simulator tick rate (ticks/s)
1011860Sandreas.hansson@arm.comhost_mem_usage                                 415960                       # Number of bytes of host memory used
1111687Sandreas.hansson@arm.comhost_seconds                                     0.06                       # Real time elapsed on the host
1211390Ssteve.reinhardt@amd.comsim_insts                                        6403                       # Number of instructions simulated
1311390Ssteve.reinhardt@amd.comsim_ops                                          6403                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                             1                       # Clock period in ticks
1611680SCurtis.Dunham@arm.comsystem.mem_ctrls.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
1711390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_read::ruby.dir_cntrl0       110784                       # Number of bytes read from this memory
1811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_read::total             110784                       # Number of bytes read from this memory
1911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_written::ruby.dir_cntrl0       110528                       # Number of bytes written to this memory
2011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_written::total          110528                       # Number of bytes written to this memory
2111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_reads::ruby.dir_cntrl0         1731                       # Number of read requests responded to by this memory
2211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_reads::total                1731                       # Number of read requests responded to by this memory
2311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_writes::ruby.dir_cntrl0         1727                       # Number of write requests responded to by this memory
2411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_writes::total               1727                       # Number of write requests responded to by this memory
2511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0    984834207                       # Total read bandwidth from this memory (bytes/s)
2611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::total             984834207                       # Total read bandwidth from this memory (bytes/s)
2711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0    982558450                       # Write bandwidth from this memory (bytes/s)
2811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::total            982558450                       # Write bandwidth from this memory (bytes/s)
2911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0   1967392657                       # Total bandwidth to/from this memory (bytes/s)
3011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::total           1967392657                       # Total bandwidth to/from this memory (bytes/s)
3111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readReqs                        1731                       # Number of read requests accepted
3211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeReqs                       1727                       # Number of write requests accepted
3311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readBursts                      1731                       # Number of DRAM read bursts, including those serviced by the write queue
3411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeBursts                     1727                       # Number of DRAM write bursts, including those merged in the write queue
3511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadDRAM                  56704                       # Total number of bytes read from DRAM
3611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadWrQ                   54080                       # Total number of bytes read from write queue
3711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesWritten                   57088                       # Total number of bytes written to DRAM
3811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesReadSys                  110784                       # Total read bytes from the system interface side
3911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesWrittenSys               110528                       # Total written bytes from the system interface side
4011680SCurtis.Dunham@arm.comsystem.mem_ctrls.servicedByWrQ                    845                       # Number of DRAM read bursts serviced by the write queue
4111680SCurtis.Dunham@arm.comsystem.mem_ctrls.mergedWrBursts                   803                       # Number of DRAM write bursts merged with an existing one
4210526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::0                83                       # Per bank write bursts
4411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::1                50                       # Per bank write bursts
4511680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::2                70                       # Per bank write bursts
4611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::3                63                       # Per bank write bursts
4711680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::4               108                       # Per bank write bursts
4811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::5                23                       # Per bank write bursts
4910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::6                 1                       # Per bank write bursts
5010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::7                 3                       # Per bank write bursts
5110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::8                 0                       # Per bank write bursts
5210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::9                 1                       # Per bank write bursts
5311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::10               55                       # Per bank write bursts
5411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::11               36                       # Per bank write bursts
5511680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::12               18                       # Per bank write bursts
5611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::13              270                       # Per bank write bursts
5711680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::14               81                       # Per bank write bursts
5811680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::15               24                       # Per bank write bursts
5911680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::0                82                       # Per bank write bursts
6011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::1                51                       # Per bank write bursts
6111680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::2                73                       # Per bank write bursts
6211680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::3                60                       # Per bank write bursts
6311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::4               126                       # Per bank write bursts
6411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::5                27                       # Per bank write bursts
6510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::6                 1                       # Per bank write bursts
6611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::7                 3                       # Per bank write bursts
6710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
6810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::9                 1                       # Per bank write bursts
6911680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::10               50                       # Per bank write bursts
7011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::11               33                       # Per bank write bursts
7111680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::12               12                       # Per bank write bursts
7211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::13              268                       # Per bank write bursts
7311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::14               81                       # Per bank write bursts
7411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::15               24                       # Per bank write bursts
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7610526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7711680SCurtis.Dunham@arm.comsystem.mem_ctrls.totGap                        112412                       # Total gap between requests
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.readPktSize::6                  1731                       # Read request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.writePktSize::6                 1727                       # Write request sizes (log2)
9211680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::0                     886                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
14011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::16                      6                       # What write queue length does an incoming req see
14111680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::17                     51                       # What write queue length does an incoming req see
14211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::18                     57                       # What write queue length does an incoming req see
14311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::19                     57                       # What write queue length does an incoming req see
14411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::20                     56                       # What write queue length does an incoming req see
14511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::21                     60                       # What write queue length does an incoming req see
14611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::22                     57                       # What write queue length does an incoming req see
14711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::23                     56                       # What write queue length does an incoming req see
14811390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::24                     56                       # What write queue length does an incoming req see
14911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::25                     56                       # What write queue length does an incoming req see
15011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::26                     56                       # What write queue length does an incoming req see
15111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::27                     56                       # What write queue length does an incoming req see
15211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::28                     56                       # What write queue length does an incoming req see
15311390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::29                     56                       # What write queue length does an incoming req see
15411390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::30                     56                       # What write queue length does an incoming req see
15511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::31                     56                       # What write queue length does an incoming req see
15611390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::32                     55                       # What write queue length does an incoming req see
15711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::samples          264                       # Bytes accessed per row activation
18911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::mean           424                       # Bytes accessed per row activation
19011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::gmean   260.079273                       # Bytes accessed per row activation
19111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::stdev   372.426347                       # Bytes accessed per row activation
19211680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::0-127           66     25.00%     25.00% # Bytes accessed per row activation
19311680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::128-255           58     21.97%     46.97% # Bytes accessed per row activation
19411680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::256-383           27     10.23%     57.20% # Bytes accessed per row activation
19511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::384-511           16      6.06%     63.26% # Bytes accessed per row activation
19611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::512-639           17      6.44%     69.70% # Bytes accessed per row activation
19711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::640-767            8      3.03%     72.73% # Bytes accessed per row activation
19811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::768-895           12      4.55%     77.27% # Bytes accessed per row activation
19911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::896-1023           10      3.79%     81.06% # Bytes accessed per row activation
20011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::1024-1151           50     18.94%    100.00% # Bytes accessed per row activation
20111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::total          264                       # Bytes accessed per row activation
20211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::samples           55                       # Reads before turning the bus around for writes
20311680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::mean      15.818182                       # Reads before turning the bus around for writes
20411680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::gmean     15.638991                       # Reads before turning the bus around for writes
20511680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::stdev      2.938196                       # Reads before turning the bus around for writes
20611680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::12-13             3      5.45%      5.45% # Reads before turning the bus around for writes
20711680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::14-15            24     43.64%     49.09% # Reads before turning the bus around for writes
20811680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::16-17            23     41.82%     90.91% # Reads before turning the bus around for writes
20911390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::18-19             4      7.27%     98.18% # Reads before turning the bus around for writes
21011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::34-35             1      1.82%    100.00% # Reads before turning the bus around for writes
21111390Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::total            55                       # Reads before turning the bus around for writes
21211390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::samples           55                       # Writes before turning the bus around for reads
21311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::mean      16.218182                       # Writes before turning the bus around for reads
21411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::gmean     16.206001                       # Writes before turning the bus around for reads
21511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::stdev      0.658025                       # Writes before turning the bus around for reads
21611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::16               49     89.09%     89.09% # Writes before turning the bus around for reads
21711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::17                1      1.82%     90.91% # Writes before turning the bus around for reads
21811680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::18                4      7.27%     98.18% # Writes before turning the bus around for reads
21911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::19                1      1.82%    100.00% # Writes before turning the bus around for reads
22011390Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::total            55                       # Writes before turning the bus around for reads
22111680SCurtis.Dunham@arm.comsystem.mem_ctrls.totQLat                        16225                       # Total ticks spent queuing
22211680SCurtis.Dunham@arm.comsystem.mem_ctrls.totMemAccLat                   33059                       # Total ticks spent from burst creation until serviced by the DRAM
22311680SCurtis.Dunham@arm.comsystem.mem_ctrls.totBusLat                       4430                       # Total ticks spent in databus transfers
22411680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgQLat                        18.31                       # Average queueing delay per DRAM burst
22510526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
22611680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgMemAccLat                   37.31                       # Average memory access latency per DRAM burst
22711680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBW                       504.08                       # Average DRAM read bandwidth in MiByte/s
22811680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrBW                       507.49                       # Average achieved write bandwidth in MiByte/s
22911680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBWSys                    984.83                       # Average system read bandwidth in MiByte/s
23011680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrBWSys                    982.56                       # Average system write bandwidth in MiByte/s
23110526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
23211680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtil                         7.90                       # Data bus utilization in percentage
23311680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtilRead                     3.94                       # Data bus utilization in percentage for reads
23411680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtilWrite                    3.96                       # Data bus utilization in percentage for writes
23510526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
23611680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrQLen                      26.10                       # Average write queue length when enqueuing
23711680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHits                      674                       # Number of row buffer hits during reads
23811680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeRowHits                     833                       # Number of row buffer hits during writes
23911680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHitRate                 76.07                       # Row buffer hit rate for reads
24011680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeRowHitRate                90.15                       # Row buffer hit rate for writes
24111680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgGap                         32.51                       # Average gap between requests
24211680SCurtis.Dunham@arm.comsystem.mem_ctrls.pageHitRate                    83.26                       # Row buffer hit rate, read and write combined
24311680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actEnergy                   735420                       # Energy for activate commands per rank (pJ)
24411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preEnergy                   386400                       # Energy for precharge commands per rank (pJ)
24511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.readEnergy                 4581024                       # Energy for read commands per rank (pJ)
24611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.writeEnergy                3532896                       # Energy for write commands per rank (pJ)
24711680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
24811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actBackEnergy             13923048                       # Energy for active background per rank (pJ)
24911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preBackEnergy               195072                       # Energy for precharge background per rank (pJ)
25011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actPowerDownEnergy        30921360                       # Energy for active power-down per rank (pJ)
25111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.prePowerDownEnergy         5237376                       # Energy for precharge power-down per rank (pJ)
25211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
25311680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalEnergy               68117556                       # Total energy per rank (pJ)
25411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.averagePower            605.543213                       # Core power per rank (mW)
25511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalIdleTime                81406                       # Total Idle time Per DRAM Rank
25611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE           88                       # Time in different power states
25711680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::REF          3640                       # Time in different power states
25811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::SREF            0                       # Time in different power states
25911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN        13639                       # Time in different power states
26011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT         27313                       # Time in different power states
26111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN        67810                       # Time in different power states
26211680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actEnergy                  1199520                       # Energy for activate commands per rank (pJ)
26311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preEnergy                   633696                       # Energy for precharge commands per rank (pJ)
26411680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.readEnergy                 5540640                       # Energy for read commands per rank (pJ)
26511680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.writeEnergy                3917088                       # Energy for write commands per rank (pJ)
26611680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.refreshEnergy         8604960.000000                       # Energy for refresh commands per rank (pJ)
26711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actBackEnergy             12524952                       # Energy for active background per rank (pJ)
26811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preBackEnergy               314880                       # Energy for precharge background per rank (pJ)
26911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actPowerDownEnergy        33139344                       # Energy for active power-down per rank (pJ)
27011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.prePowerDownEnergy         4427136                       # Energy for precharge power-down per rank (pJ)
27111680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.selfRefreshEnergy                0                       # Energy for self refresh per rank (pJ)
27211680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalEnergy               70302216                       # Total energy per rank (pJ)
27311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.averagePower            624.964139                       # Core power per rank (mW)
27411680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalIdleTime                83983                       # Total Idle time Per DRAM Rank
27511680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE          260                       # Time in different power states
27611680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
27711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::SREF            0                       # Time in different power states
27811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN        11529                       # Time in different power states
27911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT         24387                       # Time in different power states
28011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN        72674                       # Time in different power states
28111680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
28210526Snilay@cs.wisc.edusystem.cpu.clk_domain.clock                         1                       # Clock period in ticks
2838721SN/Asystem.cpu.dtb.fetch_hits                           0                       # ITB hits
2848721SN/Asystem.cpu.dtb.fetch_misses                         0                       # ITB misses
2858721SN/Asystem.cpu.dtb.fetch_acv                            0                       # ITB acv
2868721SN/Asystem.cpu.dtb.fetch_accesses                       0                       # ITB accesses
28711390Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_hits                         1185                       # DTB read hits
2888721SN/Asystem.cpu.dtb.read_misses                          7                       # DTB read misses
2898721SN/Asystem.cpu.dtb.read_acv                             0                       # DTB read access violations
29011390Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_accesses                     1192                       # DTB read accesses
2918721SN/Asystem.cpu.dtb.write_hits                         865                       # DTB write hits
2928721SN/Asystem.cpu.dtb.write_misses                         3                       # DTB write misses
2938721SN/Asystem.cpu.dtb.write_acv                            0                       # DTB write access violations
2948721SN/Asystem.cpu.dtb.write_accesses                     868                       # DTB write accesses
29511390Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_hits                         2050                       # DTB hits
2966167SN/Asystem.cpu.dtb.data_misses                         10                       # DTB misses
2978721SN/Asystem.cpu.dtb.data_acv                             0                       # DTB access violations
29811390Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_accesses                     2060                       # DTB accesses
29911390Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_hits                        6414                       # ITB hits
3008721SN/Asystem.cpu.itb.fetch_misses                        17                       # ITB misses
3018721SN/Asystem.cpu.itb.fetch_acv                            0                       # ITB acv
30211390Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_accesses                    6431                       # ITB accesses
3038721SN/Asystem.cpu.itb.read_hits                            0                       # DTB read hits
3048721SN/Asystem.cpu.itb.read_misses                          0                       # DTB read misses
3058721SN/Asystem.cpu.itb.read_acv                             0                       # DTB read access violations
3068721SN/Asystem.cpu.itb.read_accesses                        0                       # DTB read accesses
3078721SN/Asystem.cpu.itb.write_hits                           0                       # DTB write hits
3088721SN/Asystem.cpu.itb.write_misses                         0                       # DTB write misses
3098721SN/Asystem.cpu.itb.write_acv                            0                       # DTB write access violations
3108721SN/Asystem.cpu.itb.write_accesses                       0                       # DTB write accesses
3116167SN/Asystem.cpu.itb.data_hits                            0                       # DTB hits
3126167SN/Asystem.cpu.itb.data_misses                          0                       # DTB misses
3138721SN/Asystem.cpu.itb.data_acv                             0                       # DTB access violations
3148721SN/Asystem.cpu.itb.data_accesses                        0                       # DTB accesses
31511955Sgabeblack@google.comsystem.cpu.workload.numSyscalls                    17                       # Number of system calls
31611680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON          112490                       # Cumulative time (in ticks) in various power states
31711680SCurtis.Dunham@arm.comsystem.cpu.numCycles                           112490                       # number of cpu cycles simulated
3188721SN/Asystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
3197935SN/Asystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
32011390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts                        6403                       # Number of instructions committed
32111390Ssteve.reinhardt@amd.comsystem.cpu.committedOps                          6403                       # Number of ops (including micro ops) committed
32211390Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses                  6329                       # Number of integer alu accesses
3238721SN/Asystem.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
3248721SN/Asystem.cpu.num_func_calls                         251                       # number of times a function call or return occured
32511390Ssteve.reinhardt@amd.comsystem.cpu.num_conditional_control_insts          754                       # number of instructions that are conditional controls
32611390Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts                         6329                       # number of integer instructions
3277935SN/Asystem.cpu.num_fp_insts                            10                       # number of float instructions
32811390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads                8297                       # number of times the integer registers were read
32911390Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes               4575                       # number of times the integer registers were written
3307935SN/Asystem.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
3317935SN/Asystem.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
33211390Ssteve.reinhardt@amd.comsystem.cpu.num_mem_refs                          2060                       # number of memory refs
33311390Ssteve.reinhardt@amd.comsystem.cpu.num_load_insts                        1192                       # Number of load instructions
3348721SN/Asystem.cpu.num_store_insts                        868                       # Number of store instructions
3357935SN/Asystem.cpu.num_idle_cycles                          0                       # Number of idle cycles
33611680SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles                     112490                       # Number of busy cycles
3378721SN/Asystem.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
3388721SN/Asystem.cpu.idle_fraction                            0                       # Percentage of idle cycles
33911390Ssteve.reinhardt@amd.comsystem.cpu.Branches                              1056                       # Number of branches fetched
34010220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
34111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntAlu                      4331     67.53%     67.83% # Class of executed instruction
34211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntMult                        1      0.02%     67.85% # Class of executed instruction
34311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::IntDiv                         0      0.00%     67.85% # Class of executed instruction
34411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatAdd                       2      0.03%     67.88% # Class of executed instruction
34511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCmp                       0      0.00%     67.88% # Class of executed instruction
34611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatCvt                       0      0.00%     67.88% # Class of executed instruction
34711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatMult                      0      0.00%     67.88% # Class of executed instruction
34811687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMultAcc                   0      0.00%     67.88% # Class of executed instruction
34911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatDiv                       0      0.00%     67.88% # Class of executed instruction
35011687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMisc                      0      0.00%     67.88% # Class of executed instruction
35111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::FloatSqrt                      0      0.00%     67.88% # Class of executed instruction
35211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAdd                        0      0.00%     67.88% # Class of executed instruction
35311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAddAcc                     0      0.00%     67.88% # Class of executed instruction
35411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdAlu                        0      0.00%     67.88% # Class of executed instruction
35511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCmp                        0      0.00%     67.88% # Class of executed instruction
35611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdCvt                        0      0.00%     67.88% # Class of executed instruction
35711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMisc                       0      0.00%     67.88% # Class of executed instruction
35811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMult                       0      0.00%     67.88% # Class of executed instruction
35911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdMultAcc                    0      0.00%     67.88% # Class of executed instruction
36011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShift                      0      0.00%     67.88% # Class of executed instruction
36111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdShiftAcc                   0      0.00%     67.88% # Class of executed instruction
36211390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdSqrt                       0      0.00%     67.88% # Class of executed instruction
36311390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAdd                   0      0.00%     67.88% # Class of executed instruction
36411390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatAlu                   0      0.00%     67.88% # Class of executed instruction
36511390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCmp                   0      0.00%     67.88% # Class of executed instruction
36611390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatCvt                   0      0.00%     67.88% # Class of executed instruction
36711390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatDiv                   0      0.00%     67.88% # Class of executed instruction
36811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMisc                  0      0.00%     67.88% # Class of executed instruction
36911390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMult                  0      0.00%     67.88% # Class of executed instruction
37011390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.88% # Class of executed instruction
37111390Ssteve.reinhardt@amd.comsystem.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.88% # Class of executed instruction
37211687Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead                     1191     18.57%     86.45% # Class of executed instruction
37311687Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite                     861     13.43%     99.88% # Class of executed instruction
37411687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemRead                   1      0.02%     99.89% # Class of executed instruction
37511687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemWrite                  7      0.11%    100.00% # Class of executed instruction
37610220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
37710220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
37811390Ssteve.reinhardt@amd.comsystem.cpu.op_class::total                       6413                       # Class of executed instruction
37910628Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock                        1                       # Clock period in ticks
38011680SCurtis.Dunham@arm.comsystem.ruby.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
38110628Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
38210628Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
38311390Ssteve.reinhardt@amd.comsystem.ruby.delayHist::samples                   3458                       # delay histogram for all message
38411390Ssteve.reinhardt@amd.comsystem.ruby.delayHist                    |        3458    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
38511390Ssteve.reinhardt@amd.comsystem.ruby.delayHist::total                     3458                       # delay histogram for all message
38611312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::bucket_size            1                      
38711312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::max_bucket            9                      
38811390Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr::samples         8464                      
38911312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::mean            1                      
39011312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::gmean            1                      
39111390Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr    |           0      0.00%      0.00% |        8464    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
39211390Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr::total         8464                      
39311312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::bucket_size           64                      
39411312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::max_bucket          639                      
39511390Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::samples           8463                      
39611680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::mean         12.291977                      
39711680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::gmean         2.221869                      
39811680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::stdev        27.407806                      
39911680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr            |        7608     89.90%     89.90% |         798      9.43%     99.33% |          40      0.47%     99.80% |           5      0.06%     99.86% |           6      0.07%     99.93% |           6      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
40011390Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::total             8463                      
40111312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::bucket_size            1                      
40211312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::max_bucket            9                      
40311390Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr::samples         6732                      
40411312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::mean             1                      
40511312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::gmean            1                      
40611390Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |        6732    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
40711390Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr::total         6732                      
40811312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::bucket_size           64                      
40911312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::max_bucket          639                      
41011390Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::samples         1731                      
41111680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::mean    56.207395                      
41211680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::gmean    49.560362                      
41311680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::stdev    35.333412                      
41411680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr       |         876     50.61%     50.61% |         798     46.10%     96.71% |          40      2.31%     99.02% |           5      0.29%     99.31% |           6      0.35%     99.65% |           6      0.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
41511390Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::total         1731                      
41611390Ssteve.reinhardt@amd.comsystem.ruby.Directory.incomplete_times_seqr         1730                      
41711860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs     0.015352                       # Average number of messages in buffer
41811860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.forwardFromDir.avg_stall_time     0.997813                       # Average number of cycles messages are stalled in this MB
41911860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.requestToDir.avg_buf_msgs     0.030740                       # Average number of messages in buffer
42011860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.requestToDir.avg_stall_time    11.743091                       # Average number of cycles messages are stalled in this MB
42111860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs     0.015388                       # Average number of messages in buffer
42211860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromDir.avg_stall_time     0.999387                       # Average number of cycles messages are stalled in this MB
42311860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs     0.030740                       # Average number of messages in buffer
42411860Sandreas.hansson@arm.comsystem.ruby.dir_cntrl0.responseFromMemory.avg_stall_time     0.999396                       # Average number of cycles messages are stalled in this MB
42511680SCurtis.Dunham@arm.comsystem.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
42611390Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.cacheMemory.demand_hits         6732                       # Number of cache demand hits
42711390Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.cacheMemory.demand_misses         1731                       # Number of cache demand misses
42811390Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.cacheMemory.demand_accesses         8463                       # Number of cache demand accesses
42911860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs     0.015352                       # Average number of messages in buffer
43011860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.forwardToCache.avg_stall_time     6.984319                       # Average number of cycles messages are stalled in this MB
43111860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs     0.075242                       # Average number of messages in buffer
43211860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time     0.999991                       # Average number of cycles messages are stalled in this MB
43311860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs     0.061480                       # Average number of messages in buffer
43411860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.requestFromCache.avg_stall_time     1.999947                       # Average number of cycles messages are stalled in this MB
43511860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.responseToCache.avg_buf_msgs     0.015388                       # Average number of messages in buffer
43611860Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.responseToCache.avg_stall_time     6.995333                       # Average number of cycles messages are stalled in this MB
43711680SCurtis.Dunham@arm.comsystem.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
43811680SCurtis.Dunham@arm.comsystem.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
43910628Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
44011860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers03.avg_buf_msgs     0.015352                       # Average number of messages in buffer
44111860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers03.avg_stall_time     5.986612                       # Average number of cycles messages are stalled in this MB
44211860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers04.avg_buf_msgs     0.015388                       # Average number of messages in buffer
44311860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers04.avg_stall_time     5.996053                       # Average number of cycles messages are stalled in this MB
44411860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers07.avg_buf_msgs     0.092150                       # Average number of messages in buffer
44511860Sandreas.hansson@arm.comsystem.ruby.network.routers0.port_buffers07.avg_stall_time     6.743802                       # Average number of cycles messages are stalled in this MB
44611680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
44711680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.percent_links_utilized     7.685128                      
44811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Control::2         1731                      
44911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Data::2         1727                      
45011390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Response_Data::4         1731                      
45111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Writeback_Control::3         1727                      
45211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Control::2        13848                      
45311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Data::2       124344                      
45411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Response_Data::4       124632                      
45511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::3        13816                      
45611860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers02.avg_buf_msgs     0.030740                       # Average number of messages in buffer
45711860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers02.avg_stall_time    10.743268                       # Average number of cycles messages are stalled in this MB
45811860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers06.avg_buf_msgs     0.015352                       # Average number of messages in buffer
45911860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers06.avg_stall_time     1.995609                       # Average number of cycles messages are stalled in this MB
46011860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers07.avg_buf_msgs     0.015388                       # Average number of messages in buffer
46111860Sandreas.hansson@arm.comsystem.ruby.network.routers1.port_buffers07.avg_stall_time     1.998755                       # Average number of cycles messages are stalled in this MB
46211680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
46311680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.percent_links_utilized     7.685128                      
46411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Control::2         1731                      
46511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Data::2         1727                      
46611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Response_Data::4         1731                      
46711390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Writeback_Control::3         1727                      
46811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Control::2        13848                      
46911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Data::2       124344                      
47011390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Response_Data::4       124632                      
47111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::3        13816                      
47211860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers02.avg_buf_msgs     0.030740                       # Average number of messages in buffer
47311860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers02.avg_stall_time     7.743695                       # Average number of cycles messages are stalled in this MB
47411860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers08.avg_buf_msgs     0.015352                       # Average number of messages in buffer
47511860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers08.avg_stall_time     2.993386                       # Average number of cycles messages are stalled in this MB
47611860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers09.avg_buf_msgs     0.015388                       # Average number of messages in buffer
47711860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers09.avg_stall_time     2.998107                       # Average number of cycles messages are stalled in this MB
47811860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers13.avg_buf_msgs     0.015352                       # Average number of messages in buffer
47911860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers13.avg_stall_time     4.988888                       # Average number of cycles messages are stalled in this MB
48011860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers14.avg_buf_msgs     0.015388                       # Average number of messages in buffer
48111860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers14.avg_stall_time     4.996755                       # Average number of cycles messages are stalled in this MB
48211860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers17.avg_buf_msgs     0.030740                       # Average number of messages in buffer
48311860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers17.avg_stall_time     9.743428                       # Average number of cycles messages are stalled in this MB
48411860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers03.avg_buf_msgs     0.015352                       # Average number of messages in buffer
48511860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers03.avg_stall_time     3.991146                       # Average number of cycles messages are stalled in this MB
48611860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers04.avg_buf_msgs     0.015388                       # Average number of messages in buffer
48711860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers04.avg_stall_time     3.997440                       # Average number of cycles messages are stalled in this MB
48811860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers07.avg_buf_msgs     0.030740                       # Average number of messages in buffer
48911860Sandreas.hansson@arm.comsystem.ruby.network.routers2.port_buffers07.avg_stall_time     8.743571                       # Average number of cycles messages are stalled in this MB
49011680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
49111680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.percent_links_utilized     7.685128                      
49211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Control::2         1731                      
49311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Data::2         1727                      
49411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Response_Data::4         1731                      
49511390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Writeback_Control::3         1727                      
49611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Control::2        13848                      
49711390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Data::2       124344                      
49811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Response_Data::4       124632                      
49911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::3        13816                      
50011680SCurtis.Dunham@arm.comsystem.ruby.network.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
50111390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Control            5193                      
50211390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Data               5181                      
50311390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Response_Data         5193                      
50411390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Writeback_Control         5181                      
50511390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Control            41544                      
50611390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Data              373032                      
50711390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Response_Data       373896                      
50811390Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Writeback_Control        41448                      
50911680SCurtis.Dunham@arm.comsystem.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED       112490                       # Cumulative time (in ticks) in various power states
51011680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.throttle0.link_utilization     7.692239                      
51111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1731                      
51211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1727                      
51311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4       124632                      
51411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        13816                      
51511680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.throttle1.link_utilization     7.678016                      
51611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Control::2         1731                      
51711390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Data::2         1727                      
51811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Control::2        13848                      
51911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Data::2       124344                      
52011680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.throttle0.link_utilization     7.678016                      
52111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_count.Control::2         1731                      
52211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_count.Data::2         1727                      
52311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_bytes.Control::2        13848                      
52411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_bytes.Data::2       124344                      
52511680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.throttle1.link_utilization     7.692239                      
52611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1731                      
52711390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1727                      
52811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4       124632                      
52911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        13816                      
53011680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.throttle0.link_utilization     7.692239                      
53111390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1731                      
53211390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1727                      
53311390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4       124632                      
53411390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        13816                      
53511680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.throttle1.link_utilization     7.678016                      
53611390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Control::2         1731                      
53711390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Data::2         1727                      
53811390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Control::2        13848                      
53911390Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Data::2       124344                      
54010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
54110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
54211390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::samples          1731                       # delay histogram for vnet_1
54311390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1           |        1731    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
54411390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::total            1731                       # delay histogram for vnet_1
54510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
54610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
54711390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::samples          1727                       # delay histogram for vnet_2
54811390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2           |        1727    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
54911390Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::total            1727                       # delay histogram for vnet_2
55011312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::bucket_size           64                      
55111312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::max_bucket          639                      
55211390Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::samples         1185                      
55311680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::mean      33.356118                      
55411680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::gmean     10.708915                      
55511680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::stdev     36.387225                      
55611680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr         |         862     72.74%     72.74% |         301     25.40%     98.14% |          16      1.35%     99.49% |           3      0.25%     99.75% |           1      0.08%     99.83% |           2      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
55711390Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::total          1185                      
55811312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
55911312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
56011390Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples          457                      
56111312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::mean            1                      
56211312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::gmean            1                      
56311390Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |         457    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
56411390Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total          457                      
56511312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size           64                      
56611312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket          639                      
56711390Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::samples          728                      
56811680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::mean    53.667582                      
56911680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::gmean    47.442261                      
57011680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::stdev    32.940895                      
57111680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr    |         405     55.63%     55.63% |         301     41.35%     96.98% |          16      2.20%     99.18% |           3      0.41%     99.59% |           1      0.14%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
57211390Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::total          728                      
57311312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::bucket_size           32                      
57411312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::max_bucket          319                      
57511312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::samples          865                      
57611680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::mean      17.479769                      
57711680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::gmean      3.361529                      
57811680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::stdev     31.340829                      
57911680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr         |         592     68.44%     68.44% |         160     18.50%     86.94% |         102     11.79%     98.73% |           0      0.00%     98.73% |           4      0.46%     99.19% |           4      0.46%     99.65% |           1      0.12%     99.77% |           0      0.00%     99.77% |           1      0.12%     99.88% |           1      0.12%    100.00%
58011312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::total           865                      
58111312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
58211312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
58311312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples          592                      
58411312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::mean            1                      
58511312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::gmean            1                      
58611312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |         592    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
58711312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total          592                      
58811312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size           32                      
58911312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket          319                      
59011312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples          273                      
59111680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::mean    53.216117                      
59211680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::gmean    46.594106                      
59311680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::stdev    35.315815                      
59411680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr    |           0      0.00%      0.00% |         160     58.61%     58.61% |         102     37.36%     95.97% |           0      0.00%     95.97% |           4      1.47%     97.44% |           4      1.47%     98.90% |           1      0.37%     99.27% |           0      0.00%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00%
59511312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total          273                      
59611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size           64                      
59711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket          639                      
59811390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples         6413                      
59911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::mean     7.699984                      
60011680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::gmean     1.571280                      
60111680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::stdev    22.534194                      
60211680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr     |        5994     93.47%     93.47% |         395      6.16%     99.63% |          16      0.25%     99.88% |           1      0.02%     99.89% |           3      0.05%     99.94% |           4      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
60311390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total         6413                      
60411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
60511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
60611390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples         5683                      
60711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean            1                      
60811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean            1                      
60911390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |        5683    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
61011390Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total         5683                      
61111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::bucket_size           64                      
61211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::max_bucket          639                      
61311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::samples          730                      
61411680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::mean    59.858904                      
61511680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::gmean    52.975537                      
61611680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::stdev    37.310775                      
61711680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr |         311     42.60%     42.60% |         395     54.11%     96.71% |          16      2.19%     98.90% |           1      0.14%     99.04% |           3      0.41%     99.45% |           4      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
61811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::total          730                      
61911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size           64                      
62011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket          639                      
62111390Ssteve.reinhardt@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::samples         1731                      
62211680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::mean    56.207395                      
62311680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::gmean    49.560362                      
62411680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::stdev    35.333412                      
62511680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr |         876     50.61%     50.61% |         798     46.10%     96.71% |          40      2.31%     99.02% |           5      0.29%     99.31% |           6      0.35%     99.65% |           6      0.35%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
62611390Ssteve.reinhardt@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::total         1731                      
62711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size            1                      
62811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket            9                      
62911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples            1                      
63011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev          nan                      
63111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
63211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total            1                      
63311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size            1                      
63411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket            9                      
63511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples            1                      
63611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev          nan                      
63711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
63811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total            1                      
63911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size            1                      
64011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket            9                      
64111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples            1                      
64211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev          nan                      
64311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
64411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total            1                      
64511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size            8                      
64611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket           79                      
64711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples            1                      
64811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean           75                      
64911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean    75.000000                      
65011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev          nan                      
65111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
65211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total            1                      
65311312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
65411312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
65511390Ssteve.reinhardt@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples          728                      
65611680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean    53.667582                      
65711680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean    47.442261                      
65811680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev    32.940895                      
65911680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr |         405     55.63%     55.63% |         301     41.35%     96.98% |          16      2.20%     99.18% |           3      0.41%     99.59% |           1      0.14%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
66011390Ssteve.reinhardt@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total          728                      
66111312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size           32                      
66211312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket          319                      
66311312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples          273                      
66411680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean    53.216117                      
66511680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean    46.594106                      
66611680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev    35.315815                      
66711680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr |           0      0.00%      0.00% |         160     58.61%     58.61% |         102     37.36%     95.97% |           0      0.00%     95.97% |           4      1.47%     97.44% |           4      1.47%     98.90% |           1      0.37%     99.27% |           0      0.00%     99.27% |           1      0.37%     99.63% |           1      0.37%    100.00%
66811312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total          273                      
66911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size           64                      
67011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket          639                      
67111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples          730                      
67211680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean    59.858904                      
67311680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean    52.975537                      
67411680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev    37.310775                      
67511680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr |         311     42.60%     42.60% |         395     54.11%     96.71% |          16      2.19%     98.90% |           1      0.14%     99.04% |           3      0.41%     99.45% |           4      0.55%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
67611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total          730                      
67711390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.GETX            1731      0.00%      0.00%
67811390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.PUTX            1727      0.00%      0.00%
67911390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Memory_Data         1731      0.00%      0.00%
68011390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Memory_Ack         1727      0.00%      0.00%
68111390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.I.GETX          1731      0.00%      0.00%
68211390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M.PUTX          1727      0.00%      0.00%
68311390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.IM.Memory_Data         1731      0.00%      0.00%
68411390Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.MI.Memory_Ack         1727      0.00%      0.00%
68511390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Load              1185      0.00%      0.00%
68611390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ifetch            6413      0.00%      0.00%
68710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store              865      0.00%      0.00%
68811390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data              1731      0.00%      0.00%
68911390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Replacement         1727      0.00%      0.00%
69011390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Writeback_Ack         1727      0.00%      0.00%
69111390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Load             728      0.00%      0.00%
69210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch           730      0.00%      0.00%
69310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store            273      0.00%      0.00%
69411390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Load             457      0.00%      0.00%
69511390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Ifetch          5683      0.00%      0.00%
69610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store            592      0.00%      0.00%
69711390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Replacement         1727      0.00%      0.00%
69811390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.MI.Writeback_Ack         1727      0.00%      0.00%
69911390Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Data           1458      0.00%      0.00%
70010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data            273      0.00%      0.00%
7016167SN/A
7026167SN/A---------- End Simulation Statistics   ----------
703