Searched hist:52 (Results 826 - 850 of 992) sorted by relevance
/gem5/src/arch/sparc/ | ||
H A D | SConscript | 9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change. 3522:dc17a8e74141 Fri Nov 03 10:52:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> removed ua2005.cc since it's been obsorbed into the miscregfile, and added system.cc |
H A D | utility.hh | 4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge 3278:986122553077 Mon Oct 16 15:52:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Made sure the constructor for insts use ExtMachInst rather than MachInst, since otherwise the EXT_ASI field is lost. src/arch/sparc/isa/base.isa: src/arch/sparc/isa/formats/micro.isa: Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions. src/arch/sparc/utility.hh: Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used. |
/gem5/src/arch/sparc/isa/ | ||
H A D | base.isa | 11981:0c5089b6133d Wed Apr 26 05:52:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-sparc: Fix wrong indentation causing warnings for gcc 6 Change-Id: I94e15ae79f0e73692d882f62fd2b7bf45cf0c841 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 3278:986122553077 Mon Oct 16 15:52:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Made sure the constructor for insts use ExtMachInst rather than MachInst, since otherwise the EXT_ASI field is lost. src/arch/sparc/isa/base.isa: src/arch/sparc/isa/formats/micro.isa: Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions. src/arch/sparc/utility.hh: Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used. |
/gem5/src/arch/alpha/ | ||
H A D | utility.hh | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. 4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge |
H A D | isa_traits.hh | 9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change. |
/gem5/src/arch/sparc/isa/formats/mem/ | ||
H A D | util.isa | 11981:0c5089b6133d Wed Apr 26 05:52:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-sparc: Fix wrong indentation causing warnings for gcc 6 Change-Id: I94e15ae79f0e73692d882f62fd2b7bf45cf0c841 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem |
/gem5/src/python/m5/ | ||
H A D | __init__.py | 4553:fac59b75a87d Sun Jun 10 16:52:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Add a function to get a SimObject's memory mode and rework the set memory mode code to only go through the change if it is necessary 3101:6cce868ddaa6 Mon Sep 04 13:52:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Split config.py into multiple files. Some tweaking to deal with mutually recursive imports. |
/gem5/tests/configs/ | ||
H A D | memtest-ruby.py | 9827:f47274776aa0 Mon Aug 19 03:52:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> power: Add voltage domains to the clock domains This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs. 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
H A D | tsunami-simple-atomic-dual.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
H A D | tsunami-simple-atomic.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
H A D | tsunami-simple-timing.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
/gem5/src/mem/cache/prefetch/ | ||
H A D | Prefetcher.py | 13735:52ab3bab4f28 Thu Dec 13 17:33:00 EST 2018 Ivan Pizarro <ivan.pizarro@metempsy.com> mem-cache: Sandbox Based Optimal Offset Implementation Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation. Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862 Reviewed-on: https://gem5-review.googlesource.com/c/15095 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> 13427:72a3afac3e78 Sun Nov 11 09:52:00 EST 2018 Daniel <odanrc@yahoo.com.br> mem-cache: Make StridePrefetcher use Replacement Policies Previously StridePrefetcher was only able to use random replacement policy. This change allows all replacement policies to be applied to the pc table. Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14360 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | aarch64.isa | 13171:8d3d2b1f1ca3 Wed May 09 06:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: AArch64 Crypto AES This patch implements the AArch64 AES instructions from the Crypto extension. Change-Id: I9143041ec7e1c6a50dcad3f72d7d1b55d6f2d402 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13250 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/cpu/kvm/ | ||
H A D | base.hh | 11399:3f805b5c48ae Wed Mar 30 05:52:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> kvm: Add an option to force context sync on kvm entry/exit This changeset adds an option to force the kvm-based CPUs to always synchronize the gem5 thread context representation on entry/exit into the kernel. This is very useful for debugging. Unfortunately, it is also the only way to get reliable register contents when using remote gdb functionality. The long-term solution for the latter would be to implement a kvm-specific thread context. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Alexandru Dutu <alexandru.dutu@amd.com> 11363:f3f72c0ab03e Fri Nov 27 09:52:00 EST 2015 Andreas Sandberg <andreas@sandberg.pp.se> kvm: Shutdown KVM and disconnect performance counters on fork We can't/shouldn't use KVM after a fork since the child and parent probably point to the same VM. Knowing the exact effects of this is hard, but they are likely to be messy. We also disconnect the performance counters attached to the guest. This works around what seems to be a kernel bug where spurious SIGIOs get delivered to the forked child process. Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> [andreas.sandberg@arm.com: Fatal if entering KVM in child process ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/base/stats/ | ||
H A D | text.cc | 9828:4807b780ed0a Mon Aug 19 03:52:00 EDT 2013 Sascha Bischoff <sascha.bischoff@arm.com> stats: Fix issue when printing 2D vectors This patch addresses an issue with the text-based stats output which resulted in Vector2D stats being printed without subnames in the event that one of the dimensions was of length 1. This patch also fixes the total printing for the 2D vector. Previously totals were printed without explicitly stating that a total was being printed. This has been rectified in this patch. 4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and expose all of the relevant functionality to python. Clean up the mysql code while we're at it. |
/gem5/src/mem/ | ||
H A D | dram_ctrl.cc | 12969:52de9d619ce6 Fri Aug 04 06:11:00 EDT 2017 Matteo Andreozzi <Matteo.Andreozzi@arm.com> mem: Make DRAMCtrl a QoS-aware Memory Controller This patch is turning DRAMCtrl a QoS-aware Memory Controller with "no policy" as a default policy. Change-Id: I48163da8c8208498cf0398b07094cb840272507f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11973 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> 10216:52c869140fc2 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add DRAM cycle time This patch extends the current timing parameters with the DRAM cycle time. This is needed as the DRAMPower tool expects timestamps in DRAM cycles. At the moment we could get away with doing this in a post-processing step as the DRAMPower execution is separate from the simulation run. However, in the long run we want the tool to be called during the simulation, and then the cycle time is needed. 10215:52d46098c1b6 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Simplify DRAM response scheduling This patch simplifies the DRAM response scheduling based on the assumption that they are always returned in order. |
/gem5/src/sim/ | ||
H A D | pseudo_inst.cc | 5505:90d6811d5ea6 Fri Jul 11 11:52:00 EDT 2008 Nathan Binkert <nate@binkert.org> m5ops: clean up the m5ops stuff. - insert warnings for deprecated m5ops - reserve opcodes for Ali's stuff - remove code for stuff that has been deprecated forever - simplify m5op_alpha 5504:288b54c2fd8d Fri Jul 11 11:52:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: fix indentation and formatting of the pseudo insts. 4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and expose all of the relevant functionality to python. Clean up the mysql code while we're at it. |
H A D | byteswap.hh | 12521:da4f02f2e5d7 Wed Aug 02 04:52:00 EDT 2017 Chuan Zhu <chuan.zhu@arm.com> sim: Add gtoh/htog helpers that take an explicit endianness Add helper functions to swap between guest byte order and host byte order that take a guest endianness as a parameter. These functions are called htog and htog to be consistent with the helper functions that extract guest byte order from a compile time constant. Change-Id: Ie6be7dfd3b7a58ad6bfb57b25be5f85b5f425929 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/mips/isa/ | ||
H A D | operands.isa | 8449:4be49ad47c74 Tue Jul 05 19:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Define operand types with a ctype directly. |
/gem5/src/arch/mips/ | ||
H A D | SConscript | 9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change. |
/gem5/src/arch/x86/isa/ | ||
H A D | microasm.isa | 5667:78b94954f66a Sun Oct 12 20:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a handy way to access labels from the ROM in microcode. |
/gem5/src/cpu/ | ||
H A D | static_inst.cc | 4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method. Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. |
/gem5/src/arch/arm/ | ||
H A D | isa_traits.hh | 9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change. |
/gem5/src/arch/x86/ | ||
H A D | isa_traits.hh | 9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change. |
/gem5/src/systemc/core/ | ||
H A D | sc_main.cc | 13077:0037323cb4dd Wed Aug 22 20:52:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: If sc_main returns, don't do any more systemc stuff. When sc_main returns, clear out any pending work in the scheduler and also block the systemc kernel from doing actions which correspond with the start of simulation. It's most likely that work like oustanding timeouts might survive past the end of sc_main, especially if it never officially called sc_stop. It's also possible for sc_main to return and never actually call sc_start. In that case, the kernel should not call callbacks of the various objects (which may no longer even exist), or go through the initialization phase. If sc_main is never called at all, then the kernel's actions aren't gated. Change-Id: I49bf094be3283a92d846d2f3da224950bd893a5c Reviewed-on: https://gem5-review.googlesource.com/12249 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
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