16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2010, 2012 ARM Limited 37158Sgblack@eecs.umich.edu * All rights reserved 47158Sgblack@eecs.umich.edu * 57158Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67158Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77158Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87158Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97158Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107158Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117158Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127158Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137158Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Gabe Black 426019Shines@cs.fsu.edu * Stephen Hines 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARCH_ARM_ISA_TRAITS_HH__ 466019Shines@cs.fsu.edu#define __ARCH_ARM_ISA_TRAITS_HH__ 476019Shines@cs.fsu.edu 486019Shines@cs.fsu.edu#include "arch/arm/types.hh" 496214Snate@binkert.org#include "base/types.hh" 508542Sgblack@eecs.umich.edu#include "cpu/static_inst_fwd.hh" 516019Shines@cs.fsu.edu 527811Ssteve.reinhardt@amd.comnamespace LittleEndianGuest {} 536019Shines@cs.fsu.edu 546019Shines@cs.fsu.edunamespace ArmISA 556019Shines@cs.fsu.edu{ 566019Shines@cs.fsu.edu using namespace LittleEndianGuest; 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.edu StaticInstPtr decodeInst(ExtMachInst); 596019Shines@cs.fsu.edu 606019Shines@cs.fsu.edu const Addr PageShift = 12; 616019Shines@cs.fsu.edu const Addr PageBytes = ULL(1) << PageShift; 626019Shines@cs.fsu.edu const Addr Page_Mask = ~(PageBytes - 1); 636019Shines@cs.fsu.edu const Addr PageOffset = PageBytes - 1; 646019Shines@cs.fsu.edu 656019Shines@cs.fsu.edu 666019Shines@cs.fsu.edu //////////////////////////////////////////////////////////////////////// 676019Shines@cs.fsu.edu // 686019Shines@cs.fsu.edu // Translation stuff 696019Shines@cs.fsu.edu // 706019Shines@cs.fsu.edu 716019Shines@cs.fsu.edu const Addr PteShift = 3; 726019Shines@cs.fsu.edu const Addr NPtePageShift = PageShift - PteShift; 736019Shines@cs.fsu.edu const Addr NPtePage = ULL(1) << NPtePageShift; 746019Shines@cs.fsu.edu const Addr PteMask = NPtePage - 1; 756019Shines@cs.fsu.edu 766019Shines@cs.fsu.edu //// All 'Mapped' segments go through the TLB 776019Shines@cs.fsu.edu //// All other segments are translated by dropping the MSB, to give 786019Shines@cs.fsu.edu //// the corresponding physical address 796019Shines@cs.fsu.edu // User Segment - Mapped 806019Shines@cs.fsu.edu const Addr USegBase = ULL(0x0); 816019Shines@cs.fsu.edu const Addr USegEnd = ULL(0x7FFFFFFF); 826019Shines@cs.fsu.edu 836019Shines@cs.fsu.edu const unsigned VABits = 32; 846019Shines@cs.fsu.edu const unsigned PABits = 32; // Is this correct? 856019Shines@cs.fsu.edu const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 866019Shines@cs.fsu.edu const Addr VAddrUnImplMask = ~VAddrImplMask; 876019Shines@cs.fsu.edu inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 886019Shines@cs.fsu.edu inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 896019Shines@cs.fsu.edu inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.edu const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 926019Shines@cs.fsu.edu 9310037SARM gem5 Developers // Max. physical address range in bits supported by the architecture 9410037SARM gem5 Developers const unsigned MaxPhysAddrRange = 48; 9510037SARM gem5 Developers 966019Shines@cs.fsu.edu const int MachineBytes = 4; 976735Sgblack@eecs.umich.edu 986735Sgblack@eecs.umich.edu const uint32_t HighVecs = 0xFFFF0000; 996974Stjones1@inf.ed.ac.uk 1006974Stjones1@inf.ed.ac.uk // Memory accesses cannot be unaligned 1017654Sminkyu.jeong@arm.com const bool HasUnalignedMemAcc = true; 1027349SAli.Saidi@ARM.com 1039329Sdam.sunwoo@arm.com const bool CurThreadInfoImplemented = false; 1049329Sdam.sunwoo@arm.com const int CurThreadInfoReg = -1; 1059329Sdam.sunwoo@arm.com 1067400SAli.Saidi@ARM.com enum InterruptTypes 1077400SAli.Saidi@ARM.com { 1087400SAli.Saidi@ARM.com INT_RST, 1097400SAli.Saidi@ARM.com INT_ABT, 1107400SAli.Saidi@ARM.com INT_IRQ, 1117400SAli.Saidi@ARM.com INT_FIQ, 1128518Sgeoffrey.blake@arm.com INT_SEV, // Special interrupt for recieving SEV's 11310037SARM gem5 Developers INT_VIRT_IRQ, 11410037SARM gem5 Developers INT_VIRT_FIQ, 1157400SAli.Saidi@ARM.com NumInterruptTypes 1167400SAli.Saidi@ARM.com }; 1177811Ssteve.reinhardt@amd.com} // namespace ArmISA 1186019Shines@cs.fsu.edu 1196019Shines@cs.fsu.eduusing namespace ArmISA; 1206019Shines@cs.fsu.edu 1216019Shines@cs.fsu.edu#endif // __ARCH_ARM_ISA_TRAITS_HH__ 122