Searched hist:2014 (Results 476 - 500 of 1681) sorted by relevance
/gem5/src/dev/virtio/ | ||
H A D | pci.cc | 10602:3499de20ab3a Mon Dec 08 04:49:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> dev: Correctly transform packets into responses The VirtIO devices didn't correctly set the response flags in memory packets. This changeset adds the required Packet::makeResponse() calls. 10565:23593fdaadcd Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Remove redundant Packet::allocate calls This patch cleans up the packet memory allocation confusion. The data is always allocated at the requesting side, when a packet is created (or copied), and there is never a need for any device to allocate any space if it is merely responding to a paket. This behaviour is in line with how SystemC and TLM works as well, thus increasing interoperability, and matching established conventions. The redundant calls to Packet::allocate are removed, and the checks in the function are tightened up to make sure data is only ever allocated once. There are still some oddities in the packet copy constructor where we copy the data pointer if it is static (without ownership), and allocate new space if the data is dynamic (with ownership). The latter is being worked on further in a follow-on patch. 10559:62f5f7363197 Mon Nov 24 09:03:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Another round of static analysis fixups Mostly addressing uninitialised members. 10388:a26a20060ba3 Sat Sep 20 17:17:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> dev, pci: Implement basic VirtIO support This patch adds support for VirtIO over the PCI bus. It does so by providing the following new SimObjects: * VirtIODeviceBase - Abstract base class for VirtIO devices. * PciVirtIO - VirtIO PCI transport interface. A VirtIO device is hooked up to the guest system by adding a PciVirtIO device to the PCI bus and connecting it to a VirtIO device using the vio parameter. New VirtIO devices should inherit from VirtIODevice base and implementing one or more VirtQueues. The VirtQueues are usually device-specific and all derive from the VirtQueue class. Queues must be registered with the base class from the constructor since the device assumes that the number of queues stay constant. |
H A D | VirtIOBlock.py | 10390:28bc070b5a86 Sat Sep 20 17:17:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> dev: Add a VirtIO block device model |
H A D | block.cc | 10390:28bc070b5a86 Sat Sep 20 17:17:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> dev: Add a VirtIO block device model |
/gem5/src/cpu/simple/probes/ | ||
H A D | SimPoint.py | 10381:ab8b8601b6ff Sat Sep 20 17:17:00 EDT 2014 Dam Sunwoo <dam.sunwoo@arm.com> cpu: use probes infrastructure to do simpoint profiling Instead of having code embedded in cpu model to do simpoint profiling use the probes infrastructure to do it. |
H A D | simpoint.cc | 10417:710ee116eb68 Sat Sep 27 09:08:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use const StaticInstPtr references where possible This patch optimises the passing of StaticInstPtr by avoiding copying the reference-counting pointer. This avoids first incrementing and then decrementing the reference-counting pointer. 10381:ab8b8601b6ff Sat Sep 20 17:17:00 EDT 2014 Dam Sunwoo <dam.sunwoo@arm.com> cpu: use probes infrastructure to do simpoint profiling Instead of having code embedded in cpu model to do simpoint profiling use the probes infrastructure to do it. |
/gem5/build_opts/ | ||
H A D | X86_MESI_Two_Level | 10007:94d286db85c1 Sat Jan 04 01:03:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: rename MESI_CMP_directory to MESI_Two_Level This is because the next patch introduces a three level hierarchy. |
H A D | ALPHA | 10350:35241e33c38f Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> alpha: Stop using 'inorder' and rely entirely on 'minor' This patch avoids building the 'inorder' CPU model for any permutation of ALPHA, and also removes the ALPHA regressions using the 'inorder' CPU. The 'minor' CPU is already providing a broader test coverage. 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
/gem5/src/mem/ruby/structures/ | ||
H A D | DirectoryMemory.hh | 10522:13312d6e1caf Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: coherence protocols: remove data block from dirctory entry This patch removes the data block present in the directory entry structure of each protocol in gem5's mainline. Firstly, this is required for moving towards common set of memory controllers for classic and ruby memory systems. Secondly, the data block was being misused in several places. It was being used for having free access to the physical memory instead of calling on the memory controller. From now on, the directory controller will not have a direct visibility into the physical memory. The Memory Vector object now resides in the Memory Controller class. This also means that some significant changes are being made to the functional accesses in ruby. 10520:7740e0d97d48 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove sparse memory. In my opinion, it creates needless complications in rest of the code. Also, this structure hinders the move towards common set of code for physical memory controllers. 10441:5377550e1e15 Sat Oct 11 16:02:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: structures: coorect #ifndef macros in header files 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. |
H A D | TimerTable.hh | 10441:5377550e1e15 Sat Oct 11 16:02:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: structures: coorect #ifndef macros in header files 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. |
H A D | PerfectCacheMemory.hh | 10441:5377550e1e15 Sat Oct 11 16:02:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: structures: coorect #ifndef macros in header files 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. |
H A D | PersistentTable.hh | 10441:5377550e1e15 Sat Oct 11 16:02:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: structures: coorect #ifndef macros in header files 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. |
/gem5/src/cpu/minor/ | ||
H A D | func_unit.hh | 10417:710ee116eb68 Sat Sep 27 09:08:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use const StaticInstPtr references where possible This patch optimises the passing of StaticInstPtr by avoiding copying the reference-counting pointer. This avoids first incrementing and then decrementing the reference-counting pointer. 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
/gem5/src/cpu/ | ||
H A D | timing_expr.hh | 10417:710ee116eb68 Sat Sep 27 09:08:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use const StaticInstPtr references where possible This patch optimises the passing of StaticInstPtr by avoiding copying the reference-counting pointer. This avoids first incrementing and then decrementing the reference-counting pointer. 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/ | ||
H A D | system.terminal | 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. |
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/ | ||
H A D | simerr | 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. 10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA. |
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/ | ||
H A D | simerr | 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. 10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA. |
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/ | ||
H A D | stats.txt | 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. 10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches. 10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs. 10352:5f1f92bf76ee Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches. 10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ | ||
H A D | stats.txt | 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. 10526:0068ad93a67e Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to ruby 10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes 10124:46ccaf2cdef3 Thu Mar 20 10:16:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to ruby config scripts These updates to ruby regression stats are due to renaming piobus to iobus and dropping piobus in the se mode. 10093:9c55c0214404 Mon Feb 24 21:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to c0db268f811b 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes 10013:2e9e2fb2fa71 Fri Jan 10 17:19:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to ruby |
H A D | config.ini | 10526:0068ad93a67e Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to ruby 10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs. 10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes Also updates many out of date config files. 10229:aae7735450a9 Fri May 23 07:07:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: changes due to o3 cpu and ruby message buffer patches 10093:9c55c0214404 Mon Feb 24 21:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to c0db268f811b 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/ | ||
H A D | stats.txt | 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. 10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches. 10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs. 10352:5f1f92bf76ee Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches. 10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/ | ||
H A D | stats.txt | 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. 10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches. 10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs. 10352:5f1f92bf76ee Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches. 10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
/gem5/configs/ruby/ | ||
H A D | MESI_Two_Level.py | 10529:05b5a6cf3521 Thu Nov 06 06:42:00 EST 2014 Marc Orr <morr@cs.wisc.edu> x86 isa: This patch attempts an implementation at mwait. Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10300:ed3816dae6d5 Mon Sep 01 17:55:00 EDT 2014 Emilio Castillo <castilloe@unican.es>, Nilay Vaish <nilay@cs.wisc.edu> ruby: Fixes clock domains in configuration files This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10116:d61a59beb670 Mon Mar 17 18:40:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: remove piobus from protocols This patch removes the piobus from the protocol config files. The ports are now connected to the piobus in the Ruby.py file. 10090:4eec7bdde5b0 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: route all packets through ruby port Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch. 10007:94d286db85c1 Sat Jan 04 01:03:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: rename MESI_CMP_directory to MESI_Two_Level This is because the next patch introduces a three level hierarchy. |
/gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/ | ||
H A D | config.ini | 10549:6317351a288c Fri Nov 21 20:22:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Update stats for the new Linux delay port. 10540:45204db420c0 Mon Nov 17 03:16:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Update the stats for the x86 FS o3 boot test. 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. 10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs. 10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes Also updates many out of date config files. 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/ | ||
H A D | config.ini | 10517:ba51f8572571 Mon Nov 03 11:14:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences. 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. 10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs. 10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes Also updates many out of date config files. 10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/ | ||
H A D | config.ini | 10517:ba51f8572571 Mon Nov 03 11:14:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences. 10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes. 10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs. 10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes Also updates many out of date config files. 10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes 10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes |
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