stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Rename num_syscalls to numSyscalls in the reference stats.

The name of the stat was changed in the following change which broke all the
reference outputs.

commit 2367198921765848a4f5b3d020a7cc5776209f80
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:15 2017 -0500

syscall_emul: [PATCH 15/22] add clone/execve for threading and
multiprocess simulations

Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40
Reviewed-on: https://gem5-review.googlesource.com/2651
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Update stats to reflect recent changes to floats

Mostly just splitting out the floats ops and corresponding
reads/writes.

stats: Update to match classic memory changes

stats: update references

stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

stats: Update to match ARM ISA changes

stats: update for snoop filter tweak

stats: update stats to after GPU checkin

stats: bump stats to reflect ruby tester changes

stats: updates due to recent chagnesets

stats: Update stats to reflect cache changes

stats: arm: updates

stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.

stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.

stats: updates due to previous mmap and exit_group patches.

stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.

stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.

stats: Bump stats for the fixes, and mostly DRAM controller changes

stats: updates due to branch predictor warming

stats: update stats for ARMv8 changes

stats: update stats for cache occupancy and clock domain changes

stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

ARM: update stats for bp and squash fixes.

Stats: Update stats for RAS and LRU fixes.

all: Update stats for memory per master and total fix.

stats: update stats for no_value -> nan
Lots of accumulated older changes too.

ARM: Update stats for IT and conditional branch changes

ARM: Update stats for CBNZ fix.

stats: update stats for insts/ops and master id changes

SE/FS: Make both SE and FS tests available all the time.