1
2---------- Begin Simulation Statistics ----------
3sim_seconds                                  0.000003                      
4sim_ticks                                     2695000                      
5final_tick                                    2695000                      
6sim_freq                                 1000000000000                      
7host_inst_rate                                 427927                      
8host_op_rate                                   500175                      
9host_tick_rate                              250203319                      
10host_mem_usage                                 269284                      
11host_seconds                                     0.01                      
12sim_insts                                        4592                      
13sim_ops                                          5378                      
14system.voltage_domain.voltage                       1                      
15system.clk_domain.clock                          1000                      
16system.physmem.pwrStateResidencyTicks::UNDEFINED      2695000                      
17system.physmem.bytes_read::cpu.inst             18420                      
18system.physmem.bytes_read::cpu.data              4491                      
19system.physmem.bytes_read::total                22911                      
20system.physmem.bytes_inst_read::cpu.inst        18420                      
21system.physmem.bytes_inst_read::total           18420                      
22system.physmem.bytes_written::cpu.data           3648                      
23system.physmem.bytes_written::total              3648                      
24system.physmem.num_reads::cpu.inst               4605                      
25system.physmem.num_reads::cpu.data               1003                      
26system.physmem.num_reads::total                  5608                      
27system.physmem.num_writes::cpu.data               924                      
28system.physmem.num_writes::total                  924                      
29system.physmem.bw_read::cpu.inst           6834879406                      
30system.physmem.bw_read::cpu.data           1666419295                      
31system.physmem.bw_read::total              8501298701                      
32system.physmem.bw_inst_read::cpu.inst      6834879406                      
33system.physmem.bw_inst_read::total         6834879406                      
34system.physmem.bw_write::cpu.data          1353617811                      
35system.physmem.bw_write::total             1353617811                      
36system.physmem.bw_total::cpu.inst          6834879406                      
37system.physmem.bw_total::cpu.data          3020037106                      
38system.physmem.bw_total::total             9854916512                      
39system.pwrStateResidencyTicks::UNDEFINED      2695000                      
40system.cpu_clk_domain.clock                       500                      
41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED      2695000                      
42system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                      
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
50system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                      
51system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                      
52system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                      
53system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                      
54system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                      
55system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                      
56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                      
57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                      
58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                      
60system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                      
61system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                      
62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                      
63system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                      
64system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                      
65system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                      
66system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                      
67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                      
68system.cpu.dstage2_mmu.stage2_tlb.hits              0                      
69system.cpu.dstage2_mmu.stage2_tlb.misses            0                      
70system.cpu.dstage2_mmu.stage2_tlb.accesses            0                      
71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED      2695000                      
72system.cpu.dtb.walker.walks                         0                      
73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                      
74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                      
75system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                      
76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                      
77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                      
78system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                      
79system.cpu.dtb.walker.walkRequestOrigin::total            0                      
80system.cpu.dtb.inst_hits                            0                      
81system.cpu.dtb.inst_misses                          0                      
82system.cpu.dtb.read_hits                            0                      
83system.cpu.dtb.read_misses                          0                      
84system.cpu.dtb.write_hits                           0                      
85system.cpu.dtb.write_misses                         0                      
86system.cpu.dtb.flush_tlb                            0                      
87system.cpu.dtb.flush_tlb_mva                        0                      
88system.cpu.dtb.flush_tlb_mva_asid                   0                      
89system.cpu.dtb.flush_tlb_asid                       0                      
90system.cpu.dtb.flush_entries                        0                      
91system.cpu.dtb.align_faults                         0                      
92system.cpu.dtb.prefetch_faults                      0                      
93system.cpu.dtb.domain_faults                        0                      
94system.cpu.dtb.perms_faults                         0                      
95system.cpu.dtb.read_accesses                        0                      
96system.cpu.dtb.write_accesses                       0                      
97system.cpu.dtb.inst_accesses                        0                      
98system.cpu.dtb.hits                                 0                      
99system.cpu.dtb.misses                               0                      
100system.cpu.dtb.accesses                             0                      
101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED      2695000                      
102system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                      
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                      
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                      
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                      
106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                      
107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                      
108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                      
109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                      
110system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                      
111system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                      
112system.cpu.istage2_mmu.stage2_tlb.read_hits            0                      
113system.cpu.istage2_mmu.stage2_tlb.read_misses            0                      
114system.cpu.istage2_mmu.stage2_tlb.write_hits            0                      
115system.cpu.istage2_mmu.stage2_tlb.write_misses            0                      
116system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                      
117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                      
118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                      
119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                      
120system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                      
121system.cpu.istage2_mmu.stage2_tlb.align_faults            0                      
122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                      
123system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                      
124system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                      
125system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                      
126system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                      
127system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                      
128system.cpu.istage2_mmu.stage2_tlb.hits              0                      
129system.cpu.istage2_mmu.stage2_tlb.misses            0                      
130system.cpu.istage2_mmu.stage2_tlb.accesses            0                      
131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED      2695000                      
132system.cpu.itb.walker.walks                         0                      
133system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                      
134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                      
135system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                      
136system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                      
137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                      
138system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                      
139system.cpu.itb.walker.walkRequestOrigin::total            0                      
140system.cpu.itb.inst_hits                            0                      
141system.cpu.itb.inst_misses                          0                      
142system.cpu.itb.read_hits                            0                      
143system.cpu.itb.read_misses                          0                      
144system.cpu.itb.write_hits                           0                      
145system.cpu.itb.write_misses                         0                      
146system.cpu.itb.flush_tlb                            0                      
147system.cpu.itb.flush_tlb_mva                        0                      
148system.cpu.itb.flush_tlb_mva_asid                   0                      
149system.cpu.itb.flush_tlb_asid                       0                      
150system.cpu.itb.flush_entries                        0                      
151system.cpu.itb.align_faults                         0                      
152system.cpu.itb.prefetch_faults                      0                      
153system.cpu.itb.domain_faults                        0                      
154system.cpu.itb.perms_faults                         0                      
155system.cpu.itb.read_accesses                        0                      
156system.cpu.itb.write_accesses                       0                      
157system.cpu.itb.inst_accesses                        0                      
158system.cpu.itb.hits                                 0                      
159system.cpu.itb.misses                               0                      
160system.cpu.itb.accesses                             0                      
161system.cpu.workload.numSyscalls                    13                      
162system.cpu.pwrStateResidencyTicks::ON         2695000                      
163system.cpu.numCycles                             5391                      
164system.cpu.numWorkItemsStarted                      0                      
165system.cpu.numWorkItemsCompleted                    0                      
166system.cpu.committedInsts                        4592                      
167system.cpu.committedOps                          5378                      
168system.cpu.num_int_alu_accesses                  4624                      
169system.cpu.num_fp_alu_accesses                     16                      
170system.cpu.num_func_calls                         203                      
171system.cpu.num_conditional_control_insts          722                      
172system.cpu.num_int_insts                         4624                      
173system.cpu.num_fp_insts                            16                      
174system.cpu.num_int_register_reads                7572                      
175system.cpu.num_int_register_writes               2728                      
176system.cpu.num_fp_register_reads                   16                      
177system.cpu.num_fp_register_writes                   0                      
178system.cpu.num_cc_register_reads                16175                      
179system.cpu.num_cc_register_writes                2432                      
180system.cpu.num_mem_refs                          1965                      
181system.cpu.num_load_insts                        1027                      
182system.cpu.num_store_insts                        938                      
183system.cpu.num_idle_cycles                          0                      
184system.cpu.num_busy_cycles                       5391                      
185system.cpu.not_idle_fraction                        1                      
186system.cpu.idle_fraction                            0                      
187system.cpu.Branches                              1008                      
188system.cpu.op_class::No_OpClass                     0      0.00%      0.00%
189system.cpu.op_class::IntAlu                      3419     63.42%     63.42%
190system.cpu.op_class::IntMult                        4      0.07%     63.49%
191system.cpu.op_class::IntDiv                         0      0.00%     63.49%
192system.cpu.op_class::FloatAdd                       0      0.00%     63.49%
193system.cpu.op_class::FloatCmp                       0      0.00%     63.49%
194system.cpu.op_class::FloatCvt                       0      0.00%     63.49%
195system.cpu.op_class::FloatMult                      0      0.00%     63.49%
196system.cpu.op_class::FloatMultAcc                   0      0.00%     63.49%
197system.cpu.op_class::FloatDiv                       0      0.00%     63.49%
198system.cpu.op_class::FloatMisc                      0      0.00%     63.49%
199system.cpu.op_class::FloatSqrt                      0      0.00%     63.49%
200system.cpu.op_class::SimdAdd                        0      0.00%     63.49%
201system.cpu.op_class::SimdAddAcc                     0      0.00%     63.49%
202system.cpu.op_class::SimdAlu                        0      0.00%     63.49%
203system.cpu.op_class::SimdCmp                        0      0.00%     63.49%
204system.cpu.op_class::SimdCvt                        0      0.00%     63.49%
205system.cpu.op_class::SimdMisc                       0      0.00%     63.49%
206system.cpu.op_class::SimdMult                       0      0.00%     63.49%
207system.cpu.op_class::SimdMultAcc                    0      0.00%     63.49%
208system.cpu.op_class::SimdShift                      0      0.00%     63.49%
209system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.49%
210system.cpu.op_class::SimdSqrt                       0      0.00%     63.49%
211system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.49%
212system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.49%
213system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.49%
214system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.49%
215system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.49%
216system.cpu.op_class::SimdFloatMisc                  3      0.06%     63.55%
217system.cpu.op_class::SimdFloatMult                  0      0.00%     63.55%
218system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.55%
219system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.55%
220system.cpu.op_class::MemRead                     1027     19.05%     82.60%
221system.cpu.op_class::MemWrite                     922     17.10%     99.70%
222system.cpu.op_class::FloatMemRead                   0      0.00%     99.70%
223system.cpu.op_class::FloatMemWrite                 16      0.30%    100.00%
224system.cpu.op_class::IprAccess                      0      0.00%    100.00%
225system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
226system.cpu.op_class::total                       5391                      
227system.membus.snoop_filter.tot_requests             0                      
228system.membus.snoop_filter.hit_single_requests            0                      
229system.membus.snoop_filter.hit_multi_requests            0                      
230system.membus.snoop_filter.tot_snoops               0                      
231system.membus.snoop_filter.hit_single_snoops            0                      
232system.membus.snoop_filter.hit_multi_snoops            0                      
233system.membus.pwrStateResidencyTicks::UNDEFINED      2695000                      
234system.membus.trans_dist::ReadReq                5597                      
235system.membus.trans_dist::ReadResp               5608                      
236system.membus.trans_dist::WriteReq                913                      
237system.membus.trans_dist::WriteResp               913                      
238system.membus.trans_dist::LoadLockedReq            11                      
239system.membus.trans_dist::StoreCondReq             11                      
240system.membus.trans_dist::StoreCondResp            11                      
241system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9210                      
242system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                      
243system.membus.pkt_count::total                  13064                      
244system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18420                      
245system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                      
246system.membus.pkt_size::total                   26559                      
247system.membus.snoops                                0                      
248system.membus.snoopTraffic                          0                      
249system.membus.snoop_fanout::samples              6532                      
250system.membus.snoop_fanout::mean                    0                      
251system.membus.snoop_fanout::stdev                   0                      
252system.membus.snoop_fanout::underflows              0      0.00%      0.00%
253system.membus.snoop_fanout::0                    6532    100.00%    100.00%
254system.membus.snoop_fanout::1                       0      0.00%    100.00%
255system.membus.snoop_fanout::overflows               0      0.00%    100.00%
256system.membus.snoop_fanout::min_value               0                      
257system.membus.snoop_fanout::max_value               0                      
258system.membus.snoop_fanout::total                6532                      
259
260---------- End Simulation Statistics   ----------
261