stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2694500 # Number of ticks simulated 5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 685428 # Simulator instruction rate (inst/s) 8host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 400788339 # Simulator tick rate (ticks/s) 10host_mem_usage 292412 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) 38system.membus.trans_dist::ReadReq 5596 # Transaction distribution 39system.membus.trans_dist::ReadResp 5607 # Transaction distribution 40system.membus.trans_dist::WriteReq 913 # Transaction distribution 41system.membus.trans_dist::WriteResp 913 # Transaction distribution 42system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 43system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 44system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 45system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 47system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 48system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 49system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 50system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 51system.membus.snoops 0 # Total snoops (count) 52system.membus.snoop_fanout::samples 6531 # Request fanout histogram 53system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram 54system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 55system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 56system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 57system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 58system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 59system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 60system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram 61system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram 62system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63system.membus.snoop_fanout::min_value 4 # Request fanout histogram 64system.membus.snoop_fanout::max_value 5 # Request fanout histogram 65system.membus.snoop_fanout::total 6531 # Request fanout histogram 66system.cpu_clk_domain.clock 500 # Clock period in ticks 67system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 68system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 69system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 70system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 72system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 73system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 74system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 75system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 76system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 77system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 78system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 79system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 80system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 81system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 82system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 83system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 84system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 85system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 86system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 87system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 88system.cpu.dtb.inst_hits 0 # ITB inst hits 89system.cpu.dtb.inst_misses 0 # ITB inst misses 90system.cpu.dtb.read_hits 0 # DTB read hits 91system.cpu.dtb.read_misses 0 # DTB read misses 92system.cpu.dtb.write_hits 0 # DTB write hits 93system.cpu.dtb.write_misses 0 # DTB write misses 94system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 95system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 96system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 97system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 98system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 99system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 100system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 101system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 102system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 103system.cpu.dtb.read_accesses 0 # DTB read accesses 104system.cpu.dtb.write_accesses 0 # DTB write accesses 105system.cpu.dtb.inst_accesses 0 # ITB inst accesses 106system.cpu.dtb.hits 0 # DTB hits 107system.cpu.dtb.misses 0 # DTB misses 108system.cpu.dtb.accesses 0 # DTB accesses 109system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 110system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 111system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 112system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 113system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 114system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 119system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 120system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 121system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 122system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 123system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 124system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 125system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 126system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 127system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 128system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 129system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 130system.cpu.itb.inst_hits 0 # ITB inst hits 131system.cpu.itb.inst_misses 0 # ITB inst misses 132system.cpu.itb.read_hits 0 # DTB read hits 133system.cpu.itb.read_misses 0 # DTB read misses 134system.cpu.itb.write_hits 0 # DTB write hits 135system.cpu.itb.write_misses 0 # DTB write misses 136system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 137system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 139system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 140system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 141system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 142system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 143system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 144system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 145system.cpu.itb.read_accesses 0 # DTB read accesses 146system.cpu.itb.write_accesses 0 # DTB write accesses 147system.cpu.itb.inst_accesses 0 # ITB inst accesses 148system.cpu.itb.hits 0 # DTB hits 149system.cpu.itb.misses 0 # DTB misses 150system.cpu.itb.accesses 0 # DTB accesses 151system.cpu.workload.num_syscalls 13 # Number of system calls 152system.cpu.numCycles 5390 # number of cpu cycles simulated 153system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 154system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 155system.cpu.committedInsts 4591 # Number of instructions committed 156system.cpu.committedOps 5377 # Number of ops (including micro ops) committed 157system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 158system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 159system.cpu.num_func_calls 203 # number of times a function call or return occured 160system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 161system.cpu.num_int_insts 4624 # number of integer instructions 162system.cpu.num_fp_insts 16 # number of float instructions 163system.cpu.num_int_register_reads 7607 # number of times the integer registers were read 164system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 165system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 166system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 167system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read 168system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 169system.cpu.num_mem_refs 1965 # number of memory refs 170system.cpu.num_load_insts 1027 # Number of load instructions 171system.cpu.num_store_insts 938 # Number of store instructions 172system.cpu.num_idle_cycles 0 # Number of idle cycles 173system.cpu.num_busy_cycles 5390 # Number of busy cycles 174system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 175system.cpu.idle_fraction 0 # Percentage of idle cycles 176system.cpu.Branches 1007 # Number of branches fetched 177system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 178system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction 179system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 180system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 181system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 182system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 183system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 184system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 185system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 186system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 187system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 188system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 189system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 190system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 191system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 192system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 193system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 194system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 195system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 196system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 197system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 198system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 199system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 200system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 201system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 202system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 203system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction 204system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 205system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 206system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 207system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 208system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 209system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 210system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 211system.cpu.op_class::total 5390 # Class of executed instruction 212 213---------- End Simulation Statistics ---------- 214