1warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) 2info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 3warn: Sockets disabled, not accepting vnc client connections 4warn: Sockets disabled, not accepting terminal connections 5warn: Sockets disabled, not accepting gdb connections 6warn: ClockedObject: More than one power state change request encountered within the same simulation tick 7warn: ClockedObject: More than one power state change request encountered within the same simulation tick 8info: Using bootloader at address 0x10 9info: Using kernel entry physical address at 0x80008000 10info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 11warn: Existing EnergyCtrl, but no enabled DVFSHandler found. 12info: Entering event queue @ 0. Starting simulation... 13warn: Not doing anything for miscreg ACTLR 14warn: Not doing anything for write of miscreg ACTLR 15warn: The clidr register always reports 0 caches. 16warn: clidr LoUIS field of 0b001 to match current ARM implementations. 17warn: The csselr register isn't implemented. 18warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] 19warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] 20warn: instruction 'mcr dccmvau' unimplemented 21warn: instruction 'mcr icimvau' unimplemented 22warn: instruction 'mcr bpiallis' unimplemented 23warn: instruction 'mcr icialluis' unimplemented 24warn: instruction 'mcr dccimvac' unimplemented 25warn: Tried to read RealView I/O at offset 0x60 that doesn't exist 26warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 27warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 28warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 29warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 30warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 31warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 32warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 33warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 34warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 35info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 36info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 37info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 38info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 39info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 40info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 41info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 42warn: Not doing anything for miscreg ACTLR 43warn: Not doing anything for write of miscreg ACTLR 44warn: instruction 'mcr bpiall' unimplemented 45info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 46info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 47warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] 48info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 49info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 50info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 51info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 52info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 53info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 54warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] 55warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] 56warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] 57warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] 58warn: Returning zero for read from miscreg pmcr 59warn: Ignoring write to miscreg pmcntenclr 60warn: Ignoring write to miscreg pmintenclr 61warn: Ignoring write to miscreg pmovsr 62warn: Ignoring write to miscreg pmcr 63warn: Ignoring write to miscreg pmcntenclr 64warn: Ignoring write to miscreg pmintenclr 65warn: Ignoring write to miscreg pmovsr 66warn: Ignoring write to miscreg pmcr 67