1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
30#define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
31
32#include <unordered_map>
33
34#include "mem/ruby/common/Address.hh"
35#include "mem/ruby/protocol/AccessPermission.hh"
36
37template<class ENTRY>
38struct PerfectCacheLineState
39{
40    PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
41    AccessPermission m_permission;
42    ENTRY m_entry;
43};
44
45template<class ENTRY>
46inline std::ostream&
47operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
48{
49    return out;
50}
51
52template<class ENTRY>
53class PerfectCacheMemory
54{
55  public:
56    PerfectCacheMemory();
57
58    // tests to see if an address is present in the cache
59    bool isTagPresent(Addr address) const;
60
61    // Returns true if there is:
62    //   a) a tag match on this address or there is
63    //   b) an Invalid line in the same cache "way"
64    bool cacheAvail(Addr address) const;
65
66    // find an Invalid entry and sets the tag appropriate for the address
67    void allocate(Addr address);
68
69    void deallocate(Addr address);
70
71    // Returns with the physical address of the conflicting cache line
72    Addr cacheProbe(Addr newAddress) const;
73
74    // looks an address up in the cache
75    ENTRY* lookup(Addr address);
76    const ENTRY* lookup(Addr address) const;
77
78    // Get/Set permission of cache block
79    AccessPermission getPermission(Addr address) const;
80    void changePermission(Addr address, AccessPermission new_perm);
81
82    // Print cache contents
83    void print(std::ostream& out) const;
84
85  private:
86    // Private copy constructor and assignment operator
87    PerfectCacheMemory(const PerfectCacheMemory& obj);
88    PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
89
90    // Data Members (m_prefix)
91    std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
92};
93
94template<class ENTRY>
95inline std::ostream&
96operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
97{
98    obj.print(out);
99    out << std::flush;
100    return out;
101}
102
103template<class ENTRY>
104inline
105PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
106{
107}
108
109// tests to see if an address is present in the cache
110template<class ENTRY>
111inline bool
112PerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const
113{
114    return m_map.count(makeLineAddress(address)) > 0;
115}
116
117template<class ENTRY>
118inline bool
119PerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const
120{
121    return true;
122}
123
124// find an Invalid or already allocated entry and sets the tag
125// appropriate for the address
126template<class ENTRY>
127inline void
128PerfectCacheMemory<ENTRY>::allocate(Addr address)
129{
130    PerfectCacheLineState<ENTRY> line_state;
131    line_state.m_permission = AccessPermission_Invalid;
132    line_state.m_entry = ENTRY();
133    m_map[makeLineAddress(address)] = line_state;
134}
135
136// deallocate entry
137template<class ENTRY>
138inline void
139PerfectCacheMemory<ENTRY>::deallocate(Addr address)
140{
141    m_map.erase(makeLineAddress(address));
142}
143
144// Returns with the physical address of the conflicting cache line
145template<class ENTRY>
146inline Addr
147PerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const
148{
149    panic("cacheProbe called in perfect cache");
150    return newAddress;
151}
152
153// looks an address up in the cache
154template<class ENTRY>
155inline ENTRY*
156PerfectCacheMemory<ENTRY>::lookup(Addr address)
157{
158    return &m_map[makeLineAddress(address)].m_entry;
159}
160
161// looks an address up in the cache
162template<class ENTRY>
163inline const ENTRY*
164PerfectCacheMemory<ENTRY>::lookup(Addr address) const
165{
166    return &m_map[makeLineAddress(address)].m_entry;
167}
168
169template<class ENTRY>
170inline AccessPermission
171PerfectCacheMemory<ENTRY>::getPermission(Addr address) const
172{
173    return m_map[makeLineAddress(address)].m_permission;
174}
175
176template<class ENTRY>
177inline void
178PerfectCacheMemory<ENTRY>::changePermission(Addr address,
179                                            AccessPermission new_perm)
180{
181    Addr line_address = makeLineAddress(address);
182    PerfectCacheLineState<ENTRY>& line_state = m_map[line_address];
183    line_state.m_permission = new_perm;
184}
185
186template<class ENTRY>
187inline void
188PerfectCacheMemory<ENTRY>::print(std::ostream& out) const
189{
190}
191
192#endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
193